September 2015 - U-Boot

[U-Boot] [PATCH] ARMv7/ls1021a: move ns_access to common file
by Gong Qianyu 09 Sep '15

09 Sep '15

From: Mingkai Hu <Mingkai.Hu(a)freescale.com> Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch speicific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu(a)freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/ns_access.h | 84 ++++++++++++++++++++- board/freescale/common/Makefile | 2 +- board/freescale/common/ns_access.c | 7 +- board/freescale/common/ns_access.h | 13 ++++ board/freescale/ls1021aqds/ls1021aqds.c | 101 ++------------------------ board/freescale/ls1021atwr/ls1021atwr.c | 91 +---------------------- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- 8 files changed, 115 insertions(+), 187 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index b53f699..45a63a2 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -113,6 +113,88 @@ struct csu_ns_dev { uint32_t val; }; -void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; #endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 87d0578..51d2814 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -71,7 +71,7 @@ obj-$(CONFIG_P4080DS) += p_corenet/ obj-$(CONFIG_P5020DS) += p_corenet/ obj-$(CONFIG_P5040DS) += p_corenet/ -obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o +obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o ifdef CONFIG_SECURE_BOOT obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index d7de982..58a181b 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/arch/ns_access.h> -void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; @@ -28,3 +28,8 @@ void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) out_be32(reg, val); } } + +void enable_layerscape_ns_access(void) +{ + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +} diff --git a/board/freescale/common/ns_access.h b/board/freescale/common/ns_access.h new file mode 100644 index 0000000..7eb06bd --- /dev/null +++ b/board/freescale/common/ns_access.h @@ -0,0 +1,13 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __NS_ACCESS_H__ +#define __NS_ACCESS_H__ + +void enable_layerscape_ns_access(void); + +#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 655fc64..9bcdc9cc 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -8,7 +8,6 @@ #include <i2c.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> -#include <asm/arch/ns_access.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> @@ -21,6 +20,7 @@ #include <spl.h> #include <fsl_devdis.h> +#include "../common/ns_access.h" #include "../common/sleep.h" #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -56,92 +56,6 @@ enum { GE1_CLK125, }; -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; -#endif - int checkboard(void) { #ifndef CONFIG_QSPI_BOOT @@ -382,9 +296,8 @@ void board_init_f(ulong dummy) dram_init(); /* Allow OCRAM access permission as R/W */ -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(&ns_dev[4], 1); - enable_devices_ns_access(&ns_dev[7], 1); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); @@ -602,8 +515,8 @@ int board_init(void) ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif #ifdef CONFIG_U_QE @@ -627,8 +540,8 @@ void board_sleep_prepare(void) } -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif } #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 228dbf8..3132997 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -25,6 +25,7 @@ #include <fsl_devdis.h> #include <spl.h> #include "../common/sleep.h" +#include "../common/ns_access.h" #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif @@ -69,92 +70,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PIN_QE_LCD_MUX_LCD 0x0 #define PIN_QE_LCD_MUX_QE 0x1 -#ifdef CONFIG_LS102XA_NS_ACCESS -static struct csu_ns_dev ns_dev[] = { - { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, - { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, - { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, - { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, - { CSU_CSLX_OCRAM, CSU_ALL_RW }, - { CSU_CSLX_GIC, CSU_ALL_RW }, - { CSU_CSLX_PCIE1, CSU_ALL_RW }, - { CSU_CSLX_OCRAM2, CSU_ALL_RW }, - { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, - { CSU_CSLX_PCIE2, CSU_ALL_RW }, - { CSU_CSLX_SATA, CSU_ALL_RW }, - { CSU_CSLX_USB3, CSU_ALL_RW }, - { CSU_CSLX_SERDES, CSU_ALL_RW }, - { CSU_CSLX_QDMA, CSU_ALL_RW }, - { CSU_CSLX_LPUART2, CSU_ALL_RW }, - { CSU_CSLX_LPUART1, CSU_ALL_RW }, - { CSU_CSLX_LPUART4, CSU_ALL_RW }, - { CSU_CSLX_LPUART3, CSU_ALL_RW }, - { CSU_CSLX_LPUART6, CSU_ALL_RW }, - { CSU_CSLX_LPUART5, CSU_ALL_RW }, - { CSU_CSLX_DSPI2, CSU_ALL_RW }, - { CSU_CSLX_DSPI1, CSU_ALL_RW }, - { CSU_CSLX_QSPI, CSU_ALL_RW }, - { CSU_CSLX_ESDHC, CSU_ALL_RW }, - { CSU_CSLX_2D_ACE, CSU_ALL_RW }, - { CSU_CSLX_IFC, CSU_ALL_RW }, - { CSU_CSLX_I2C1, CSU_ALL_RW }, - { CSU_CSLX_USB2, CSU_ALL_RW }, - { CSU_CSLX_I2C3, CSU_ALL_RW }, - { CSU_CSLX_I2C2, CSU_ALL_RW }, - { CSU_CSLX_DUART2, CSU_ALL_RW }, - { CSU_CSLX_DUART1, CSU_ALL_RW }, - { CSU_CSLX_WDT2, CSU_ALL_RW }, - { CSU_CSLX_WDT1, CSU_ALL_RW }, - { CSU_CSLX_EDMA, CSU_ALL_RW }, - { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, - { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, - { CSU_CSLX_DDR, CSU_ALL_RW }, - { CSU_CSLX_QUICC, CSU_ALL_RW }, - { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, - { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, - { CSU_CSLX_SFP, CSU_ALL_RW }, - { CSU_CSLX_TMU, CSU_ALL_RW }, - { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, - { CSU_CSLX_RESERVED0, CSU_ALL_RW }, - { CSU_CSLX_ETSEC1, CSU_ALL_RW }, - { CSU_CSLX_SEC5_5, CSU_ALL_RW }, - { CSU_CSLX_ETSEC3, CSU_ALL_RW }, - { CSU_CSLX_ETSEC2, CSU_ALL_RW }, - { CSU_CSLX_GPIO2, CSU_ALL_RW }, - { CSU_CSLX_GPIO1, CSU_ALL_RW }, - { CSU_CSLX_GPIO4, CSU_ALL_RW }, - { CSU_CSLX_GPIO3, CSU_ALL_RW }, - { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, - { CSU_CSLX_CSU, CSU_ALL_RW }, - { CSU_CSLX_ASRC, CSU_ALL_RW }, - { CSU_CSLX_SPDIF, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, - { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, - { CSU_CSLX_SAI2, CSU_ALL_RW }, - { CSU_CSLX_SAI1, CSU_ALL_RW }, - { CSU_CSLX_SAI4, CSU_ALL_RW }, - { CSU_CSLX_SAI3, CSU_ALL_RW }, - { CSU_CSLX_FTM2, CSU_ALL_RW }, - { CSU_CSLX_FTM1, CSU_ALL_RW }, - { CSU_CSLX_FTM4, CSU_ALL_RW }, - { CSU_CSLX_FTM3, CSU_ALL_RW }, - { CSU_CSLX_FTM6, CSU_ALL_RW }, - { CSU_CSLX_FTM5, CSU_ALL_RW }, - { CSU_CSLX_FTM8, CSU_ALL_RW }, - { CSU_CSLX_FTM7, CSU_ALL_RW }, - { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, - { CSU_CSLX_EPU, CSU_ALL_RW }, - { CSU_CSLX_GDI, CSU_ALL_RW }, - { CSU_CSLX_DDI, CSU_ALL_RW }, - { CSU_CSLX_RESERVED1, CSU_ALL_RW }, - { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, - { CSU_CSLX_RESERVED2, CSU_ALL_RW }, -}; -#endif - struct cpld_data { u8 cpld_ver; /* cpld revision */ u8 cpld_ver_sub; /* cpld sub revision */ @@ -637,8 +552,8 @@ int board_init(void) ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); -#ifdef CONFIG_LS102XA_NS_ACCESS - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); #endif #ifdef CONFIG_U_QE diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b44f326..0234e32 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -561,7 +561,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 7dcb719..f561cbe 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -409,7 +409,7 @@ #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm/ls102xa: Add STANDBY implement based on PSCI
by Dongsheng Wang 09 Sep '15

09 Sep '15

From: Wang Dongsheng <dongsheng.wang(a)freescale.com> Base on PSCI services, implement CPU_SUSPEND for ls102xa platform. Signed-off-by: Wang Dongsheng <dongsheng.wang(a)freescale.com> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index cf5cd48..1bc7e45 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -14,10 +14,13 @@ #define SCFG_CORE0_SFT_RST 0x130 #define SCFG_CORESRENCR 0x204 +#define SCFG_CLUSTERPMCR 0x904 #define DCFG_CCSR_BRR 0x0E4 #define DCFG_CCSR_SCRATCHRW1 0x200 +#define RCPM_POWMGTCSR 0x130 + .pushsection ._secure.text, "ax" .arch_extension sec @@ -111,6 +114,41 @@ psci_cpu_off: 1: wfi b 1b +.globl psci_cpu_suspend +psci_cpu_suspend: + push {lr} + + @ Get Power State + mov r0, r2, lsr #16 + ands r0, r0, #1 + bne out + + @ STANDBY Power State + @ Get RCPM base address + movw r0, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff) + movt r0, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16) + + @ Get POWMGTCSR + ldr r1, [r0, #RCPM_POWMGTCSR] + rev r1, r1 + + movw r2, #0 + movt r2, #(1 << 4) + + orr r1, r1, r2 + rev r1, r1 + str r1, [r0, #RCPM_POWMGTCSR] + + dsb + wfi + +out: + @ Return + mov r0, #ARM_PSCI_RET_SUCCESS + + pop {lr} + bx lr + .globl psci_arch_init psci_arch_init: mov r6, lr @@ -121,6 +159,6 @@ psci_arch_init: bx r6 - .globl psci_text_end +.globl psci_text_end psci_text_end: .popsection diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index c55cdef..e314c35 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -32,6 +32,7 @@ #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) -- 2.1.0.27.g96db324

1 0

[U-Boot] [PATCH 0/5] nios2: add device tree control of U-Boot
by Thomas Chou 09 Sep '15

09 Sep '15

These patches add device tree control of U-Boot to nios2 boards. In case of separated device tree blob, the blob is relocated from the end of u-boot-dtb.bin image. Thomas Chou (5): nios2: permit device tree control of U-Boot nios2: enable device tree control of U-Boot nios2: revert _end symbol in link script nios2: initialize stack earlier in startup nios2: relocate dtb for separated device tree arch/Kconfig | 1 + arch/nios2/cpu/fdt.c | 20 ++++- arch/nios2/cpu/start.S | 55 +++++++------ arch/nios2/cpu/u-boot.lds | 16 +++- arch/nios2/dts/.gitignore | 1 + arch/nios2/dts/3c120_devboard.dts | 164 +++++++++++++++++++++++++++++++++++++ arch/nios2/dts/Makefile | 11 +++ arch/nios2/dts/include/dt-bindings | 1 + configs/nios2-generic_defconfig | 2 + 9 files changed, 244 insertions(+), 27 deletions(-) create mode 100644 arch/nios2/dts/.gitignore create mode 100644 arch/nios2/dts/3c120_devboard.dts create mode 100644 arch/nios2/dts/Makefile create mode 120000 arch/nios2/dts/include/dt-bindings -- 2.1.4

4 78

[U-Boot] [PATCH] arm: socfpga: mcvevk: Update DRAM clock to 400MHz
by Marek Vasut 08 Sep '15

08 Sep '15

The MCV SoM has DDR3-1600 DRAMs on it, update the DRAM speed to 400MHz to make use of these DRAMs completely. Signed-off-by: Marek Vasut <marex(a)denx.de> --- board/denx/mcvevk/qts/iocsr_config.h | 128 +++++++++++++++++------------------ board/denx/mcvevk/qts/pll_config.h | 6 +- board/denx/mcvevk/qts/sdram_config.h | 36 +++++----- 3 files changed, 85 insertions(+), 85 deletions(-) diff --git a/board/denx/mcvevk/qts/iocsr_config.h b/board/denx/mcvevk/qts/iocsr_config.h index e40274f..3021830 100644 --- a/board/denx/mcvevk/qts/iocsr_config.h +++ b/board/denx/mcvevk/qts/iocsr_config.h @@ -130,7 +130,7 @@ const unsigned long iocsr_scan_chain2_table[] = { }; const unsigned long iocsr_scan_chain3_table[] = { - 0x0CC20D80, + 0x0C420D80, 0x0C3000FF, 0x0A804001, 0x07900000, @@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00001000, 0xA0000034, 0x0D000001, - 0xC0680618, - 0x45034071, - 0x1A681A01, - 0x806180D0, - 0x34071C06, - 0x01A034D0, - 0x380D0000, - 0x0820680E, - 0x034D0340, + 0xC0680A28, + 0x45034030, + 0x12481A01, + 0x80A280D0, + 0x34030C06, + 0x01A01450, + 0x280D0000, + 0x30C0680A, + 0x02490340, 0xD000001A, - 0x0680E380, + 0x0680A280, 0x10040000, 0x00200000, 0x10040000, @@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00001000, 0xA0000034, 0x0D000001, - 0xC0680618, - 0x45034071, - 0x1A681A01, - 0x80E380D0, - 0x34071C06, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, 0x01A00040, - 0x380D0002, - 0x71C0680E, - 0x034D0340, - 0xD01A681A, - 0x06806180, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD00A281A, + 0x0680A280, 0x10040000, 0x00200000, 0x10040000, @@ -285,7 +285,7 @@ const unsigned long iocsr_scan_chain3_table[] = { 0xAA0D4000, 0x01C3A800, 0xAA0D4000, - 0x01C3A800, + 0x01C3A890, 0xAA0D4000, 0x01C3A800, 0x00040100, @@ -313,7 +313,7 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x2A835000, 0x0070EA00, 0x2A835000, - 0x0070EA00, + 0x0070EA24, 0x2A835000, 0x0070EA00, 0x00010040, @@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x04864000, - 0x69A47A01, - 0x932CA3DA, - 0xF459651E, - 0x03549248, + 0x18864000, + 0x49247A06, + 0x9A28A3D7, + 0xF511451E, + 0x0356E388, 0x821A0000, 0x0000D000, - 0x030C0680, - 0xDA69A47A, - 0x1E9228A3, - 0x48F45965, - 0x000354D3, + 0x05140680, + 0xD749247A, + 0x1E9A28A3, + 0x88F51145, + 0x00034EE3, 0x00080000, 0x00001000, 0x00080200, @@ -359,7 +359,7 @@ const unsigned long iocsr_scan_chain3_table[] = { 0xAA0D4000, 0x01C3A800, 0xAA0D4000, - 0x01C3A800, + 0x01C3A890, 0xAA0D4000, 0x01C3A800, 0x00040000, @@ -387,7 +387,7 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x2A835000, 0x0070EA00, 0x2A835000, - 0x0070EA00, + 0x0070EA24, 0x2A835000, 0x0070EA00, 0x00015000, @@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x14864000, - 0x59647A05, - 0xE228A3D6, - 0xF459651E, - 0x034CD348, - 0x821A0041, + 0x18864000, + 0x49247A06, + 0xEBCF23D7, + 0xF611451E, + 0x034E9248, + 0x821A038E, 0x0000D000, 0x00000680, - 0xD669A47A, - 0x1E9228A3, - 0x48F45965, - 0x00034492, + 0xD749247A, + 0x1E9BCF23, + 0x88F61145, + 0x00034EE3, 0x00080000, 0x00001000, 0x00080000, @@ -433,7 +433,7 @@ const unsigned long iocsr_scan_chain3_table[] = { 0xAA0D4000, 0x01C3A800, 0xAA0D4000, - 0x01C3A800, + 0x01C3A890, 0xAA0D4000, 0x01C3A800, 0x00040000, @@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x14864000, - 0x59647A05, - 0x9228A3D6, - 0xF459651E, - 0x034CD348, + 0x18864000, + 0x49247A06, + 0x9A28A3D7, + 0xF431451E, + 0x034E9248, 0x821A0000, 0x0000D000, 0x00000680, - 0xD659647A, - 0x1E932CA3, - 0x48F65965, - 0x00034CD3, + 0xD749247A, + 0x1E9A28A3, + 0x88F61145, + 0x000356E3, 0x00080000, 0x00001000, 0x00080000, @@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F1690D, 0x1A041414, 0x00D00000, - 0x14864000, - 0x59647A05, - 0x932CA3D6, - 0xF659651E, - 0x034CD348, + 0x08864000, + 0x49247A02, + 0xEBCF23DB, + 0xF431451E, + 0x0356E388, 0x821A0000, 0x0000D000, 0x00000680, - 0xD669A47A, - 0x1E9228A3, - 0x48F45965, - 0x00034CD3, + 0xD749247A, + 0x1EEBCF23, + 0x88F43E79, + 0x000356A2, 0x00080000, 0x00001000, 0x00080000, diff --git a/board/denx/mcvevk/qts/pll_config.h b/board/denx/mcvevk/qts/pll_config.h index aff4648..b718b39 100644 --- a/board/denx/mcvevk/qts/pll_config.h +++ b/board/denx/mcvevk/qts/pll_config.h @@ -45,8 +45,8 @@ #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 @@ -63,7 +63,7 @@ #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 #define CONFIG_HPS_CLK_EMAC1_HZ 1953125 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h index cf9d1d3..30c4d7d 100644 --- a/board/denx/mcvevk/qts/sdram_config.h +++ b/board/denx/mcvevk/qts/sdram_config.h @@ -34,19 +34,19 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 @@ -132,7 +132,7 @@ #define ENABLE_SUPER_QUICK_CALIBRATION 0 #define IO_DELAY_PER_DCHAIN_TAP 25 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#define IO_DELAY_PER_OPA_TAP 375 +#define IO_DELAY_PER_OPA_TAP 312 #define IO_DLL_CHAIN_LENGTH 8 #define IO_DQDQS_OUT_PHASE_MAX 0 #define IO_DQS_EN_DELAY_MAX 31 @@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32 @@ -160,10 +160,10 @@ #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 -#define TINIT_CNTR0_VAL 82 +#define TINIT_CNTR0_VAL 99 #define TINIT_CNTR1_VAL 32 #define TINIT_CNTR2_VAL 32 -#define TRESET_CNTR0_VAL 82 +#define TRESET_CNTR0_VAL 99 #define TRESET_CNTR1_VAL 99 #define TRESET_CNTR2_VAL 10 @@ -171,14 +171,14 @@ const u32 ac_rom_init[] = { 0x20700000, 0x20780000, - 0x10080221, - 0x10080320, + 0x10080421, + 0x10080520, 0x10090044, 0x100a0008, 0x100b0000, 0x10380400, - 0x10080241, - 0x100802c0, + 0x10080441, + 0x100804c0, 0x100a0024, 0x10090010, 0x100b0000, -- 2.1.4

1 1

[U-Boot] [PATCH 1/2] mx6slevk: Remove CONFIG_SPL_FAT_SUPPORT
by Fabio Estevam 08 Sep '15

08 Sep '15

If the SD card does not contain the u-boot.img then we get the following error: U-Boot SPL 2015.10-rc2-23947-g7ad5930 (Sep 08 2015 - 14:10:29) ** Partition 1 not valid on device 0 ** spl_register_fat_device: fat register err - -1 spl_load_image_fat: error reading image u-boot.img, err - -1 Remove CONFIG_SPL_FAT_SUPPORT and let CONFIG_SPL_MMC_SUPPORT do the job. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx6slevk.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 04d53a7..c86710d 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -14,7 +14,6 @@ #ifdef CONFIG_SPL #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT #include "imx6_spl.h" #endif -- 1.9.1

1 1

[U-Boot] [PATCH 0/3] Introduce TPM driver model and STMicroelectronics ST33ZP24 TPMs
by Christophe Ricard 08 Sep '15

08 Sep '15

Hi, This patch serie introduce TPM driver model allowing to instantiate a TPM using U_BOOT_DEVICE macro for platform_data or device tree. As an information, there is no TCG transport protocol official specification for i2c for TPM1.2. The TPM uclass allows to support different kind of bus (LPC, I2C, SPI) keeping the TPM command duration in common. Also, this serie introduce TPM1.2 from STMicroelectronics ST33ZP24 with I2C and SPI support. It has been ported from existing Linux drivers. This has been tested on Beagleboard xM. Best Regards Christophe Christophe Ricard (3): tpm: Move tpm_tis_i2c to tpm_i2c_infineon tpm: Initial work to introduce TPM driver model tpm: Add st33zp24 tpm with i2c and spi phy README | 23 +- drivers/tpm/Makefile | 5 +- drivers/tpm/st33zp24/Makefile | 7 + drivers/tpm/st33zp24/i2c.c | 226 +++++++++++ drivers/tpm/st33zp24/spi.c | 286 ++++++++++++++ drivers/tpm/st33zp24/st33zp24.c | 454 ++++++++++++++++++++++ drivers/tpm/st33zp24/st33zp24.h | 29 ++ drivers/tpm/tpm.c | 275 +++---------- drivers/tpm/{tpm_tis_i2c.c => tpm_i2c_infineon.c} | 271 ++++++++----- drivers/tpm/tpm_private.h | 23 +- include/dm/platform_data/st33zp24_i2c.h | 28 ++ include/dm/platform_data/st33zp24_spi.h | 30 ++ include/dm/platform_data/tpm_i2c_infineon.h | 23 ++ include/dm/uclass-id.h | 1 + include/fdtdec.h | 5 +- lib/fdtdec.c | 2 + 16 files changed, 1351 insertions(+), 337 deletions(-) create mode 100644 drivers/tpm/st33zp24/Makefile create mode 100644 drivers/tpm/st33zp24/i2c.c create mode 100644 drivers/tpm/st33zp24/spi.c create mode 100644 drivers/tpm/st33zp24/st33zp24.c create mode 100644 drivers/tpm/st33zp24/st33zp24.h rename drivers/tpm/{tpm_tis_i2c.c => tpm_i2c_infineon.c} (70%) create mode 100644 include/dm/platform_data/st33zp24_i2c.h create mode 100644 include/dm/platform_data/st33zp24_spi.h create mode 100644 include/dm/platform_data/tpm_i2c_infineon.h -- 2.1.4

2 16

[U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
by Chin Liang See 08 Sep '15

08 Sep '15

Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> --- Changes for v2 - remove frequency set before calibration - introducing previous_hz to store requested frequency - prevent calibration run when request same frequency --- drivers/spi/cadence_qspi.c | 19 ++++++++++++------- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..23c88d5 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,7 +37,7 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -46,6 +46,10 @@ static int spi_calibration(struct udevice *bus) unsigned int idcode = 0, temp = 0; int err = 0, i, range_lo = -1, range_hi = -1; + /* if calibrated frequency same as reqeusted, skip it */ + if (priv->qspi_calibrated_hz == hz) + return 0; + /* start with slowest clock (1 MHz) */ cadence_spi_write_speed(bus, 1000000); @@ -64,7 +68,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +115,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -126,14 +130,15 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + if (priv->previous_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..2912e36 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ -- 1.7.7.4

3 4

[U-Boot] [PATCH 4/4] arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash
by Chin Liang See 08 Sep '15

08 Sep '15

With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Reviewed-by: Marek Vasut <marex(a)denx.de> --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9650eb0..04e5695 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -86,7 +86,7 @@ #size-cells = <1>; compatible = "n25q00"; reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + spi-max-frequency = <100000000>; m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ -- 1.7.7.4

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[U-Boot] [PATCH 1/2] arm: socfpga: mmc: Enable calibration for drvsel and smpsel
by Chin Liang See 08 Sep '15

08 Sep '15

Enable SDMMC calibration to determine the best setting for drvsel and smpsel. It will be triggered whenever there is a change of card frequency and bus width. This is to ensure reliable transmission between the controller and the card. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/mmc/socfpga_dw_mmc.c | 187 ++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 180 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index eb69aed..15e537c 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -11,25 +11,140 @@ #include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> +#include "mmc_private.h" static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; -static void socfpga_dwmci_clksel(struct dwmci_host *host) +#define CAL_ROWS 7 +#define CAL_COLS 8 + +/* + * This function determines the largest rectangle filled with 1's and returns + * the middle. This functon can be optimized, for example using the algorithm + * from http://www.drdobbs.com/database/the-maximal-rectangle-problem/184410529 + * It currently takes less than 1ms, while creating the input data takes ~5ms + * so there is not a real need to optimize it. + */ +int find_calibration_point(unsigned char cal_results[CAL_ROWS][CAL_COLS], +unsigned int sum, unsigned int * cal_row, unsigned int * cal_col) { - unsigned int drvsel; - unsigned int smplsel; + /* Structure containing a rectangle candidate */ + typedef struct + { + unsigned char height; + unsigned char width; + unsigned short area; + } rect_cand_t; + + /* Array with the rectangle candidates */ + rect_cand_t rect_cands[CAL_ROWS * CAL_COLS]; + unsigned char cr_rect_cand = 0; + unsigned char height, width, k; + + /* No solution if all combinations fail */ + if(sum == 0) + return 1; + + /* Simple solution if all combinations pass */ + if(sum == (CAL_ROWS * CAL_COLS)) { + *cal_row = (CAL_ROWS - 1) / 2; + *cal_col = (CAL_COLS - 1) / 2; + return 0; + } + + /* + * Create list of all possible sub-rectangles, in descending area + * order + */ + for(height = CAL_ROWS; height >= 1; height--) { + for(width = CAL_COLS; width >= 1 ; width--){ + /* Add a new rectangle candidate */ + rect_cands[cr_rect_cand].height = height; + rect_cands[cr_rect_cand].width = width; + rect_cands[cr_rect_cand].area = height * width; + cr_rect_cand++; + + /* First candidate it always in the right position */ + if(cr_rect_cand == 1) + continue; + + /* + * Put the candidate in right location to maintain + * descending order + */ + for(k = cr_rect_cand - 1; k > 1; k--){ + if(rect_cands[k-1].area < rect_cands[k].area){ + rect_cand_t tmp = rect_cands[k-1]; + rect_cands[k-1] = rect_cands[k]; + rect_cands[k] = tmp; + } else + break; + } + } + } + + /* Try to fit the rectangle candidates, in descending area order */ + for(k = 0; k < CAL_ROWS * CAL_COLS; k++) { + unsigned char start_row, start_col; + unsigned rect_width = rect_cands[k].width; + unsigned rect_height = rect_cands[k].height; + + /* Find the row and column where the candidate fits */ + for (start_col = 0; start_col < (CAL_COLS - rect_width + 1); + start_col++) { + for (start_row = 0; start_row < (CAL_ROWS - + rect_height + 1); start_row++) { + unsigned ok = 1; + unsigned add_col, add_row; + + /* Determine if the rectangle fits here */ + for (add_col = 0; (add_col < rect_width) && ok; + add_col++) { + for (add_row = 0; add_row < rect_height; + add_row++) { + if (!cal_results + [start_row+add_row][start_col + + add_col]) { + ok = 0; + break; + } + } + } + + /* + * Return 'middle' of rectangle in case of + * success + */ + if (ok) { + if(rect_width > 1) + rect_width--; + + if(rect_height > 1) + rect_height--; + + *cal_row = start_row + + (rect_height / 2); + *cal_col = start_col + (rect_width / 2); + + return 0; + } + } + } + } + + /* We could not fit any rectangle - return failure */ + return 1; +} +void socfpga_dwmmc_set_clksel(unsigned int drvsel, unsigned int smplsel) +{ /* Disable SDMMC clock. */ clrbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); - /* Configures drv_sel and smpl_sel */ - drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; - smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; - debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), &system_manager_base->sdmmcgrp_ctrl); @@ -42,6 +157,64 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } +/* + * This functions calirates the drvsel and smplsel by trying all possible + * values and selecting the best combnation + */ +void socfpga_dwmmc_calibrate(struct dwmci_host *host) +{ + int err = 0; + unsigned char cal_results[CAL_ROWS][CAL_COLS]; + unsigned int sum = 0; + unsigned int row, col, drvsel, smplsel; + + struct mmc *mmc = (struct mmc *)host->mmc; + if (mmc == NULL) { + printf("struct mmc is NULL\n"); + hang(); + } + + printf("%s: Calibration started.\n", __func__); + + for (row = 0; row < CAL_ROWS; row++) { + for (col = 0; col < CAL_COLS; col++) { + drvsel = row + 1; + smplsel = col; + socfpga_dwmmc_set_clksel(drvsel, smplsel); + cal_results[row][col] = !(mmc_set_blocklen(mmc, + mmc->read_bl_len)); + sum += cal_results[row][col]; + } + } + + debug("%s: Calibration raw data:\n", __func__); + for(row = 0; row < CAL_ROWS; row++) { + debug("\t"); + for(col = 0; col < CAL_COLS; col++) + debug("%d ", cal_results[row][col]); + debug("\n"); + } + + err = find_calibration_point(cal_results, sum, &drvsel, &smplsel); + + if(err) { + printf("%s: Calibration failed.\n", __func__); + hang(); + } else + printf("%s: Calibration passed: drvsel = %d " + "smplsel = %d.\n", __func__, drvsel, smplsel); + + socfpga_dwmmc_set_clksel(drvsel, smplsel); + + /* re-write in case accidentally overwrite with junk */ + mmc_set_blocklen(mmc, mmc->read_bl_len); +} + +void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + socfpga_dwmmc_calibrate(host); +} + int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) { struct dwmci_host *host; -- 1.7.7.4

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[U-Boot] [PATCH v3 1/9] net: Revert "tftp: adjust settings to be suitable for 100Mbit ethernet"
by Bin Meng 08 Sep '15

08 Sep '15

Commit 620776d "tftp: adjust settings to be suitable for 100Mbit ethernet" causes the following error message when trying to load a file using 'tftp' command via a tftp server. TFTP error: 'Unsupported option(s) requested' (8) This is due to with commit 620776d changes, the tftp option 'timeout' value is now set to zero which is an invalid value as per RFC2349 [1]. Valid values range between "1" and "255" seconds, inclusive. With some tftp servers that strictly implement the RFC requirement, it reports such an error message. Revert commit 620776d for RFC compliance. [1] https://www.ietf.org/rfc/rfc2349.txt Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> --- Changes in v3: - Drop e1000 build warning patch which is already applied Changes in v2: - Rewrite the commit message to mention RFC2349 net/tftp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/net/tftp.c b/net/tftp.c index 18ce84c..89be32a 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -19,10 +19,10 @@ /* Well known TFTP port # */ #define WELL_KNOWN_PORT 69 /* Millisecs to timeout for lost pkt */ -#define TIMEOUT 100UL +#define TIMEOUT 5000UL #ifndef CONFIG_NET_RETRY_COUNT /* # of timeouts before giving up */ -# define TIMEOUT_COUNT 1000 +# define TIMEOUT_COUNT 10 #else # define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2) #endif @@ -711,10 +711,10 @@ void tftp_start(enum proto_t protocol) if (ep != NULL) timeout_ms = simple_strtol(ep, NULL, 10); - if (timeout_ms < 10) { - printf("TFTP timeout (%ld ms) too low, set min = 10 ms\n", + if (timeout_ms < 1000) { + printf("TFTP timeout (%ld ms) too low, set min = 1000 ms\n", timeout_ms); - timeout_ms = 10; + timeout_ms = 1000; } debug("TFTP blocksize = %i, timeout = %ld ms\n", -- 1.8.2.1

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