September 2015 - U-Boot

[U-Boot] [PATCH 1/4] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
by Chin Liang See 08 Sep '15

08 Sep '15

Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> --- drivers/spi/cadence_qspi.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..300934e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,7 +37,7 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); @@ -64,7 +64,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +111,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -131,7 +131,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) /* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; } -- 1.7.7.4

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[U-Boot] [PATCH v3] spi: tegra20: Add support for mode selection
by Mirza Krak 08 Sep '15

08 Sep '15

From: Mirza Krak <mirza.krak(a)hostmobility.com> Respect the mode passed in set_mode ops. Signed-off-by: Mirza Krak <mirza.krak(a)hostmobility.com> --- Changes in v3: * Move mode selection to .set_mode ops from .claim_bus ops Changes in v2: * Refactor clearing the CPOL and CPHA bits. Based on comments from Jagan Teki. drivers/spi/tegra20_slink.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index fbb665b86f3f..08c644c2173a 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_ENB (1 << 31) #define SLINK_CMD_GO (1 << 30) #define SLINK_CMD_M_S (1 << 28) +#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) +#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) #define SLINK_CMD_CK_SDA (1 << 21) #define SLINK_CMD_CS_POL (1 << 13) #define SLINK_CMD_CS_VAL (1 << 12) @@ -331,6 +336,22 @@ static int tegra30_spi_set_speed(struct udevice *bus, uint speed) static int tegra30_spi_set_mode(struct udevice *bus, uint mode) { struct tegra30_spi_priv *priv = dev_get_priv(bus); + struct spi_regs *regs = priv->regs; + u32 reg; + + reg = readl(&regs->command); + + /* Set CPOL and CPHA */ + reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA); + if (mode & SPI_CPHA) + reg |= SLINK_CMD_CK_SDA; + + if (mode & SPI_CPOL) + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; + else + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; + + writel(reg, &regs->command); priv->mode = mode; debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); -- 2.1.0

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[U-Boot] Any more patches for x86?
by Simon Glass 08 Sep '15

08 Sep '15

Hi Bin, Do you have any other patches that you think should be applied for the upcoming release? I'd like to get these in before sending out the last big pull request. Regards, Simon

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[U-Boot] [PATCH v3 2/2] arm: socfpga: config: Remove hard-coded drvsel and smpsel
by Chin Liang See 08 Sep '15

08 Sep '15

Remove hard-coded SDMMC timing parameter drvsel and smplsel. This setting now will come from SDMMC calibration Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- include/configs/socfpga_common.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 38ae763..2a2fdc5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -155,8 +155,6 @@ #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 /* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ -- 1.7.7.4

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[U-Boot] [PATCH v3 1/2] mmc: socfpga_dw_mmc: Enable calibration for drvsel and smpsel
by Chin Liang See 08 Sep '15

08 Sep '15

Enable SDMMC calibration to determine the best setting for drvsel and smpsel. It will be triggered whenever there is a change of card frequency and bus width. This is to ensure reliable transmission between the controller and the card. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Pantelis Antoniou <pantelis.antoniou(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- Changes for v3 - Remove the && ok as its redundant Changes for v2 - Using standard error return macro - Split to small function to avoid deep identation - Fix coding standard --- drivers/mmc/socfpga_dw_mmc.c | 198 ++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 191 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 8076761..2161f694 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -13,25 +13,150 @@ #include <asm/arch/dwmmc.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> +#include "mmc_private.h" static const struct socfpga_clock_manager *clock_manager_base = (void *)SOCFPGA_CLKMGR_ADDRESS; static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; -static void socfpga_dwmci_clksel(struct dwmci_host *host) +/* + * rows and columns of calibration rectange. The values are based on the value + * range of drvsel and smplsel register in system manager + */ +#define CAL_ROWS 7 +#define CAL_COLS 8 + +int find_row_col_fit_rectangle(unsigned rect_width, unsigned rect_height, +unsigned char cal_results[CAL_ROWS][CAL_COLS], unsigned int *cal_row, +unsigned int *cal_col) { - unsigned int drvsel; - unsigned int smplsel; + unsigned char start_row, start_col; + + /* Find the row and column where the candidate fits */ + for (start_col = 0; start_col < (CAL_COLS - rect_width + 1); + start_col++) { + for (start_row = 0; start_row < (CAL_ROWS - rect_height + 1); + start_row++) { + unsigned ok = 1; + unsigned add_col, add_row; + + /* Determine if the rectangle fits here */ + for (add_col = 0; (add_col < rect_width); add_col++) { + for (add_row = 0; add_row < rect_height; + add_row++) { + if (!cal_results[start_row + add_row] + [start_col + add_col]) { + ok = 0; + break; + } + } + } + + /* + * Return 'middle' of rectangle in case of + * success + */ + if (ok) { + if (rect_width > 1) + rect_width--; + + if (rect_height > 1) + rect_height--; + *cal_row = start_row + (rect_height / 2); + *cal_col = start_col + (rect_width / 2); + + return 0; + } + } + } + return -EINVAL; +} + +/* + * This function determines the largest rectangle filled with 1's and returns + * the middle. This functon can be optimized, for example using the algorithm + * from http://www.drdobbs.com/database/the-maximal-rectangle-problem/184410529 + * It currently takes less than 1ms, while creating the input data takes ~5ms + * so there is not a real need to optimize it. + */ +int find_calibration_point(unsigned char cal_results[CAL_ROWS][CAL_COLS], +unsigned int sum, unsigned int *cal_row, unsigned int *cal_col) +{ + /* Structure containing a rectangle candidate */ + struct rect_cand_t { + unsigned char height; + unsigned char width; + unsigned short area; + }; + + /* Array with the rectangle candidates */ + struct rect_cand_t rect_cands[CAL_ROWS * CAL_COLS], tmp; + unsigned char cr_rect_cand = 0; + unsigned char height, width, k; + + /* No solution if all combinations fail */ + if (sum == 0) + return -EINVAL; + + /* Simple solution if all combinations pass */ + if (sum == (CAL_ROWS * CAL_COLS)) { + *cal_row = (CAL_ROWS - 1) / 2; + *cal_col = (CAL_COLS - 1) / 2; + return 0; + } + + /* + * Create list of all possible sub-rectangles, in descending area + * order + */ + for (height = CAL_ROWS; height >= 1; height--) { + for (width = CAL_COLS; width >= 1; width--) { + /* Add a new rectangle candidate */ + rect_cands[cr_rect_cand].height = height; + rect_cands[cr_rect_cand].width = width; + rect_cands[cr_rect_cand].area = height * width; + cr_rect_cand++; + + /* First candidate it always in the right position */ + if (cr_rect_cand == 1) + continue; + + /* + * Put the candidate in right location to maintain + * descending order + */ + for (k = cr_rect_cand - 1; k > 1; k--) { + if (rect_cands[k-1].area < rect_cands[k].area) { + tmp = rect_cands[k-1]; + rect_cands[k-1] = rect_cands[k]; + rect_cands[k] = tmp; + } else { + break; + } + } + } + } + + /* Try to fit the rectangle candidates, in descending area order */ + for (k = 0; k < CAL_ROWS * CAL_COLS; k++) { + if (!find_row_col_fit_rectangle(rect_cands[k].width, + rect_cands[k].height, + cal_results, cal_row, cal_col)) + return 0; + } + + /* We could not fit any rectangle - return failure */ + return -EINVAL; +} + +static void socfpga_dwmmc_set_clksel(unsigned int drvsel, unsigned int smplsel) +{ /* Disable SDMMC clock. */ clrbits_le32(&clock_manager_base->per_pll.en, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); - /* Configures drv_sel and smpl_sel */ - drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; - smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; - debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), &system_manager_base->sdmmcgrp_ctrl); @@ -44,6 +169,65 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } +/* + * This functions calirates the drvsel and smplsel by trying all possible + * values and selecting the best combnation + */ +void socfpga_dwmmc_calibrate(struct dwmci_host *host) +{ + int err = 0; + unsigned char cal_results[CAL_ROWS][CAL_COLS]; + unsigned int sum = 0; + unsigned int row, col, drvsel, smplsel; + + struct mmc *mmc = (struct mmc *)host->mmc; + if (mmc == NULL) { + printf("struct mmc is NULL\n"); + hang(); + } + + debug("%s: Calibration started.\n", __func__); + + for (row = 0; row < CAL_ROWS; row++) { + for (col = 0; col < CAL_COLS; col++) { + drvsel = row + 1; + smplsel = col; + socfpga_dwmmc_set_clksel(drvsel, smplsel); + cal_results[row][col] = !(mmc_set_blocklen(mmc, + mmc->read_bl_len)); + sum += cal_results[row][col]; + } + } + + debug("%s: Calibration raw data:\n", __func__); + for (row = 0; row < CAL_ROWS; row++) { + debug("\t"); + for (col = 0; col < CAL_COLS; col++) + debug("%d ", cal_results[row][col]); + debug("\n"); + } + + err = find_calibration_point(cal_results, sum, &drvsel, &smplsel); + + if (err) { + printf("%s: Calibration failed.\n", __func__); + hang(); + } else + debug("%s: Calibration passed: drvsel = %d " + "smplsel = %d.\n", __func__, drvsel, smplsel); + + socfpga_dwmmc_set_clksel(drvsel, smplsel); + + /* re-write in case accidentally overwrite with junk */ + mmc_set_blocklen(mmc, mmc->read_bl_len); +} + +void socfpga_dwmci_clksel(struct dwmci_host *host) +{ + socfpga_dwmmc_calibrate(host); +} + + static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx) { /* FIXME: probe from DT eventually too/ */ -- 1.7.7.4

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 08 Sep '15

08 Sep '15

The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521: doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400) are available in the git repository at: git://git.denx.de/u-boot-usb.git for you to fetch changes up to 49b4c5c700077e387fef61a7225f92d190ee0c45: usb: ehci: remember init mode (2015-09-07 13:41:05 +0200) ---------------------------------------------------------------- Jiandong Zheng (1): implement Fastboot via USB OTG on bcm28155_ap boards Kishon Vijay Abraham I (1): h2200: Fix build error Lukasz Majewski (11): dfu:tests: Modify dfu_gadget_test.sh to accept USB device vendor:product ID dfu: Delete superfluous initialization of the dfu_buf_size static variable doc: dfu: tftp: README entry for TFTP extension of DFU net: tftp: Move tftp.h file from ./net to ./include/net tftp: update: Allow some parts of the code to be reused when CONFIG_SYS_NO_FLASH is set dfu: tftp: update: Provide tftp support for the DFU subsystem dfu: tftp: update: Add dfu_write_from_mem_addr() function update: tftp: dfu: Extend update_tftp() function to support DFU dfu: command: Extend "dfu" command to handle receiving data via TFTP dfu: tftp: Kconfig: Add Kconfig entry for dfu tftp feature dfu: tftp: Kconfig: Enable DFU_TFTP support on the am335x_boneblack_defconfig Siva Durga Prasad Paladugu (2): f_thor: Dont perform reset at the end of thor usb: gadget: f_thor: Allocate request up to THOR_PACKET_SIZE Stephen Warren (1): usb: ehci: remember init mode board/h2200/h2200.c | 12 +++++++++++ common/Makefile | 1 + common/cmd_dfu.c | 20 ++++++++++++++++++ common/cmd_fitupd.c | 2 +- common/main.c | 2 +- common/update.c | 58 +++++++++++++++++++++++++++++++++++++--------------- configs/am335x_boneblack_defconfig | 1 + doc/README.dfutftp | 114 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ doc/README.update | 7 +++++++ drivers/dfu/Kconfig | 10 +++++++++ drivers/dfu/Makefile | 1 + drivers/dfu/dfu.c | 39 ++++++++++++++++++++++++++++++++++- drivers/dfu/dfu_tftp.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/gadget/f_thor.c | 9 ++++++++- drivers/usb/gadget/f_thor.h | 3 +++ drivers/usb/host/ehci-hcd.c | 7 ++++++- drivers/usb/host/ehci.h | 1 + include/configs/bcm28155_ap.h | 19 ++++++++++++++++++ include/dfu.h | 41 +++++++++++++++++++++++++++++++++++++ include/net.h | 14 +++++++++++-- {net => include/net}/tftp.h | 0 net/bootp.c | 2 +- net/net.c | 2 +- net/rarp.c | 2 +- net/tftp.c | 2 +- test/dfu/README | 9 ++++++++- test/dfu/dfu_gadget_test.sh | 18 ++++++++++------- 27 files changed, 426 insertions(+), 35 deletions(-) create mode 100644 doc/README.dfutftp create mode 100644 drivers/dfu/dfu_tftp.c rename {net => include/net}/tftp.h (100%)

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 08 Sep '15

08 Sep '15

The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521: doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git for you to fetch changes up to a7ed0ac2620b00c6eb85227f3c66bc169ad11f44: net: altera_tse: Zap unused variable (2015-09-04 16:09:44 +0200) ---------------------------------------------------------------- Dinh Nguyen (1): arm: socfpga: Add support for the Terasic DE-0 Atlas board Marek Vasut (8): mmc: dw_mmc: Probe the MMC from OF arm: socfpga: Assure ISWGRP 0 and 1 are inited arm: socfpga: Always enable OF_CONTROL and SPL_OF_CONTROL arm: socfpga: Zap OF_CONTROL checks, it's always enabled arm: socfpga: Do not call board_init_r() from board_init_f() arm: socfpga: Add support for Terasic SoCkit board arm: socfpga: Add support for DENX MCV SoM and MCVEVK board net: altera_tse: Zap unused variable arch/arm/Kconfig | 2 + arch/arm/dts/Makefile | 3 + arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 61 +++++++++ arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 53 ++++++++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 92 +++++++++++++ arch/arm/mach-socfpga/Kconfig | 21 +++ arch/arm/mach-socfpga/include/mach/dwmmc.h | 2 +- arch/arm/mach-socfpga/misc.c | 9 +- arch/arm/mach-socfpga/reset_manager.c | 8 +- arch/arm/mach-socfpga/spl.c | 2 - board/denx/mcvevk/MAINTAINERS | 5 + board/denx/mcvevk/Makefile | 9 ++ board/denx/mcvevk/qts/iocsr_config.h | 660 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/denx/mcvevk/qts/pinmux_config.h | 219 ++++++++++++++++++++++++++++++ board/denx/mcvevk/qts/pll_config.h | 85 ++++++++++++ board/denx/mcvevk/qts/sdram_config.h | 341 +++++++++++++++++++++++++++++++++++++++++++++++ board/denx/mcvevk/socfpga.c | 45 +++++++ board/terasic/de0-nano-soc/MAINTAINERS | 5 + board/terasic/de0-nano-soc/Makefile | 9 ++ board/terasic/de0-nano-soc/qts/iocsr_config.h | 658 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/terasic/de0-nano-soc/qts/pinmux_config.h | 220 +++++++++++++++++++++++++++++++ board/terasic/de0-nano-soc/qts/pll_config.h | 85 ++++++++++++ board/terasic/de0-nano-soc/qts/sdram_config.h | 342 +++++++++++++++++++++++++++++++++++++++++++++++ board/terasic/de0-nano-soc/socfpga.c | 72 ++++++++++ board/terasic/sockit/MAINTAINERS | 5 + board/terasic/sockit/Makefile | 9 ++ board/terasic/sockit/qts/iocsr_config.h | 660 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/terasic/sockit/qts/pinmux_config.h | 219 ++++++++++++++++++++++++++++++ board/terasic/sockit/qts/pll_config.h | 85 ++++++++++++ board/terasic/sockit/qts/sdram_config.h | 341 +++++++++++++++++++++++++++++++++++++++++++++++ board/terasic/sockit/socfpga.c | 85 ++++++++++++ configs/socfpga_de0_nano_soc_defconfig | 20 +++ configs/socfpga_mcvevk_defconfig | 21 +++ configs/socfpga_sockit_defconfig | 26 ++++ drivers/mmc/socfpga_dw_mmc.c | 81 ++++++++++-- drivers/net/altera_tse.c | 2 - include/configs/socfpga_common.h | 7 +- include/configs/socfpga_de0_nano_soc.h | 87 ++++++++++++ include/configs/socfpga_mcvevk.h | 132 +++++++++++++++++++ include/configs/socfpga_sockit.h | 92 +++++++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 42 files changed, 4851 insertions(+), 31 deletions(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_mcvevk.dts create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit.dts create mode 100644 board/denx/mcvevk/MAINTAINERS create mode 100644 board/denx/mcvevk/Makefile create mode 100644 board/denx/mcvevk/qts/iocsr_config.h create mode 100644 board/denx/mcvevk/qts/pinmux_config.h create mode 100644 board/denx/mcvevk/qts/pll_config.h create mode 100644 board/denx/mcvevk/qts/sdram_config.h create mode 100644 board/denx/mcvevk/socfpga.c create mode 100644 board/terasic/de0-nano-soc/MAINTAINERS create mode 100644 board/terasic/de0-nano-soc/Makefile create mode 100644 board/terasic/de0-nano-soc/qts/iocsr_config.h create mode 100644 board/terasic/de0-nano-soc/qts/pinmux_config.h create mode 100644 board/terasic/de0-nano-soc/qts/pll_config.h create mode 100644 board/terasic/de0-nano-soc/qts/sdram_config.h create mode 100644 board/terasic/de0-nano-soc/socfpga.c create mode 100644 board/terasic/sockit/MAINTAINERS create mode 100644 board/terasic/sockit/Makefile create mode 100644 board/terasic/sockit/qts/iocsr_config.h create mode 100644 board/terasic/sockit/qts/pinmux_config.h create mode 100644 board/terasic/sockit/qts/pll_config.h create mode 100644 board/terasic/sockit/qts/sdram_config.h create mode 100644 board/terasic/sockit/socfpga.c create mode 100644 configs/socfpga_de0_nano_soc_defconfig create mode 100644 configs/socfpga_mcvevk_defconfig create mode 100644 configs/socfpga_sockit_defconfig create mode 100644 include/configs/socfpga_de0_nano_soc.h create mode 100644 include/configs/socfpga_mcvevk.h create mode 100644 include/configs/socfpga_sockit.h

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[U-Boot] please pull u-boot-arc master
by Alexey Brodkin 08 Sep '15

08 Sep '15

Hi Tom, The following changes since commit 6015f8f1b6fc30de7b4839bd691058583ec7f521: doc: document the fdtdir PXE command (2015-09-03 16:59:07 -0400) are available in the git repository at: git://git.denx.de/u-boot-arc.git for you to fetch changes up to a883f83e6d62fef1830b1634ccb72535c43696f7: arc: make AXS101 default platform (2015-09-07 13:38:24 +0300) ---------------------------------------------------------------- Alexey Brodkin (1): arc: make AXS101 default platform arch/arc/Kconfig | 2 +- configs/axs101_defconfig | 3 +-- configs/axs103_defconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) Regards, Alexey

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[U-Boot] [PATCH 1/3] spi: xilinx_spi: Fix to configure CPOL, CPHA mask
by Jagan Teki 07 Sep '15

07 Sep '15

priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki(a)openedev.com> --- drivers/spi/xilinx_spi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 6c21acd..8ccc578 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -247,7 +247,7 @@ static int xilinx_spi_set_speed(struct udevice *bus, uint speed) priv->freq = speed; - debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs, + debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs, priv->freq); return 0; @@ -260,13 +260,13 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode) uint32_t spicr; spicr = readl(&regs->spicr); - if (priv->mode & SPI_LSB_FIRST) + if (mode & SPI_LSB_FIRST) spicr |= SPICR_LSB_FIRST; - if (priv->mode & SPI_CPHA) + if (mode & SPI_CPHA) spicr |= SPICR_CPHA; - if (priv->mode & SPI_CPOL) + if (mode & SPI_CPOL) spicr |= SPICR_CPOL; - if (priv->mode & SPI_LOOP) + if (mode & SPI_LOOP) spicr |= SPICR_LOOP; writel(spicr, &regs->spicr); -- 1.9.1

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[U-Boot] [PATCH v2] spi: tegra20: Add support for mode selection
by Mirza Krak 07 Sep '15

07 Sep '15

From: Mirza Krak <mirza.krak(a)hostmobility.com> Respect the mode passed in claim_bus call. Signed-off-by: Mirza Krak <mirza.krak(a)hostmobility.com> --- Changes in v2: * Refactor clearing the CPOL and CPHA bits. Based on comments from Jagan Teki. drivers/spi/tegra20_slink.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index fbb665b86f3f..fa39dea2daf1 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -36,6 +36,11 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_ENB (1 << 31) #define SLINK_CMD_GO (1 << 30) #define SLINK_CMD_M_S (1 << 28) +#define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24) +#define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH (1 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) +#define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) +#define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) #define SLINK_CMD_CK_SDA (1 << 21) #define SLINK_CMD_CS_POL (1 << 13) #define SLINK_CMD_CS_VAL (1 << 12) @@ -146,6 +151,7 @@ static int tegra30_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct tegra30_spi_priv *priv = dev_get_priv(bus); struct spi_regs *regs = priv->regs; + unsigned int mode = priv->mode; u32 reg; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ @@ -161,6 +167,17 @@ static int tegra30_spi_claim_bus(struct udevice *dev) /* Set master mode and sw controlled CS */ reg = readl(&regs->command); reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; + + /* Set CPOL and CPHA */ + reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA); + if (mode & SPI_CPHA) + reg |= SLINK_CMD_CK_SDA; + + if (mode & SPI_CPOL) + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH; + else + reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW; + writel(reg, &regs->command); debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command)); -- 2.1.0

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