September 2015 - U-Boot

[U-Boot] [PATCH V2 1/2] nios2: Switch to generic timer
by Marek Vasut 07 Sep '15

07 Sep '15

Zap almost all of the ad-hoc timer code from interrupts.c and use the code in lib/time.c instead. Signed-off-by: Marek Vasut <marex(a)denx.de> --- arch/nios2/cpu/interrupts.c | 132 ++++++++++++---------------------------- arch/nios2/lib/Makefile | 1 - arch/nios2/lib/time.c | 22 ------- common/board_f.c | 3 +- include/configs/nios2-generic.h | 9 +-- 5 files changed, 43 insertions(+), 124 deletions(-) delete mode 100644 arch/nios2/lib/time.c V2: Rebase on top of u-boot/master diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 9d7e193..36d3ef7 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -8,7 +8,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ - #include <asm/nios2.h> #include <asm/types.h> #include <asm/io.h> @@ -20,14 +19,14 @@ #include <status_led.h> #endif -typedef volatile struct { - unsigned status; /* Timer status reg */ - unsigned control; /* Timer control reg */ - unsigned periodl; /* Timeout period low */ - unsigned periodh; /* Timeout period high */ - unsigned snapl; /* Snapshot low */ - unsigned snaph; /* Snapshot high */ -} nios_timer_t; +struct nios_timer { + u32 status; /* Timer status reg */ + u32 control; /* Timer control reg */ + u32 periodl; /* Timeout period low */ + u32 periodh; /* Timeout period high */ + u32 snapl; /* Snapshot low */ + u32 snaph; /* Snapshot high */ +}; /* status register */ #define NIOS_TIMER_TO (1 << 0) /* Timeout */ @@ -39,8 +38,8 @@ typedef volatile struct { #define NIOS_TIMER_START (1 << 2) /* Start timer */ #define NIOS_TIMER_STOP (1 << 3) /* Stop timer */ -#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) -#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) +#if defined(CONFIG_SYS_TIMER_BASE) && !defined(CONFIG_SYS_TIMER_IRQ) +#error CONFIG_SYS_TIMER_IRQ not defined (see documentation) #endif /****************************************************************************/ @@ -54,80 +53,15 @@ struct irq_action { static struct irq_action vecs[32]; /*************************************************************************/ -volatile ulong timestamp = 0; - -void reset_timer (void) -{ - nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; - - /* From Embedded Peripherals Handbook: - * - * "When the hardware is configured with Writeable period - * disabled, writing to one of the period_n registers causes - * the counter to reset to the fixed Timeout Period specified - * at system generation time." - * - * Here we force a reload to prevent early timeouts from - * get_timer() when the interrupt period is greater than - * than 1 msec. - * - * Simply write to periodl with its own value to force an - * internal counter reload, THEN reset the timestamp. - */ - writel (readl (&tmr->periodl), &tmr->periodl); - timestamp = 0; - - /* From Embedded Peripherals Handbook: - * - * "Writing to one of the period_n registers stops the internal - * counter, except when the hardware is configured with Start/Stop - * control bits off. If Start/Stop control bits is off, writing - * either register does not stop the counter." - * - * In order to accomodate either configuration, the control - * register is re-written. If the counter is stopped, it will - * be restarted. If it is running, the write is essentially - * a nop. - */ - writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, - &tmr->control); - -} - -ulong get_timer (ulong base) -{ - WATCHDOG_RESET (); - return (timestamp - base); -} - -/* - * This function is derived from Blackfin code (read timebase as long long). - * On Nios2 it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} +static volatile ulong timestamp; /* - * This function is derived from Blackfin code. - * On Nios2 it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; -} - -/* The board must handle this interrupt if a timer is not + * The board must handle this interrupt if a timer is not * provided. */ -#if defined(CONFIG_SYS_NIOS_TMRBASE) void tmr_isr (void *arg) { - nios_timer_t *tmr = (nios_timer_t *)arg; + struct nios_timer *tmr = (struct nios_timer *)arg; /* Interrupt is cleared by writing anything to the * status register. */ @@ -138,24 +72,38 @@ void tmr_isr (void *arg) #endif } -static void tmr_init (void) +unsigned long notrace timer_read_counter(void) +{ + struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE; + u32 val; + + /* Trigger update */ + writel(0x0, &tmr->snapl); + + /* Read timer value */ + val = readl(&tmr->snapl) & 0xffff; + val |= (readl(&tmr->snaph) & 0xffff) << 16; + + return ~val; +} + +int timer_init(void) { - nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; + struct nios_timer *tmr = (struct nios_timer *)CONFIG_SYS_TIMER_BASE; writel (0, &tmr->status); writel (0, &tmr->control); writel (NIOS_TIMER_STOP, &tmr->control); -#if defined(CONFIG_SYS_NIOS_TMRCNT) - writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl); - writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh); -#endif - writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START, - &tmr->control); - irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); -} + writel (0xffff, &tmr->periodl); + writel (0xffff, &tmr->periodh); -#endif /* CONFIG_SYS_NIOS_TMRBASE */ + writel (NIOS_TIMER_CONT | NIOS_TIMER_START, &tmr->control); + /* FIXME */ + irq_install_handler(CONFIG_SYS_TIMER_IRQ, tmr_isr, (void *)tmr); + + return 0; +} /*************************************************************************/ int disable_interrupts (void) @@ -245,10 +193,6 @@ int interrupt_init (void) vecs[i].count = 0; } -#if defined(CONFIG_SYS_NIOS_TMRBASE) - tmr_init (); -#endif - enable_interrupts (); return (0); } diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile index 079378a..e35d2e9 100644 --- a/arch/nios2/lib/Makefile +++ b/arch/nios2/lib/Makefile @@ -8,4 +8,3 @@ obj-y += cache.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += libgcc.o -obj-y += time.o diff --git a/arch/nios2/lib/time.c b/arch/nios2/lib/time.c deleted file mode 100644 index d396045..0000000 --- a/arch/nios2/lib/time.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2003, Psyent Corporation <www.psyent.com> - * Scott McNutt <smcnutt(a)psyent.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> - - -extern void dly_clks( unsigned long ticks ); - -void __udelay(unsigned long usec) -{ - /* The Nios core doesn't have a timebase, so we do our - * best for now and call a low-level loop that counts - * cpu clocks. - */ - unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec; - dly_clks (cnt); -} diff --git a/common/board_f.c b/common/board_f.c index 613332e..d0a9ff7 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -795,7 +795,8 @@ static init_fnc_t init_sequence_f[] = { init_timebase, #endif #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ - defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) + defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ + defined(CONFIG_NIOS2) timer_init, /* initialize timer */ #endif #ifdef CONFIG_SYS_ALLOC_DPRAM diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 945cbd4..1635794 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -38,12 +38,9 @@ /* * TIMER */ -#define CONFIG_SYS_LOW_RES_TIMER -#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE -#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ -#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/ -#define CONFIG_SYS_NIOS_TMRCNT \ - (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1) +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TIMER_FREQ +#define CONFIG_SYS_NIOS_TMRMS 10 /* FIXME: Desired period (msec)*/ /* * STATUS LED -- 2.1.4

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[U-Boot] [PATCH] nios2: enable Driver Model
by Thomas Chou 07 Sep '15

07 Sep '15

Enable the Driver Model config. The driver subsystems are not enabled until we enable each of them. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- configs/nios2-generic_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig index 09cc51e..2acf45d 100644 --- a/configs/nios2-generic_defconfig +++ b/configs/nios2-generic_defconfig @@ -1,4 +1,5 @@ CONFIG_NIOS2=y +# CONFIG_SYS_MALLOC_F is not set CONFIG_TARGET_NIOS2_GENERIC=y CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" CONFIG_HUSH_PARSER=y @@ -13,3 +14,4 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y -- 2.1.4

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[U-Boot] [PATCH] arc: make AXS101 default platform
by Alexey Brodkin 07 Sep '15

07 Sep '15

This fixes building in automated flow that doesn't use defconfigs. See discussion on that topic here: http://patchwork.ozlabs.org/patch/502558/ See similar patches for other architectures/platforms here: [1] http://git.denx.de/?p=u-boot.git;a=commit;h=ff560a13056a565a4e9ce1761bd0427… [2] http://git.denx.de/?p=u-boot.git;a=commit;h=589907e2c187ec69b351c38ccda3673… And while at it add missing shell prompt to axs103. Cc: Tom Rini <trini(a)konsulko.com> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- arch/arc/Kconfig | 2 +- configs/axs101_defconfig | 3 +-- configs/axs103_defconfig | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 925e312..264c83d 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -129,7 +129,7 @@ config ARC_CACHE_LINE_SHIFT choice prompt "Target select" - optional + default TARGET_AXS101 config TARGET_TB100 bool "Support tb100" diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 9a6cef3..fdb3149 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,13 +1,12 @@ CONFIG_ARC=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARC_CACHE_LINE_SHIFT=5 -CONFIG_TARGET_AXS101=y CONFIG_SYS_CLK_FREQ=750000000 CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y CONFIG_USE_PRIVATE_LIBGCC=y -CONFIG_SYS_PROMPT="AXS# " diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 8315b61..b3dbb8d 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -1,8 +1,8 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y -CONFIG_TARGET_AXS101=y CONFIG_SYS_CLK_FREQ=50000000 CONFIG_SYS_TEXT_BASE=0x81000000 +CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -- 2.4.3

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[U-Boot] u-boot hangs in spl fat load when Linux image size exceeds one cluster
by Lixun.Lin＠rohde-schwarz.com 07 Sep '15

07 Sep '15

Hi there, I am using u-boot 2015.04. I am trying to use spl mode to boot Linux without loading u-boot. I am working on the Zynq-7000 zc706 board. I enabled the debug mode and here is the output: U-Boot SPL 2015.04 (Sep 07 2015 - 08:22:08) >>spl:board_init_r() using memory 0xffff10c0-0xffff20c0 for malloc() fpga_init mmc boot boot device - 1 mmc_init: 0, time 67 boot mode - FS ...(omitted, successfully initialize and load dts from SD card) RootName: uimage, start: 0x90, size: 0x351478 Filesize: 3478648 bytes 64 bytes gc - clustnum: 144, startsect: 17520 Size: 3478648, got: 64 spl: payload image: Linu load addr: 0x7fc0 size: 3478648 reading uImage VFAT Support enabled FAT32, fat_sect: 1304, fatlength: 7540 Rootdir begins at cluster: 2, sector: 16384, offset: 800000 Data begins at: 16368 Sector size: 512, cluster size: 8 FAT read(sect=16384, cnt:8), clust_size=8, DIRENTSPERBLOCK=16 RootMismatch: |boot.bin|| RootMismatch: |system.dtb|| RootMismatch: |u-boot.img|| Rootvfatname: |uimage| RootName: uimage, start: 0x90, size: 0x351478 Filesize: 3478648 bytes 3478648 bytes FAT32: entry: 0x0090 = 144, offset: 0x0090 = 144 FAT32: ret: 00000091, offset: 0090 FAT32: entry: 0x0091 = 145, offset: 0x0091 = 145 FAT32: ret: 00000092, offset: 0091 FAT32: entry: 0x0092 = 146, offset: 0x0092 = 146 FAT32: ret: 00000093, offset: 0092 FAT32: entry: 0x0093 = 147, offset: 0x0093 = 147 FAT32: ret: 00000094, offset: 0093 ... FAT32: entry: 0x02fd = 765, offset: 0x02fd = 765 FAT32: ret: 000002fe, offset: 02fd FAT32: entry: 0x02fe = 766, offset: 0x02fe = 766 FAT32: ret: 000002ff, offset: 02fe FAT32: entry: 0x02ff = 767, offset: 0x02ff = 767 FAT32: ret: 00000300, offset: 02ff FAT32: entry: 0x0300 = 768, offset: 0x0000 = 0 <== notice here FAT32: ret: 00000301, offset: 0000 FAT32: entry: 0x0301 = 769, offset: 0x0001 = 1 FAT32: ret: 00000302, offset: 0001 FAT32: entry: 0x0302 = 770, offset: 0x0002 = 2 FAT32: ret: 00000303, offset: 0002 FAT32: entry: 0x0303 = 771, offset: 0x0003 = 3 FAT32: ret: 00000304, offset: 0003 FAT32: entry: 0x0304 = 772, offset: 0x0004 = 4 FAT32: ret: 00000305, offset: 0004 ... FAT32: entry: 0x03da = 986, offset: 0x00da = 218 FAT32: ret: 000003db, offset: 00da FAT32: entry: 0x03db = 987, offset: 0x00db = 219 FAT32: ret: 000003dc, offset: 00db FAT32: entry: 0x03dc = 988, offset: 0x00dc = 220 FAT32: ret: 000003dd, offset: 00dc FAT32: entry: 0x03dd = 989, offset: 0x00dd = 221 FAT32: ret: 000003de, offset: 00dd FAT32: entry: 0x03de = 990, offset: 0x00de = 222 FAT32: ret: 000003df, offset: 00de FAT32: entry: 0x03df = 991, offset: 0x00df = 223 FAT32: ret: 000003e0, offset: 00df FAT32: entry: 0x03e0 = 992, offset: 0x00e0 = 224 FAT32: ret: 000003e1, offset: 00e0 gc - clustnum: 144, startsect: 17520 After the last line, u-boot does not proceed any more. I have tried loading the u-boot.img, which is much smaller than the uImage and that is successful. Could this a problem with fat load in the spl mode? In fs/fat/fat.c get_contents() function, it seems it only read at data from at most cluster. I am sorry if I missed something. I am new to u-boot. Thank you very much in advance. Best Regards, Lixun

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[U-Boot] [PATCH v4 0/8] This patch series adds support for Cavium ThunderX 88xx SoC family
by Sergey Temerkhanov 07 Sep '15

07 Sep '15

(http://cavium.com/ThunderX_ARM_Processors.html) Changes in v4: - Use ALIGN macro for address alignment - Document FW calls - Fixed build warnings - Moved to DM_SERIAL - Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig - Add proper DM_SERIAL definitions Changes in v3: - Reduced code duplication - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS - Moved 'reset_sctrl' call to the 'reset' label - Rebased to the actual upstream tree - Documented newly added config options - Fixed clobber lists (thanks to Corey) - Added __used keyword - Fixed formatting - Added MAINTAINERS - Moved command definitions to defconfig Changes in v2: - Changed code licensing - Completed the patchset Sergey Temerkhanov (8): armv8: Add read_mpidr() function armv8: New MMU setup code allowing to use 48+ bits PA/VA armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructure armv8: Add psci.h from the Linux kernel arm: serial: Add ability to use pre-initialized UARTs armv8: cavium: Add ThunderX 88xx board definition armv8: cavium: Add an implementation of ATF calling functions armv8: cavium: Get DRAM size from ATF arch/arm/Kconfig | 4 + arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cache_v8.c | 80 +++++++- arch/arm/cpu/armv8/fwcall.c | 75 ++++++++ arch/arm/cpu/armv8/start.S | 36 ++++ arch/arm/include/asm/armv8/mmu.h | 79 +++++++- arch/arm/include/asm/global_data.h | 1 + arch/arm/include/asm/system.h | 39 ++++ arch/arm/lib/board.c | 6 +- board/cavium/thunderx/Kconfig | 19 ++ board/cavium/thunderx/MAINTAINERS | 6 + board/cavium/thunderx/Makefile | 8 + board/cavium/thunderx/atf.c | 312 ++++++++++++++++++++++++++++++++ board/cavium/thunderx/dram.c | 35 ++++ board/cavium/thunderx/thunderx.c | 74 ++++++++ configs/thunderx_88xx_defconfig | 28 +++ doc/README.arm64 | 35 +++- drivers/serial/serial_pl01x.c | 12 +- include/cavium/atf.h | 22 +++ include/cavium/atf_part.h | 26 +++ include/cavium/thunderx_svc.h | 67 +++++++ include/configs/thunderx_88xx.h | 151 ++++++++++++++++ include/dm/platform_data/serial_pl01x.h | 6 + include/linux/psci.h | 90 +++++++++ 24 files changed, 1191 insertions(+), 21 deletions(-) create mode 100644 arch/arm/cpu/armv8/fwcall.c create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/MAINTAINERS create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/atf.c create mode 100644 board/cavium/thunderx/dram.c create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/cavium/atf.h create mode 100644 include/cavium/atf_part.h create mode 100644 include/cavium/thunderx_svc.h create mode 100644 include/configs/thunderx_88xx.h create mode 100644 include/linux/psci.h -- 2.2.0

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[U-Boot] [PATCH v1] fix: possible overflow when copying the string
by Imran Zaman 07 Sep '15

07 Sep '15

Bigger source buffer than dest buffer could overflow when copying strings. Source and destination buffer sizes are same now. Signed-off-by: Imran Zaman <imran.zaman(a)intel.com> --- common/cli_simple.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cli_simple.c b/common/cli_simple.c index 00a8d2f..d8b40c9 100644 --- a/common/cli_simple.c +++ b/common/cli_simple.c @@ -258,7 +258,7 @@ int cli_simple_run_command(const char *cmd, int flag) void cli_simple_loop(void) { - static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, }; + static char lastcommand[CONFIG_SYS_CBSIZE + 1] = { 0, }; int len; int flag; -- 1.9.1 --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.

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[U-Boot] [PATCH v4 1/2] usb: zynqmp: Add XHCI driver support
by Siva Durga Prasad Paladugu 07 Sep '15

07 Sep '15

Added USB XHCI driver support for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- Changes for v4: - Added sanity check for index as per review comment Changes for v3: - Decreased the phy reset delay to 10 micro secs - Defined base addresses in board config file as per review comment. Changes for v2: - Moved all from xhci-zynqmp.h to .c file as per review comment - Removed ad-hoc function zynqmp_xhci_core_exit() as per review comment --- drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-zynqmp.c | 148 ++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp_ep.h | 2 + 3 files changed, 151 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/xhci-zynqmp.c diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c..645b990 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c new file mode 100644 index 0000000..7c4a413 --- /dev/null +++ b/drivers/usb/host/xhci-zynqmp.c @@ -0,0 +1,148 @@ +/* + * Copyright 2015 Xilinx, Inc. + * + * Zynq USB HOST xHCI Controller + * + * Author: Siva Durga Prasad Paladugu<sivadur(a)xilinx.com> + * + * This file was reused from Freescale USB xHCI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <asm-generic/errno.h> +#include <asm/arch-zynqmp/hardware.h> +#include <linux/compat.h> +#include <linux/usb/dwc3.h> +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* Default to the ZYNQMP XHCI defines */ +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN BIT(1) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) + +struct zynqmp_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static struct zynqmp_xhci zynqmp_xhci; + +unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST; + +__weak int __board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} + +void usb_phy_reset(struct dwc3 *dwc3_reg) +{ + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + + udelay(10); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); +} + +static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) +{ + int ret = 0; + + ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return ret; +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct zynqmp_xhci *ctx = &zynqmp_xhci; + int ret = 0; + + if (index < 0 || index >= ARRAY_SIZE(ctr_addr)) + return -EINVAL; + + ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + ret = zynqmp_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + *hcor = (struct xhci_hcor *)((uint32_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + /* + * Currently zynqmp socs do not support PHY shutdown from + * sw. But this support may be added in future socs. + */ + + return 0; +} diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index e476eb1..abb3c40 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -24,6 +24,8 @@ #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM #define CONFIG_AHCI +#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ + ZYNQMP_USB1_XHCI_BASEADDR} #include <configs/xilinx_zynqmp.h> -- 1.7.1

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[U-Boot] [PATCH] nios2: enable CONFIG_NET_RANDOM_ETHADDR
by Thomas Chou 07 Sep '15

07 Sep '15

Enable CONFIG_NET_RANDOM_ETHADDR to generate a random MAC address when ETHADDR is not set. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- configs/nios2-generic_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig index 5f93394..f8d2821 100644 --- a/configs/nios2-generic_defconfig +++ b/configs/nios2-generic_defconfig @@ -10,3 +10,4 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y -- 2.1.4

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[U-Boot] [PATCH] nios2: move command line configuration to Kconfig
by Thomas Chou 07 Sep '15

07 Sep '15

This patch moves command line configuration from board header file to board defconfig in the way of Kconfig. The change passed savedefconfig. This fixes warnings such as : "CONFIG_SYS_HUSH_PARSER" redefined, when "Use hush shell" is selected with menuconfig, etc. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- configs/nios2-generic_defconfig | 3 +++ include/configs/nios2-generic.h | 9 +-------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/configs/nios2-generic_defconfig b/configs/nios2-generic_defconfig index 573a084..5f93394 100644 --- a/configs/nios2-generic_defconfig +++ b/configs/nios2-generic_defconfig @@ -1,9 +1,12 @@ CONFIG_NIOS2=y CONFIG_TARGET_NIOS2_GENERIC=y +CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_FPGA is not set # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 945cbd4..5bb7768 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -73,13 +73,8 @@ #define CONFIG_BOOTP_HOSTNAME /* - * Command line configuration. + * FDT options */ -#ifdef CONFIG_CMD_NET -# define CONFIG_CMD_DHCP -# define CONFIG_CMD_PING -#endif - #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP #define CONFIG_LMB @@ -130,6 +125,4 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000) #define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_HUSH_PARSER - #endif /* __CONFIG_H */ -- 2.1.4

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[U-Boot] "tftp: adjust settings to be suitable for 100Mbit ethernet" breaks imx6
by Peng Fan 07 Sep '15

07 Sep '15

Hi, With the following patch, I met tftp errors on mx6qsabresd and mx6ul boards: " => setenv serverip 10.193.102.217; setenv ipaddr 10.193.102.31;tftp ${loadaddr} zImage Using FEC device TFTP from server 10.193.102.217; our IP address is 10.193.102.31 Filename 'zImage'. Load address: 0x12000000 Loading: * TFTP error: 'Failure to negotiate RFC1782 options' (8) Starting again " Without the following patch, tftp work fine on mx6qsabresd and mx6ul board. " commit 620776d734e4b126c407f636bda825a594a17723 Author: Pavel Machek <pavel(a)denx.de> Date: Tue Aug 18 14:34:26 2015 +0200 tftp: adjust settings to be suitable for 100Mbit ethernet Adjust timouts and retry counts to be suitable for loaded ethernet network. With 5 seconds timeout, 10 retries maximum, tftp is impossible even on local network with single full-speed TCP connection. 100msec timeout should be suitable for most networks tftp is used on, that is local ethernets. Timeout count really needs to be way higher, as lost packets are normal when TCP is running over the same network. Enforce 10msec minimum. Signed-off-by: Pavel Machek <pavel(a)denx.de> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> " Regards, Peng. --

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