September 2015 - U-Boot

[U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support
by Peng Fan 01 Sep '15

01 Sep '15

To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Heiko Schocher <hs(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos(a)imgtec.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Changes v2: Addressed Fabio's comments. Using "fec_id == 0", but not "0 == fec_id". arch/arm/cpu/armv7/mx6/clock.c | 23 ++++++++++++++++++----- arch/arm/include/asm/arch-mx6/clock.h | 2 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 6 ++++++ board/aristainetos/aristainetos-v1.c | 2 +- board/barco/platinum/platinum_picon.c | 2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- 9 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 9cf4eec..ba6cc75 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num) #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(enum enet_freq freq) +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq) if (freq < ENET_25MHZ || freq > ENET_125MHZ) return -EINVAL; - reg = readl(&anatop->pll_enet); - reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; - reg |= freq; + if (fec_id == 0) { + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); + } else if (fec_id == 1) { + /* Only i.MX6SX/UL support ENET2 */ + if (!(is_cpu_type(MXC_CPU_MX6SX) || + is_cpu_type(MXC_CPU_MX6UL))) + return -EINVAL; + reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; + reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); + } else { + return -EINVAL; + } if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { @@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq) } /* Enable FEC clock */ - reg |= BM_ANADIG_PLL_ENET_ENABLE; + if (fec_id == 0) + reg |= BM_ANADIG_PLL_ENET_ENABLE; + else + reg |= BM_ANADIG_PLL_ENET2_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 7b3bbb8..2b220d6 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -64,7 +64,7 @@ int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); -int enable_fec_anatop_clock(enum enet_freq freq); +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index fe75da4..10306cd 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1052,6 +1052,12 @@ struct mxc_ccm_reg { #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +/* ENET2 for i.MX6SX/UL */ +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) + #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c index d6a7614..b8fed2e 100644 --- a/board/aristainetos/aristainetos-v1.c +++ b/board/aristainetos/aristainetos-v1.c @@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(ENET_50MHZ); + ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c index b2eab76..0384a26 100644 --- a/board/barco/platinum/platinum_picon.c +++ b/board/barco/platinum/platinum_picon.c @@ -148,7 +148,7 @@ int platinum_setup_enet(void) /* set GPIO_16 as ENET_REF_CLK_OUT */ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } int platinum_setup_i2c(void) diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 98602f8..7c0e90a 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -361,7 +361,7 @@ static void setup_fec(void) * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(ENET_125MHZ); + enable_fec_anatop_clock(0, ENET_125MHZ); } setup_iomux_enet(); diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 7c18c90..98e3ef0 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -279,7 +279,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - return enable_fec_anatop_clock(ENET_50MHZ); + return enable_fec_anatop_clock(0, ENET_50MHZ); } #endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index d58a79a..ffc0046 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -170,7 +170,7 @@ static int setup_fec(void) reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); - return enable_fec_anatop_clock(ENET_125MHZ); + return enable_fec_anatop_clock(0, ENET_125MHZ); } int board_eth_init(bd_t *bis) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 9b1ecf0..8247e43 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis) struct mii_dev *bus; struct phy_device *phydev; - int ret = enable_fec_anatop_clock(ENET_25MHZ); + int ret = enable_fec_anatop_clock(0, ENET_25MHZ); if (ret) return ret; -- 1.8.4

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[U-Boot] TFTP Timeout Interval problem
by Gong Q.Y. 01 Sep '15

01 Sep '15

Hi, I got a problem with tftp and found this patch. ------------- commit 620776d734e4b126c407f636bda825a594a17723 Author: Pavel Machek <pavel(a)denx.de> Date: Tue Aug 18 14:34:26 2015 +0200 tftp: adjust settings to be suitable for 100Mbit ethernet -------------- The default timeout is changed to 100 (ms) and this causes "TFTP error: 'Unsupported option(s) requested' (8)". Because the option is equal to timeout/1000, now it's zero(100/1000 -> 0) which is not supported. Actually I find in an original doc RFC-2349 which specifies this value should range between "1" and "255" seconds. So I think there may be a conflict? Look forward to your help. This is my test log: => tftp a0000000 gqy/bootscript Using FM1@DTSEC3 device TFTP from server 10.192.208.233; our IP address is 10.193.20.130 Filename 'gqy/bootscript'. Load address: 0xa0000000 Loading: * TFTP error: 'Unsupported option(s) requested' (8) Starting again => setenv tftptimeout 1000 => tftp a0000000 gqy/bootscript Using FM1@DTSEC3 device TFTP from server 10.192.208.233; our IP address is 10.193.20.130 Filename 'gqy/bootscript'. Load address: 0xa0000000 Loading: # 44.9 KiB/s done Bytes transferred = 92 (5c hex) => Regards, Qianyu

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[U-Boot] [RFC PATCH v2] arm: cache_v7: fix dcache invalidation
by Markus Niebel 01 Sep '15

01 Sep '15

From: Markus Niebel <Markus.Niebel(a)tq-group.com> according to http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14802.ht… and the clarification given by Marc Rutland of ARM data cache invalidation should go from outer to inner cache. This patch corrects the order in flush_dcache_range flush_dcache_all Signed-off-by: Markus Niebel <Markus.Niebel(a)tq-group.com> --- Changes for v2: - delete non related stuff (thanks to Hannes Schmelzer) arch/arm/cpu/armv7/cache_v7.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index a5aa4fa..81eb286 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -235,9 +235,9 @@ static void v7_inval_tlb(void) void invalidate_dcache_all(void) { - v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); - v7_outer_cache_inval_all(); + + v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL); } /* @@ -257,9 +257,9 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { - v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); - v7_outer_cache_inval_range(start, stop); + + v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE); } /* -- 2.3.0

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[U-Boot] ls2085ardb not booting
by Scott Wood 01 Sep '15

01 Sep '15

I'm unable to boot ls2085ardb on the current tree. I get no console output. v2015.07 gives some output, but hangs at: > U-Boot 2015.07 (Aug 27 2015 - 16:24:43 -0500) LS2085A-RDB > > Clock Configuration: > CPU0(A57):1600 MHz CPU1(A57):1600 MHz CPU2(A57):1600 MHz > CPU3(A57):1600 MHz CPU4(A57):1600 MHz CPU5(A57):1600 MHz > CPU6(A57):1600 MHz CPU7(A57):1600 MHz > Bus: 600 MHz DDR: 1333.333 MHz DP-DDR: 1333.333 MHz > Reset Configuration Word (RCW): > 00: 40282830 40400040 00000000 00000000 > 10: 00000000 00200000 00200000 00000000 > 20: 00c12980 00002580 00000000 00000000 > 30: 00000e0b 00000000 00000000 00000000 > 40: 00000000 00000000 00000000 00000000 > 50: 00000000 00000000 00000000 00000000 > 60: 00000000 00000000 00027000 00000000 > 70: 412a0000 00000000 00000000 00000000 > Board: LS2085A-RDB, Board Arch: V1, Board version: C, boot from vBank: 4 > FPGA: v1.18 > SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz > SERDES2 Reference : Clock1 = 100MHz Clock2 = 100MHz > I2C: ready > DRAM: Initializing DDR....using SPD > Detected UDIMM 18ASF1G72AZ-2G1A1 > Detected UDIMM 18ASF1G72AZ-2G1A1 > There is no rank on CS0 for controller 1. > Controler 1 timeout, debug_2 = 2100 > Controler 1 timeout, debug_2 = 2500 > Waiting for D_INIT timeout. Memory may not work. > DP-DDR: Detected UDIMM 18ASF1G72AZ-2G1A1 > 19.5 GiB > DDR 15.5 GiB (DDR4, 64-bit, CL=9, ECC on) > DDR Chip-Select Interleaving Mode: CS0+CS1 > DP-DDR 4 GiB (DDR4, 32-bit, CL=9, ECC on) > DDR Chip-Select Interleaving Mode: CS0+CS1 The internal bringup branch does boot on the same board, with the same RCW. -Scott

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[U-Boot] [PATCH] Revert "patman: use -D option for git format-patch"
by Masahiro Yamada 01 Sep '15

01 Sep '15

This reverts commit 19b4a3369876f9215e2b861f211e8df1a75e26ca. Since that commit, patman generates useless patches for file removal; "git format -D" prints only the header but not the diff when deleting files, and "git am" always refuses such patches. The following is the quotation from "man git-format-patch": -D, --irreversible-delete Omit the preimage for deletes, i.e. print only the header but not the diff between the preimage and /dev/null. The resulting patch is not meant to be applied with patch nor git apply; this is solely for people who want to just concentrate on reviewing the text after the change. In addition, the output obviously lack enough information to apply such a patch in reverse, even manually, hence the name of the option. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- tools/patman/gitutil.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 67b086b..9e739d8 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -264,7 +264,7 @@ def CreatePatches(start, count, series): """ if series.get('version'): version = '%s ' % series['version'] - cmd = ['git', 'format-patch', '-D', '-M', '--signoff'] + cmd = ['git', 'format-patch', '-M', '--signoff'] if series.get('cover'): cmd.append('--cover-letter') prefix = series.GetPatchPrefix() -- 1.9.1

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[U-Boot] [PATCH 1/2] x86: coreboot: Convert to use more dm drivers
by Bin Meng 01 Sep '15

01 Sep '15

Move to driver model for RTC, USB and ETH on coreboot. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/coreboot/coreboot.c | 6 ------ configs/coreboot-x86_defconfig | 5 ++++- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 0e9f15f..845f86a 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -8,7 +8,6 @@ #include <common.h> #include <fdtdec.h> -#include <netdev.h> #include <asm/io.h> #include <asm/msr.h> #include <asm/mtrr.h> @@ -48,11 +47,6 @@ int last_stage_init(void) return 0; } -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - void board_final_cleanup(void) { /* diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index df3a624..b1e94f6 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -12,7 +12,10 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y -CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y CONFIG_E1000=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_RTC=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y -- 1.8.2.1

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[U-Boot] [PATCH v3] x86: panther: Add PCI and video configuration
by Simon Glass 01 Sep '15

01 Sep '15

Add a PCI node to the device tree. This allows SPI flash and SATA to work correctly. Also configure the video to come up correctly even though there is no keyboard. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v3: - Fix 'correectly' typo Changes in v2: - Fix PCI I/O range value arch/x86/dts/chromebox_panther.dts | 10 ++++++++++ include/configs/chromebox_panther.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts index 84eae3a..31daf26 100644 --- a/arch/x86/dts/chromebox_panther.dts +++ b/arch/x86/dts/chromebox_panther.dts @@ -42,6 +42,16 @@ stdout-path = "/serial"; }; + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xf000>; + }; + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h index 00fe26d..dc732b8 100644 --- a/include/configs/chromebox_panther.h +++ b/include/configs/chromebox_panther.h @@ -14,4 +14,6 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define CONFIG_VGA_AS_SINGLE_DEVICE + #endif /* __CONFIG_H */ -- 2.5.0.457.gab17608

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[U-Boot] [PATCH 1/3] x86: ifdtool: Support checking region overlap before U-Boot
by Bin Meng 01 Sep '15

01 Sep '15

We have the capability to check regions written after U-Boot that do not overlap. Since regions can also be written before U-Boot, add such check for these too. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- tools/ifdtool.c | 66 ++++++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 46 insertions(+), 20 deletions(-) diff --git a/tools/ifdtool.c b/tools/ifdtool.c index 1f95203..48059c0 100644 --- a/tools/ifdtool.c +++ b/tools/ifdtool.c @@ -707,10 +707,12 @@ int inject_region(char *image, int size, int region_type, char *region_fname) * 8MB ROM the start address is 0xfff80000. * @write_fname: Filename to add to the image * @offset_uboot_top: Offset of the top of U-Boot + * @offset_uboot_start: Offset of the start of U-Boot * @return number of bytes written if OK, -ve on error */ static int write_data(char *image, int size, unsigned int addr, - const char *write_fname, int offset_uboot_top) + const char *write_fname, int offset_uboot_top, + int offset_uboot_start) { int write_fd, write_size; int offset; @@ -720,13 +722,25 @@ static int write_data(char *image, int size, unsigned int addr, return write_fd; offset = (uint32_t)(addr + size); - if (offset_uboot_top && offset_uboot_top >= offset) { - fprintf(stderr, "U-Boot image overlaps with region '%s'\n", - write_fname); - fprintf(stderr, - "U-Boot finishes at offset %x, file starts at %x\n", - offset_uboot_top, offset); - return -EXDEV; + if (offset_uboot_top) { + if (offset_uboot_start < offset && + offset_uboot_top >= offset) { + fprintf(stderr, "U-Boot image overlaps with region '%s'\n", + write_fname); + fprintf(stderr, + "U-Boot finishes at offset %x, file starts at %x\n", + offset_uboot_top, offset); + return -EXDEV; + } + if (offset_uboot_start > offset && + offset_uboot_start <= offset + write_size) { + fprintf(stderr, "U-Boot image overlaps with region '%s'\n", + write_fname); + fprintf(stderr, + "U-Boot starts at offset %x, file finishes at %x\n", + offset_uboot_start, offset + write_size); + return -EXDEV; + } } debug("Writing %s to offset %#x\n", write_fname, offset); @@ -927,27 +941,36 @@ static int write_ucode(char *image, int size, struct input_file *fdt, */ static int write_uboot(char *image, int size, struct input_file *uboot, struct input_file *fdt, unsigned int ucode_ptr, - int collate_ucode) + int collate_ucode, int *offset_uboot_top, + int *offset_uboot_start) { - const void *blob; int uboot_size, fdt_size; + int uboot_top; - uboot_size = write_data(image, size, uboot->addr, uboot->fname, 0); + uboot_size = write_data(image, size, uboot->addr, uboot->fname, 0, 0); if (uboot_size < 0) return uboot_size; fdt->addr = uboot->addr + uboot_size; debug("U-Boot size %#x, FDT at %#x\n", uboot_size, fdt->addr); - fdt_size = write_data(image, size, fdt->addr, fdt->fname, 0); + fdt_size = write_data(image, size, fdt->addr, fdt->fname, 0, 0); if (fdt_size < 0) return fdt_size; - blob = (void *)image + (uint32_t)(fdt->addr + size); + + uboot_top = (uint32_t)(fdt->addr + size) + fdt_size; if (ucode_ptr) { - return write_ucode(image, size, fdt, fdt_size, ucode_ptr, - collate_ucode); + uboot_top = write_ucode(image, size, fdt, fdt_size, ucode_ptr, + collate_ucode); + if (uboot_top < 0) + return uboot_top; } - return ((char *)blob + fdt_size) - image; + if (offset_uboot_top && offset_uboot_start) { + *offset_uboot_top = uboot_top; + *offset_uboot_start = (uint32_t)(uboot->addr + size); + } + + return 0; } static void print_version(void) @@ -1268,13 +1291,14 @@ int main(int argc, char *argv[]) } if (mode_write_descriptor) - ret = write_data(image, size, -size, desc_fname, 0); + ret = write_data(image, size, -size, desc_fname, 0, 0); if (mode_inject) ret = inject_region(image, size, region_type, inject_fname); if (mode_write) { int offset_uboot_top = 0; + int offset_uboot_start = 0; for (wr_idx = 0; wr_idx < wr_num; wr_idx++) { ifile = &input_file[wr_idx]; @@ -1282,11 +1306,13 @@ int main(int argc, char *argv[]) continue; } else if (ifile->type == IF_uboot) { ret = write_uboot(image, size, ifile, fdt, - ucode_ptr, collate_ucode); - offset_uboot_top = ret; + ucode_ptr, collate_ucode, + &offset_uboot_top, + &offset_uboot_start); } else { ret = write_data(image, size, ifile->addr, - ifile->fname, offset_uboot_top); + ifile->fname, offset_uboot_top, + offset_uboot_start); } if (ret < 0) break; -- 1.8.2.1

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Re: [U-Boot] [PATCH 1/3] x86: ifdtool: Support checking region overlap before U-Boot
by Simon Glass 01 Sep '15

01 Sep '15

On 27 August 2015 at 10:01, Andy Pont <andy.pont(a)sdcsystems.com> wrote: > Bin wrote... > >> We have the capability to check regions written after U-Boot that >> do not overlap. Since regions can also be written before U-Boot, >> add such check for these too. >> >> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> >> --- > > This fixes the issue I raised this morning with building the .rom file for > Galileo with the latest master, so: > > Tested-by: Andy Pont <andy.pont(a)sdcsystems.com> Acked-by: Simon Glass <sjg(a)chromium.org> Tested on Minnowmax: Tested-by: Simon Glass <sjg(a)chromium.org>

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