September 2015 - U-Boot

[U-Boot] dm gpio
by Bin Meng 02 Sep '15

02 Sep '15

Hi Simon, I have the following codes to control a gpio pin in my board codes: void board_assert_perst(void) { gpio_request(32, "PERST"); gpio_direction_output(32, 0); } But when I read <asm-generic/gpio.h>, I found these two apis are deprecated. Instead it suggests we should use corresponding dm gpio apis like gpio_request_by_name(), etc. However these dm gpio apis takes one udevice* as a parameter, which requires a dm driver. I don't think I am going to create a dm driver for this. What's the guideline here? Regards, Bin

2 2

[U-Boot] [PATCH] pci/layerscape: Setup mmu-masters property for the PCIe
by Varun Sethi 02 Sep '15

02 Sep '15

Setup mmu-masters property for the PCIe controllers. This would be used by the Linux SMMU driver, while setting up stream ID table mappings for the PCIe devices. Signed-off-by: Varun Sethi <Varun.Sethi(a)freescale.com> --- drivers/pci/pcie_layerscape.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 95cfe8c..2f24a6a 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -689,6 +689,7 @@ void fdt_fixup_smmu_pcie(void *blob) { int count; u32 stream_ids[MAX_STREAM_IDS]; + u32 ctlr_streamid = 0x300; #ifdef CONFIG_PCIE1 /* PEX1 stream ID fixup */ @@ -696,6 +697,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE2 @@ -704,6 +707,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE3 @@ -712,6 +717,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000", + &ctlr_streamid, 1); #endif #ifdef CONFIG_PCIE4 @@ -720,6 +727,8 @@ void fdt_fixup_smmu_pcie(void *blob) alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids, MAX_STREAM_IDS); pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count); + append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000", + &ctlr_streamid, 1); #endif } #endif -- 1.7.9.5

2 1

[U-Boot] [PATCH v3] armv8: fsl-lsch3: Rewrite MMU translation table entries
by Alison Wang 02 Sep '15

02 Sep '15

This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang(a)freescale.com> Signed-off-by: York Sun <yorksun(a)freescale.com> --- Changes in v3: - Make only the first 4MB cache-enabled for IFC Region #1. - Make only the first 64MB cache-enabled for QBMAN portal. Changes in v2: - Rebase the patch. - Fix build error for emu and emu_D4 defconfig. arch/arm/cpu/armv8/cache_v8.c | 17 +- arch/arm/cpu/armv8/fsl-lsch3/README | 71 ++++ arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 474 +++++++++++++++++---------- arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + arch/arm/include/asm/armv8/mmu.h | 8 +- 5 files changed, 392 insertions(+), 179 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c5ec529..978175f 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,13 +12,22 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_DCACHE_OFF -void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type) +inline void set_pgtable_section(u64 *page_table, u64 index, u64 section, + u64 memory_type, u64 share) { u64 value; value = section | PMD_TYPE_SECT | PMD_SECT_AF; value |= PMD_ATTRINDX(memory_type); + value |= share; + page_table[index] = value; +} + +inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) +{ + u64 value; + + value = (u64)table_addr | PMD_TYPE_TABLE; page_table[index] = value; } @@ -32,7 +41,7 @@ static void mmu_setup(void) /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, - MT_DEVICE_NGNRNE); + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE); } /* Setup an identity-mapping for all RAM space */ @@ -42,7 +51,7 @@ static void mmu_setup(void) for (j = start >> SECTION_SHIFT; j < end >> SECTION_SHIFT; j++) { set_pgtable_section(page_table, j, j << SECTION_SHIFT, - MT_NORMAL); + MT_NORMAL, PMD_SECT_NON_SHARE); } } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 3c15479..08da7e4 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -171,3 +171,74 @@ nand write <u-boot image in memory> 80000 <size of u-boot image> Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image to match board NAND device with 4KB/page, block size 512KB. + +MMU Translation Tables +====================== + +(1) Early MMU Tables: + + Level 0 Level 1 Level 2 +------------------ ------------------ ------------------ +| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | +------------------ ------------------ ------------------ +| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | +------------------ | ------------------ ------------------ +| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | +------------------ | ------------------ ------------------ + | | 0x00_c000_0000 | | 0x00_0060_0000 | + | ------------------ ------------------ + | | 0x01_0000_0000 | | 0x00_0080_0000 | + | ------------------ ------------------ + | ... ... + | ------------------ + | | 0x05_8000_0000 | --| + | ------------------ | + | | 0x05_c000_0000 | | + | ------------------ | + | ... | + | ------------------ | ------------------ + |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | + ------------------ ------------------ + | 0x80_4000_0000 | | 0x00_3020_0000 | + ------------------ ------------------ + | 0x80_8000_0000 | | 0x00_3040_0000 | + ------------------ ------------------ + | 0x80_c000_0000 | | 0x00_3060_0000 | + ------------------ ------------------ + | 0x81_0000_0000 | | 0x00_3080_0000 | + ------------------ ------------------ + ... ... + +(2) Final MMU Tables: + + Level 0 Level 1 Level 2 +------------------ ------------------ ------------------ +| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | +------------------ ------------------ ------------------ +| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | +------------------ | ------------------ ------------------ +| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | +------------------ | ------------------ ------------------ + | | 0x00_c000_0000 | | 0x00_0060_0000 | + | ------------------ ------------------ + | | 0x01_0000_0000 | | 0x00_0080_0000 | + | ------------------ ------------------ + | ... ... + | ------------------ + | | 0x08_0000_0000 | --| + | ------------------ | + | | 0x08_4000_0000 | | + | ------------------ | + | ... | + | ------------------ | ------------------ + |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | + ------------------ ------------------ + | 0x80_4000_0000 | | 0x08_0020_0000 | + ------------------ ------------------ + | 0x80_8000_0000 | | 0x08_0040_0000 | + ------------------ ------------------ + | 0x80_c000_0000 | | 0x08_0060_0000 | + ------------------ ------------------ + | 0x81_0000_0000 | | 0x08_0080_0000 | + ------------------ ------------------ + ... ... diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index d02c0be..eb1213e 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/errno.h> #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/io.h> @@ -53,27 +54,16 @@ void cpu_name(char *name) } #ifndef CONFIG_SYS_DCACHE_OFF -/* - * To start MMU before DDR is available, we create MMU table in SRAM. - * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three - * levels of translation tables here to cover 40-bit address space. - * We use 4KB granule size, with 40 bits physical address, T0SZ=24 - * Level 0 IA[39], table address @0 - * Level 1 IA[31:30], table address @0x1000, 0x2000 - * Level 2 IA[29:21], table address @0x3000, 0x4000 - * Address above 0x5000 is free for other purpose. - */ -#define SECTION_SHIFT_L0 39UL -#define SECTION_SHIFT_L1 30UL -#define SECTION_SHIFT_L2 21UL -#define BLOCK_SIZE_L0 0x8000000000UL -#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) -#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) -#define CONFIG_SYS_IFC_BASE 0x30000000 -#define CONFIG_SYS_IFC_SIZE 0x10000000 -#define CONFIG_SYS_IFC_BASE2 0x500000000 -#define CONFIG_SYS_IFC_SIZE2 0x100000000 +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000 +#define BLOCK_SIZE_L1 0x40000000 +#define BLOCK_SIZE_L2 0x200000 + +#define NUM_OF_ENTRY 512 + #define TCR_EL2_PS_40BIT (2 << 16) #define LSCH3_VA_BITS (40) #define LSCH3_TCR (TCR_TG0_4K | \ @@ -89,95 +79,265 @@ void cpu_name(char *name) TCR_IRGN_WBWA | \ TCR_T0SZ(LSCH3_VA_BITS)) +#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 +#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 +#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 +#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 +#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 +#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 +#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 +#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 +#define CONFIG_SYS_FSL_NI_BASE 0x810000000 +#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 +#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 +#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 + +struct sys_mmu_table { + u64 virt_addr; + u64 phys_addr; + u64 size; + u64 memory_type; + u64 share; +}; + +static const struct sys_mmu_table lsch3_early_mmu_table[] = { + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +}; + +static const struct sys_mmu_table lsch3_final_mmu_table[] = { + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#ifdef CONFIG_LS2085A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +}; + +struct table_info { + u64 *ptr; + u64 table_base; + u64 entry_size; +}; + /* - * Final MMU - * Let's start from the same layout as early MMU and modify as needed. - * IFC regions will be cache-inhibit. + * Set the block entries according to the information of the table. */ -#define FINAL_QBMAN_CACHED_MEM 0x818000000UL -#define FINAL_QBMAN_CACHED_SIZE 0x4000000 +static int set_block_entry(const struct sys_mmu_table *list, + struct table_info *table) +{ + u64 block_size = 0, block_shift = 0; + u64 block_addr, index; + int j; + + if (table->entry_size == BLOCK_SIZE_L1) { + block_size = BLOCK_SIZE_L1; + block_shift = SECTION_SHIFT_L1; + } else if (table->entry_size == BLOCK_SIZE_L2) { + block_size = BLOCK_SIZE_L2; + block_shift = SECTION_SHIFT_L2; + } else { + return -EINVAL; + } + block_addr = list->phys_addr; + index = (list->virt_addr - table->table_base) >> block_shift; + + for (j = 0; j < (list->size >> block_shift); j++) { + set_pgtable_section(table->ptr, + index, + block_addr, + list->memory_type, + list->share); + block_addr += block_size; + index++; + } -static inline void early_mmu_setup(void) + return 0; +} + +/* + * Find the corresponding table entry for the list. + */ +static int find_table(const struct sys_mmu_table *list, + struct table_info *table, u64 *level0_table) { - int el; - u64 i; - u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1; - u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; - u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); - u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); - u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); - u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + u64 index = 0, level = 0; + u64 *level_table = level0_table; + u64 temp_base = 0, block_size = 0, block_shift = 0; + + while (level < 3) { + if (level == 0) { + block_size = BLOCK_SIZE_L0; + block_shift = SECTION_SHIFT_L0; + } else if (level == 1) { + block_size = BLOCK_SIZE_L1; + block_shift = SECTION_SHIFT_L1; + } else if (level == 2) { + block_size = BLOCK_SIZE_L2; + block_shift = SECTION_SHIFT_L2; + } - level0_table[0] = - (u64)level1_table_0 | PMD_TYPE_TABLE; - level0_table[1] = - (u64)level1_table_1 | PMD_TYPE_TABLE; + index = 0; + while (list->virt_addr >= temp_base) { + index++; + temp_base += block_size; + } - /* - * set level 1 table 0 to cache_inhibit, covering 0 to 512GB - * set level 1 table 1 to cache enabled, covering 512GB to 1TB - * set level 2 table to cache-inhibit, covering 0 to 1GB - */ - section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0; - section_l2t0 = 0; - section_l2t1 = CONFIG_SYS_FLASH_BASE; - for (i = 0; i < 512; i++) { - set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); - set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); - set_pgtable_section(level2_table_0, i, section_l2t0, - MT_DEVICE_NGNRNE); - set_pgtable_section(level2_table_1, i, section_l2t1, - MT_DEVICE_NGNRNE); - section_l1t0 += BLOCK_SIZE_L1; - section_l1t1 += BLOCK_SIZE_L1; - section_l2t0 += BLOCK_SIZE_L2; - section_l2t1 += BLOCK_SIZE_L2; + temp_base -= block_size; + + if ((level_table[index - 1] & PMD_TYPE_MASK) == + PMD_TYPE_TABLE) { + level_table = (u64 *)(level_table[index - 1] & + ~PMD_TYPE_MASK); + level++; + continue; + } else { + if (level == 0) + return -EINVAL; + + if ((list->phys_addr + list->size) > + (temp_base + block_size * NUM_OF_ENTRY)) + return -EINVAL; + + /* + * Check the address and size of the list member is + * aligned with the block size. + */ + if (((list->phys_addr & (block_size - 1)) != 0) || + ((list->size & (block_size - 1)) != 0)) + return -EINVAL; + + table->ptr = level_table; + table->table_base = temp_base - + ((index - 1) << block_shift); + table->entry_size = block_size; + + return 0; + } } + return -EINVAL; +} - level1_table_0[0] = - (u64)level2_table_0 | PMD_TYPE_TABLE; - level1_table_0[1] = - 0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_DEVICE_NGNRNE); - level1_table_0[2] = - 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); - level1_table_0[3] = - 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); - - /* Rewerite table to enable cache for OCRAM */ - set_pgtable_section(level2_table_0, - CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, - CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); - -#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY) - /* Rewrite table to enable cache for two entries (4MB) */ - section_l2t1 = CONFIG_SYS_IFC_BASE; - set_pgtable_section(level2_table_0, - section_l2t1 >> SECTION_SHIFT_L2, - section_l2t1, - MT_NORMAL); - section_l2t1 += BLOCK_SIZE_L2; - set_pgtable_section(level2_table_0, - section_l2t1 >> SECTION_SHIFT_L2, - section_l2t1, - MT_NORMAL); -#endif - - /* Create a mapping for 256MB IFC region to final flash location */ - level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] = - (u64)level2_table_1 | PMD_TYPE_TABLE; - section_l2t1 = CONFIG_SYS_IFC_BASE; - for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) { - set_pgtable_section(level2_table_1, i, - section_l2t1, MT_DEVICE_NGNRNE); - section_l2t1 += BLOCK_SIZE_L2; +/* + * To start MMU before DDR is available, we create MMU table in SRAM. + * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three + * levels of translation tables here to cover 40-bit address space. + * We use 4KB granule size, with 40 bits physical address, T0SZ=24 + * Level 0 IA[39], table address @0 + * Level 1 IA[38:30], table address @0x1000, 0x2000 + * Level 2 IA[29:21], table address @0x3000, 0x4000 + * Address above 0x5000 is free for other purpose. + */ +static inline void early_mmu_setup(void) +{ + unsigned int el, i; + u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; + u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); + u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); + u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); + u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + + /* Invalidate all table entries */ + memset(level0_table, 0, 0x5000); + + /* Fill in the table entries */ + set_pgtable_table(level0_table, 0, level1_table0); + set_pgtable_table(level0_table, 1, level1_table1); + set_pgtable_table(level1_table0, 0, level2_table0); + set_pgtable_table(level1_table0, + CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, + level2_table1); + + /* Find the table and fill in the block entries */ + for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) { + if (find_table(&lsch3_early_mmu_table[i], + &table, level0_table) == 0) { + /* + * If find_table() returns error, it cannot be dealt + * with here. Breakpoint can be added for debugging. + */ + set_block_entry(&lsch3_early_mmu_table[i], &table); + /* + * If set_block_entry() returns error, it cannot be + * dealt with here too. + */ + } } el = current_el(); @@ -186,89 +346,55 @@ static inline void early_mmu_setup(void) } /* - * This final tale looks similar to early table, but different in detail. - * These tables are in regular memory. Cache on IFC is disabled. One sub table - * is added to enable cache for QBMan. + * The final tables look similar to early tables, but different in detail. + * These tables are in DRAM. Sub tables are added to enable cache for + * QBMan and OCRAM. + * + * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. + * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. + * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. + * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. */ static inline void final_mmu_setup(void) { - int el; - u64 i, tbl_base, tbl_limit, section_base; - u64 section_l1t0, section_l1t1, section_l2; + unsigned int el, i; u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000); - u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000); - u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000); - u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000); - - - level0_table[0] = - (u64)level1_table_0 | PMD_TYPE_TABLE; - level0_table[1] = - (u64)level1_table_1 | PMD_TYPE_TABLE; - - /* - * set level 1 table 0 to cache_inhibit, covering 0 to 512GB - * set level 1 table 1 to cache enabled, covering 512GB to 1TB - * set level 2 table 0 to cache-inhibit, covering 0 to 1GB - */ - section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE; - section_l2 = 0; - for (i = 0; i < 512; i++) { - set_pgtable_section(level1_table_0, i, section_l1t0, - MT_DEVICE_NGNRNE); - set_pgtable_section(level1_table_1, i, section_l1t1, - MT_NORMAL); - set_pgtable_section(level2_table_0, i, section_l2, - MT_DEVICE_NGNRNE); - section_l1t0 += BLOCK_SIZE_L1; - section_l1t1 += BLOCK_SIZE_L1; - section_l2 += BLOCK_SIZE_L2; - } - - level1_table_0[0] = - (u64)level2_table_0 | PMD_TYPE_TABLE; - level1_table_0[2] = - 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); - level1_table_0[3] = - 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); - - /* Rewrite table to enable cache */ - set_pgtable_section(level2_table_0, - CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2, - CONFIG_SYS_FSL_OCRAM_BASE, - MT_NORMAL); + u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); + u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); + u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); + u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + /* Fill in the table entries */ + set_pgtable_table(level0_table, 0, level1_table0); + set_pgtable_table(level0_table, 1, level1_table1); + set_pgtable_table(level1_table0, 0, level2_table0); + set_pgtable_table(level1_table0, + CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, + level2_table1); + + /* Find the table and fill in the block entries */ + for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) { + if (find_table(&lsch3_final_mmu_table[i], + &table, level0_table) == 0) { + if (set_block_entry(&lsch3_final_mmu_table[i], + &table) != 0) { + printf("MMU error: could not set block entry for %p\n", + &lsch3_final_mmu_table[i]); + } - /* - * Fill in other part of tables if cache is needed - * If finer granularity than 1GB is needed, sub table - * should be created. - */ - section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1); - i = section_base >> SECTION_SHIFT_L1; - level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE; - section_l2 = section_base; - for (i = 0; i < 512; i++) { - set_pgtable_section(level2_table_1, i, section_l2, - MT_DEVICE_NGNRNE); - section_l2 += BLOCK_SIZE_L2; - } - tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1); - tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) & - (BLOCK_SIZE_L1 - 1); - for (i = tbl_base >> SECTION_SHIFT_L2; - i < tbl_limit >> SECTION_SHIFT_L2; i++) { - section_l2 = section_base + (i << SECTION_SHIFT_L2); - set_pgtable_section(level2_table_1, i, - section_l2, MT_NORMAL); + } else { + printf("MMU error: could not find the table for %p\n", + &lsch3_final_mmu_table[i]); + } } /* flush new MMU table */ flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + gd->arch.tlb_addr + gd->arch.tlb_size); /* point TTBR to the new table */ el = current_el(); diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 4e2c738..3cc0833 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -19,6 +19,7 @@ #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 04fa0be..0c928d4 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -65,6 +65,7 @@ /* * Section */ +#define PMD_SECT_NON_SHARE (0 << 8) #define PMD_SECT_OUTER_SHARE (2 << 8) #define PMD_SECT_INNER_SHARE (3 << 8) #define PMD_SECT_AF (1 << 10) @@ -110,8 +111,13 @@ TCR_T0SZ(VA_BITS)) #ifndef __ASSEMBLY__ + void set_pgtable_section(u64 *page_table, u64 index, - u64 section, u64 memory_type); + u64 section, u64 memory_type, + u64 share); +void set_pgtable_table(u64 *page_table, u64 index, + u64 *table_addr); + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH v2 1/1] arm/ls102xa:add hwconfig setting to support disable unused devices.
by Zhuoyu Zhang 02 Sep '15

02 Sep '15

DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang(a)freescale.com> --- Change log: v2 use CONFIG_FSL_DEVICE_DISABLE instead of CONFIG_DEVICE_DISABLE. arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h | 52 ++++++++++++++++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 5 +++ board/freescale/ls1021atwr/ls1021atwr.c | 5 +++ drivers/misc/Makefile | 1 + drivers/misc/fsl_devdis.c | 29 ++++++++++++ include/configs/ls1021aqds.h | 4 +- include/configs/ls1021atwr.h | 4 +- include/fsl_devdis.h | 18 ++++++++ 8 files changed, 116 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h create mode 100644 drivers/misc/fsl_devdis.c create mode 100644 include/fsl_devdis.h diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h new file mode 100644 index 0000000..3e9e9ea --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h @@ -0,0 +1,52 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_DEVDIS_H_ +#define __FSL_LS102XA_DEVDIS_H_ + +#include <fsl_devdis.h> + +const struct devdis_table devdis_tbl[] = { + { "pbl", 0x0, 0x80000000 }, /* PBL */ + { "esdhc", 0x0, 0x20000000 }, /* eSDHC */ + { "qdma", 0x0, 0x800000 }, /* qDMA */ + { "edma", 0x0, 0x400000 }, /* eDMA */ + { "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/ + { "usb2", 0x0, 0x40000 }, /* USB2.0 controller */ + { "sata", 0x0, 0x8000 }, /* SATA */ + { "sec", 0x0, 0x200 }, /* SEC */ + { "dcu", 0x0, 0x2 }, /* Display controller Unit */ + { "qe", 0x0, 0x1 }, /* QUICC Engine */ + { "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */ + { "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */ + { "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */ + { "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */ + { "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */ + { "duart1", 0x3, 0x20000000 }, /* DUART1 */ + { "duart2", 0x3, 0x10000000 }, /* DUART2 */ + { "qspi", 0x3, 0x8000000 }, /* QSPI */ + { "ddr", 0x4, 0x80000000 }, /* DDR */ + { "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */ + { "ifc", 0x4, 0x800000 }, /* IFC */ + { "gpio", 0x4, 0x400000 }, /* GPIO */ + { "dbg", 0x4, 0x200000 }, /* DBG */ + { "can1", 0x4, 0x80000 }, /* FlexCAN1 */ + { "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */ + { "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */ + { "secmon", 0x4, 0x4000 }, /* Security Monitor */ + { "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */ + { "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */ + { "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */ + { "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */ + { "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */ + { "asrc", 0x4, 0x20 }, /* ASRC */ + { "spdif", 0x4, 0x10 }, /* SPDIF */ + { "i2c1", 0x4, 0x4 }, /* I2C1 */ + { "lpuart1", 0x4, 0x2 }, /* LPUART1 */ + { "ftm1", 0x4, 0x1 }, /* FlexTimer1 */ +}; + +#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d6ef6ba..a1c10cf 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -12,12 +12,14 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <fsl_sec.h> #include <spl.h> +#include <fsl_devdis.h> #include "../common/sleep.h" #include "../common/qixis.h" @@ -530,6 +532,9 @@ int misc_init_r(void) else if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif #ifdef CONFIG_FSL_CAAM return sec_init(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9..5ebe781 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/ls102xa_stream_id.h> +#include <asm/arch/ls102xa_devdis.h> #include <hwconfig.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -21,6 +22,7 @@ #include <fsl_mdio.h> #include <tsec.h> #include <fsl_sec.h> +#include <fsl_devdis.h> #include <spl.h> #include "../common/sleep.h" #ifdef CONFIG_U_QE @@ -651,6 +653,9 @@ int board_init(void) #if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif #ifndef CONFIG_QSPI_BOOT config_board_mux(); #endif diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 5218b91..8d0fc3c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,3 +35,4 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o obj-$(CONFIG_RESET) += reset-uclass.o +obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c new file mode 100644 index 0000000..996f45c --- /dev/null +++ b/drivers/misc/fsl_devdis.c @@ -0,0 +1,29 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Author: Zhuoyu Zhang <Zhuoyu.Zhang(a)freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch-ls102xa/immap_ls102xa.h> +#include <asm/arch-ls102xa/config.h> +#include <linux/compiler.h> +#include <hwconfig.h> +#include <fsl_devdis.h> + +void device_disable(const struct devdis_table *tbl, uint32_t num) +{ + int i; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + /* + * Extract hwconfig from environment and disable unused device. + */ + for (i = 0; i < num; i++) { + if (hwconfig_sub("devdis", tbl[i].name)) + setbits_be32(&gur->devdisr + tbl[i].offset, + tbl[i].mask); + } +} + diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 0871a71..f8710ed 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -567,7 +567,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index df7af3c..56e5808 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -415,7 +415,9 @@ #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE #define CONFIG_BOOTDELAY 3 diff --git a/include/fsl_devdis.h b/include/fsl_devdis.h new file mode 100644 index 0000000..02415fe --- /dev/null +++ b/include/fsl_devdis.h @@ -0,0 +1,18 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_DEVDIS_H_ +#define __FSL_DEVDIS_H_ + +struct devdis_table { + char name[32]; + u32 offset; + u32 mask; +}; + +void device_disable(const struct devdis_table *tbl, uint32_t num); + +#endif -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] Move malloc_cache_aligned() to malloc.h
by Simon Glass 02 Sep '15

02 Sep '15

At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to malloc.h so that this can be avoided. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- fs/ubifs/super.c | 2 ++ include/common.h | 9 --------- include/malloc.h | 12 ++++++++++++ lib/zlib/zutil.c | 4 +++- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 0bf52db..74edff1 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -28,6 +28,8 @@ #include <linux/writeback.h> #else +#include <common.h> +#include <malloc.h> #include <linux/compat.h> #include <linux/stat.h> #include <linux/err.h> diff --git a/include/common.h b/include/common.h index c12f402..c48e5bc 100644 --- a/include/common.h +++ b/include/common.h @@ -1060,15 +1060,6 @@ int cpu_release(int nr, int argc, char * const argv[]); #define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) -#ifndef __ASSEMBLY__ -#include <malloc.h> - -static inline void *malloc_cache_aligned(size_t size) -{ - return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); -} -#endif - /* * check_member() - Check the offset of a structure member * diff --git a/include/malloc.h b/include/malloc.h index f4da9e6..1d6327e 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -953,6 +953,18 @@ extern ulong mem_malloc_start; extern ulong mem_malloc_end; extern ulong mem_malloc_brk; +/* + * ARCH_DMA_MINALIGN is defined by including common.h which should be the + * first include in a U-Boot C file. Protect this declaration for imported + * files which don't follow this convention, to avoid compile errors. + */ +#ifdef ARCH_DMA_MINALIGN +static inline void *malloc_cache_aligned(size_t size) +{ + return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN)); +} +#endif + void mem_malloc_init(ulong start, ulong size); #ifdef __cplusplus diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index 173a81d..227343e 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c @@ -43,7 +43,9 @@ void z_error (m) */ #ifndef MY_ZCALLOC /* Any system without a special alloc function */ -#ifndef __UBOOT__ +#ifdef __UBOOT__ +#include <malloc.h> +#else #ifndef STDC extern voidp malloc OF((uInt size)); extern voidp calloc OF((uInt items, uInt size)); -- 2.5.0.457.gab17608

3 3

[U-Boot] [PATCH v3] buildman: Improve the config comparison feature
by Simon Glass 02 Sep '15

02 Sep '15

At present buildman can compare configurations between commits but the feature is less useful than it could be. There is no summary by architecture and changes are not reported on a per-board basis. Correct these deficiencies so that it is possible to see exactly what is changing for any number of boards. Note that 'buildman -b <branch> -C' is recommended for any build where you will be comparing configuration. Without -C the correct configuration will not be reported since changes will often not be picked up. Reviewed-by: Joe Hershberger <joe.hershberger(a)ni.com> Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Remove commented-out test code from buildman Changes in v2: - Add patch to improve the buildman config comparison feature tools/buildman/builder.py | 186 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 142 insertions(+), 44 deletions(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index c7d3c86..141bf64 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -103,6 +103,24 @@ CONFIG_FILENAMES = [ 'u-boot.cfg', 'u-boot-spl.cfg', 'u-boot-tpl.cfg' ] +class Config: + """Holds information about configuration settings for a board.""" + def __init__(self, target): + self.target = target + self.config = {} + for fname in CONFIG_FILENAMES: + self.config[fname] = {} + + def Add(self, fname, key, value): + self.config[fname][key] = value + + def __hash__(self): + val = 0 + for fname in self.config: + for key, value in self.config[fname].iteritems(): + print key, value + val = val ^ hash(key) & hash(value) + return val class Builder: """Class for building U-Boot for a particular commit. @@ -659,7 +677,8 @@ class Builder: List containing a summary of warning lines Dict keyed by error line, containing a list of the Board objects with that warning - Dictionary keyed by filename - e.g. '.config'. Each + Dictionary keyed by board.target. Each value is a dictionary: + key: filename - e.g. '.config' value is itself a dictionary: key: config name value: config value @@ -678,8 +697,6 @@ class Builder: warn_lines_summary = [] warn_lines_boards = {} config = {} - for fname in CONFIG_FILENAMES: - config[fname] = {} for board in boards_selected.itervalues(): outcome = self.GetBuildOutcome(commit_upto, board.target, @@ -709,11 +726,12 @@ class Builder: line, board) last_was_warning = is_warning last_func = None + tconfig = Config(board.target) for fname in CONFIG_FILENAMES: - config[fname] = {} if outcome.config: for key, value in outcome.config[fname].iteritems(): - config[fname][key] = value + tconfig.Add(fname, key, value) + config[board.target] = tconfig return (board_dict, err_lines_summary, err_lines_boards, warn_lines_summary, warn_lines_boards, config) @@ -774,9 +792,7 @@ class Builder: self._base_warn_lines = [] self._base_err_line_boards = {} self._base_warn_line_boards = {} - self._base_config = {} - for fname in CONFIG_FILENAMES: - self._base_config[fname] = {} + self._base_config = None def PrintFuncSizeDetail(self, fname, old, new): grow, shrink, add, remove, up, down = 0, 0, 0, 0, 0, 0 @@ -1051,12 +1067,14 @@ class Builder: out = '' for key in sorted(config.keys()): out += '%s=%s ' % (key, config[key]) - return '%5s %s: %s' % (delta, name, out) + return '%s %s: %s' % (delta, name, out) - def _ShowConfig(name, config_plus, config_minus, config_change): - """Show changes in configuration + def _AddConfig(lines, name, config_plus, config_minus, config_change): + """Add changes in configuration to a list Args: + lines: list to add to + name: config file name config_plus: configurations added, dictionary key: config name value: config value @@ -1068,14 +1086,24 @@ class Builder: value: config value """ if config_plus: - Print(_CalcConfig('+', name, config_plus), - colour=self.col.GREEN) + lines.append(_CalcConfig('+', name, config_plus)) if config_minus: - Print(_CalcConfig('-', name, config_minus), - colour=self.col.RED) + lines.append(_CalcConfig('-', name, config_minus)) if config_change: - Print(_CalcConfig('+/-', name, config_change), - colour=self.col.YELLOW) + lines.append(_CalcConfig('c', name, config_change)) + + def _OutputConfigInfo(lines): + for line in lines: + if not line: + continue + if line[0] == '+': + col = self.col.GREEN + elif line[0] == '-': + col = self.col.RED + elif line[0] == 'c': + col = self.col.YELLOW + Print(' ' + line, newline=True, colour=col) + better = [] # List of boards fixed since last commit worse = [] # List of new broken boards since last commit @@ -1137,34 +1165,104 @@ class Builder: self.PrintSizeSummary(board_selected, board_dict, show_detail, show_bloat) - if show_config: - all_config_plus = {} - all_config_minus = {} - all_config_change = {} - for name in CONFIG_FILENAMES: - if not config[name]: + if show_config and self._base_config: + summary = {} + arch_config_plus = {} + arch_config_minus = {} + arch_config_change = {} + arch_list = [] + + for target in board_dict: + if target not in board_selected: + continue + arch = board_selected[target].arch + if arch not in arch_list: + arch_list.append(arch) + + for arch in arch_list: + arch_config_plus[arch] = {} + arch_config_minus[arch] = {} + arch_config_change[arch] = {} + for name in CONFIG_FILENAMES: + arch_config_plus[arch][name] = {} + arch_config_minus[arch][name] = {} + arch_config_change[arch][name] = {} + + for target in board_dict: + if target not in board_selected: continue - config_plus = {} - config_minus = {} - config_change = {} - base = self._base_config[name] - for key, value in config[name].iteritems(): - if key not in base: - config_plus[key] = value - all_config_plus[key] = value - for key, value in base.iteritems(): - if key not in config[name]: - config_minus[key] = value - all_config_minus[key] = value - for key, value in base.iteritems(): - new_value = base[key] - if key in config[name] and value != new_value: - desc = '%s -> %s' % (value, new_value) - config_change[key] = desc - all_config_change[key] = desc - _ShowConfig(name, config_plus, config_minus, config_change) - _ShowConfig('all', all_config_plus, all_config_minus, - all_config_change) + + arch = board_selected[target].arch + + all_config_plus = {} + all_config_minus = {} + all_config_change = {} + tbase = self._base_config[target] + tconfig = config[target] + lines = [] + for name in CONFIG_FILENAMES: + if not tconfig.config[name]: + continue + config_plus = {} + config_minus = {} + config_change = {} + base = tbase.config[name] + for key, value in tconfig.config[name].iteritems(): + if key not in base: + config_plus[key] = value + all_config_plus[key] = value + for key, value in base.iteritems(): + if key not in tconfig.config[name]: + config_minus[key] = value + all_config_minus[key] = value + for key, value in base.iteritems(): + new_value = tconfig.config.get(key) + if new_value and value != new_value: + desc = '%s -> %s' % (value, new_value) + config_change[key] = desc + all_config_change[key] = desc + + arch_config_plus[arch][name].update(config_plus) + arch_config_minus[arch][name].update(config_minus) + arch_config_change[arch][name].update(config_change) + + _AddConfig(lines, name, config_plus, config_minus, + config_change) + _AddConfig(lines, 'all', all_config_plus, all_config_minus, + all_config_change) + summary[target] = '\n'.join(lines) + + lines_by_target = {} + for target, lines in summary.iteritems(): + if lines in lines_by_target: + lines_by_target[lines].append(target) + else: + lines_by_target[lines] = [target] + + for arch in arch_list: + lines = [] + all_plus = {} + all_minus = {} + all_change = {} + for name in CONFIG_FILENAMES: + all_plus.update(arch_config_plus[arch][name]) + all_minus.update(arch_config_minus[arch][name]) + all_change.update(arch_config_change[arch][name]) + _AddConfig(lines, name, arch_config_plus[arch][name], + arch_config_minus[arch][name], + arch_config_change[arch][name]) + _AddConfig(lines, 'all', all_plus, all_minus, all_change) + #arch_summary[target] = '\n'.join(lines) + if lines: + Print('%s:' % arch) + _OutputConfigInfo(lines) + + for lines, targets in lines_by_target.iteritems(): + if not lines: + continue + Print('%s :' % ' '.join(sorted(targets))) + _OutputConfigInfo(lines.split('\n')) + # Save our updated information for the next call to this function self._base_board_dict = board_dict -- 2.5.0.457.gab17608

1 1

[U-Boot] [PATCH] ls102xa: etsec: Use proper settings for BE BDs
by Claudiu Manoil 02 Sep '15

02 Sep '15

Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil(a)freescale.com> --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 3 ++- board/freescale/ls1021atwr/ls1021atwr.c | 3 ++- drivers/net/tsec.c | 6 ------ 4 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index d34044a..60aa0d3 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -143,7 +143,7 @@ struct ccsr_gur { u32 sdhcpcr; }; -#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f +#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d6ef6ba..e585380 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -280,7 +280,8 @@ int board_early_init_f(void) unsigned int major; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); #endif #ifdef CONFIG_FSL_IFC diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index b7458a9..006700f 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -481,7 +481,8 @@ int board_early_init_f(void) unsigned int major; #ifdef CONFIG_TSEC_ENET - out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 42d0374..4bdc188 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -271,9 +271,6 @@ void redundant_init(struct eth_device *dev) out_be32(&regs->tstat, TSTAT_CLEAR_THALT); out_be32(&regs->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS); -#ifdef CONFIG_LS102XA - setbits_be32(&regs->dmactrl, DMACTRL_LE); -#endif do { uint16_t status; @@ -370,9 +367,6 @@ static void startup_tsec(struct eth_device *dev) out_be32(&regs->tstat, TSTAT_CLEAR_THALT); out_be32(&regs->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS); -#ifdef CONFIG_LS102XA - setbits_be32(&regs->dmactrl, DMACTRL_LE); -#endif } /* This returns the status bits of the device. The return value -- 1.7.11.7

3 2

[U-Boot] [PATCH][v3] driver: misc: debug server: Update Error message
by Prabhakar Kushwaha 02 Sep '15

02 Sep '15

Append "debug server FW" in error message to make more informative. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma(a)freescale.com> --- Changes for v2: Incorporated Bhupesh's review comments Changes for v3: Corrected description drivers/misc/fsl_debug_server.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c index 44cd9b9..a592891 100644 --- a/drivers/misc/fsl_debug_server.c +++ b/drivers/misc/fsl_debug_server.c @@ -60,29 +60,29 @@ int debug_server_parse_firmware_fit_image(const void **raw_image_addr, /* Check if Image is in FIT format */ format = genimg_get_format(fit_hdr); if (format != IMAGE_FORMAT_FIT) { - printf("Error! Not a FIT image\n"); + printf("Debug Server FW: Not a FIT image\n"); goto out_error; } if (!fit_check_format(fit_hdr)) { - printf("Error! Bad FIT image format\n"); + printf("Debug Server FW: Bad FIT image format\n"); goto out_error; } node_offset = fit_image_get_node(fit_hdr, uname); if (node_offset < 0) { - printf("Error! Can not find %s subimage\n", uname); + printf("Debug Server FW:Can not find %s subimage\n", uname); goto out_error; } /* Verify Debug Server firmware image */ if (!fit_image_verify(fit_hdr, node_offset)) { - printf("Error! Bad Debug Server firmware hash"); + printf("Debug Server FW: Bad Debug Server firmware hash"); goto out_error; } if (fit_get_desc(fit_hdr, node_offset, &desc) < 0) { - printf("Error! Failed to get Debug Server fw description"); + printf("Debug Server FW: Failed to get FW description"); goto out_error; } -- 1.9.1

2 1

[U-Boot] [PATCH 4/4] armv8: ls2085qds: Add support of X-QSGMII-16PORT riser card
by Prabhakar Kushwaha 02 Sep '15

02 Sep '15

The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes interfaces implemented in PCIe form factor board. It supports followings - Card can operate with up to 4 QSGMII lane simultaneously - Card can operate with up to 8 SGMII lane simultaneously Add support of X-QSGMII-16PORT riser card. This patch also take care of back-ward compatiblity with old SGMII rise cards used on LS2085QDS Platform. Signed-off-by: King Chung Lo(a)freescale.com <KingChungLo(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/ls2085aqds/README | 81 +++++++ board/freescale/ls2085aqds/eth.c | 466 +++++++++++++++++++++++++++++++++++++- include/configs/ls2085aqds.h | 17 ++ 3 files changed, 553 insertions(+), 11 deletions(-) diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README index 11b2e79..e4a6f69 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085aqds/README @@ -146,3 +146,84 @@ below: earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m hugepages=16 mem=2048M' + +X-QSGMII-16PORT riser card +---------------------------- +The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes +interfaces implemented in PCIe form factor board. +It supports followings + - Card can operate with up to 4 QSGMII lane simultaneously + - Card can operate with up to 8 SGMII lane simultaneously + +Supported card configuration + - CSEL : ON ON ON ON + - MSEL1 : ON ON ON ON OFF OFF OFF OFF + - MSEL2 : OFF OFF OFF OFF ON ON ON ON + +To enable this card: modify hwconfig to add "xqsgmii" variable. + +Supported PHY addresses during SGMII: +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P0 +DPMAC2 -> PHY2-P0 +DPMAC3 -> PHY3-P0 +DPMAC4 -> PHY4-P0 +DPMAC5 -> PHY3-P2 +DPMAC6 -> PHY1-P2 +DPMAC7 -> PHY4-P1 +DPMAC8 -> PHY2-P2 +DPMAC9 -> PHY1-P0 +DPMAC10 -> PHY2-P0 +DPMAC11 -> PHY3-P0 +DPMAC12 -> PHY4-P0 +DPMAC13 -> PHY3-P2 +DPMAC14 -> PHY1-P2 +DPMAC15 -> PHY4-P1 +DPMAC16 -> PHY2-P2 + + +Supported PHY address during QSGMII +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + +Mapping DPMACx to PHY during QSGMII +DPMAC1 -> PHY1-P3 +DPMAC2 -> PHY1-P2 +DPMAC3 -> PHY1-P1 +DPMAC4 -> PHY1-P0 +DPMAC5 -> PHY2-P3 +DPMAC6 -> PHY2-P2 +DPMAC7 -> PHY2-P1 +DPMAC8 -> PHY2-P0 +DPMAC9 -> PHY3-P0 +DPMAC10 -> PHY3-P1 +DPMAC11 -> PHY3-P2 +DPMAC12 -> PHY3-P3 +DPMAC13 -> PHY4-P0 +DPMAC14 -> PHY4-P1 +DPMAC15 -> PHY4-P2 +DPMAC16 -> PHY4-P3 + diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c index 1f8a31f..007b433 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2085aqds/eth.c @@ -9,9 +9,12 @@ #include <asm/io.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <hwconfig.h> #include <fsl_mdio.h> #include <malloc.h> #include <fm_eth.h> +#include <i2c.h> +#include <miiphy.h> #include <fsl-mc/ldpaa_wriop.h> #include "../common/qixis.h" @@ -30,6 +33,10 @@ * maps to something other than a board slot. */ +static u8 lane_to_slot_fsm1[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + static u8 lane_to_slot_fsm2[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; @@ -37,7 +44,19 @@ static u8 lane_to_slot_fsm2[] = { /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs * housed. */ -static int riser_phy_addr[] = { + +static int xqsgii_riser_phy_addr[] = { + XQSGMII_CARD_PHY1_PORT0_ADDR, + XQSGMII_CARD_PHY2_PORT0_ADDR, + XQSGMII_CARD_PHY3_PORT0_ADDR, + XQSGMII_CARD_PHY4_PORT0_ADDR, + XQSGMII_CARD_PHY3_PORT2_ADDR, + XQSGMII_CARD_PHY1_PORT2_ADDR, + XQSGMII_CARD_PHY4_PORT2_ADDR, + XQSGMII_CARD_PHY2_PORT2_ADDR, +}; + +static int sgmii_riser_phy_addr[] = { SGMII_CARD_PORT1_PHY_ADDR, SGMII_CARD_PORT2_PHY_ADDR, SGMII_CARD_PORT3_PHY_ADDR, @@ -70,6 +89,236 @@ struct ls2085a_qds_mdio { struct mii_dev *realbus; }; +static void sgmii_configure_repeater(int serdes_port) +{ + struct mii_dev *bus; + uint8_t a = 0xf; + int i, j, ret; + int dpmac_id = 0, dpmac, mii_bus = 0; + unsigned short value; + char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"}; + uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60}; + + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + + int *riser_phy_addr = &xqsgii_riser_phy_addr[0]; + + /* Set I2c to Slot 1 */ + i2c_write(0x77, 0, 0, &a, 1); + + for (dpmac = 0; dpmac < 8; dpmac++) { + /* Check the PHY status */ + switch (serdes_port) { + case 1: + mii_bus = 0; + dpmac_id = dpmac + 1; + break; + case 2: + mii_bus = 1; + dpmac_id = dpmac + 9; + a = 0xb; + i2c_write(0x76, 0, 0, &a, 1); + break; + } + + ret = miiphy_set_current_dev(dev[mii_bus]); + if (ret > 0) + goto error; + + bus = mdio_get_current_dev(); + debug("Reading from bus %s\n", bus->name); + + ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, + 3); + if (ret > 0) + goto error; + + mdelay(10); + ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11, + &value); + if (ret > 0) + goto error; + + mdelay(10); + + if ((value & 0xfff) == 0x40f) { + printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id); + continue; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + a = 0x18; + i2c_write(i2c_addr[dpmac], 6, 1, &a, 1); + a = 0x38; + i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + a = 0x4; + i2c_write(i2c_addr[dpmac], 8, 1, &a, 1); + + i2c_write(i2c_addr[dpmac], 0xf, 1, + &ch_a_eq[i], 1); + i2c_write(i2c_addr[dpmac], 0x11, 1, + &ch_a_ctl2[j], 1); + + i2c_write(i2c_addr[dpmac], 0x16, 1, + &ch_b_eq[i], 1); + i2c_write(i2c_addr[dpmac], 0x18, 1, + &ch_b_ctl2[j], 1); + + a = 0x14; + i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1); + a = 0xb5; + i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1); + a = 0x20; + i2c_write(i2c_addr[dpmac], 4, 1, &a, 1); + mdelay(100); + ret = miiphy_read(dev[mii_bus], + riser_phy_addr[dpmac], + 0x11, &value); + if (ret > 0) + goto error; + + mdelay(1); + ret = miiphy_read(dev[mii_bus], + riser_phy_addr[dpmac], + 0x11, &value); + if (ret > 0) + goto error; + mdelay(10); + + if ((value & 0xfff) == 0x40f) { + printf("DPMAC %d :PHY is configured ", + dpmac_id); + printf("after setting repeater 0x%x\n", + value); + i = 5; + j = 5; + } else + printf("DPMAC %d :PHY is failed to ", + dpmac_id); + printf("configure the repeater 0x%x\n", + value); + } + } + } +error: + if (ret) + printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id); + return; +} + +static void qsgmii_configure_repeater(int dpmac) +{ + uint8_t a = 0xf; + int i, j; + int i2c_phy_addr = 0; + int phy_addr = 0; + int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; + + uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; + uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + + const char *dev = "LS2085A_QDS_MDIO0"; + int ret = 0; + unsigned short value; + + /* Set I2c to Slot 1 */ + i2c_write(0x77, 0, 0, &a, 1); + + switch (dpmac) { + case 1: + case 2: + case 3: + case 4: + i2c_phy_addr = i2c_addr[0]; + phy_addr = 0; + break; + + case 5: + case 6: + case 7: + case 8: + i2c_phy_addr = i2c_addr[1]; + phy_addr = 4; + break; + + case 9: + case 10: + case 11: + case 12: + i2c_phy_addr = i2c_addr[2]; + phy_addr = 8; + break; + + case 13: + case 14: + case 15: + case 16: + i2c_phy_addr = i2c_addr[3]; + phy_addr = 0xc; + break; + } + + /* Check the PHY status */ + ret = miiphy_set_current_dev(dev); + ret = miiphy_write(dev, phy_addr, 0x1f, 3); + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + mdelay(10); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + mdelay(10); + if ((value & 0xf) == 0xf) { + printf("DPMAC %d :PHY is ..... Configured\n", dpmac); + return; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < 4; j++) { + a = 0x18; + i2c_write(i2c_phy_addr, 6, 1, &a, 1); + a = 0x38; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + a = 0x4; + i2c_write(i2c_phy_addr, 8, 1, &a, 1); + + i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); + i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); + + i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); + i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); + + a = 0x14; + i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); + a = 0xb5; + i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); + a = 0x20; + i2c_write(i2c_phy_addr, 4, 1, &a, 1); + mdelay(100); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + mdelay(1); + ret = miiphy_read(dev, phy_addr, 0x11, &value); + if (ret > 0) + goto error; + mdelay(10); + if ((value & 0xf) == 0xf) { + printf("DPMAC %d :PHY is ..... Configured\n", + dpmac); + return; + } + } + } +error: + printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac); + return; +} + static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval) { return mdio_names[muxval]; @@ -195,14 +444,38 @@ static void initialize_dpmac_to_slot(void) FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + char *env_hwconfig; + env_hwconfig = getenv("hwconfig"); switch (serdes1_prtcl) { + case 0x07: + case 0x09: + case 0x33: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + lane_to_slot_fsm1[0] = EMI1_SLOT1; + lane_to_slot_fsm1[1] = EMI1_SLOT1; + lane_to_slot_fsm1[2] = EMI1_SLOT1; + lane_to_slot_fsm1[3] = EMI1_SLOT1; + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm1[4] = EMI1_SLOT1; + lane_to_slot_fsm1[5] = EMI1_SLOT1; + lane_to_slot_fsm1[6] = EMI1_SLOT1; + lane_to_slot_fsm1[7] = EMI1_SLOT1; + } else { + lane_to_slot_fsm1[4] = EMI1_SLOT2; + lane_to_slot_fsm1[5] = EMI1_SLOT2; + lane_to_slot_fsm1[6] = EMI1_SLOT2; + lane_to_slot_fsm1[7] = EMI1_SLOT2; + } + break; + case 0x2A: - printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; } @@ -210,21 +483,30 @@ static void initialize_dpmac_to_slot(void) switch (serdes2_prtcl) { case 0x07: case 0x08: + case 0x09: case 0x49: - printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); lane_to_slot_fsm2[0] = EMI1_SLOT4; lane_to_slot_fsm2[1] = EMI1_SLOT4; lane_to_slot_fsm2[2] = EMI1_SLOT4; lane_to_slot_fsm2[3] = EMI1_SLOT4; - /* No MDIO physical connection */ - lane_to_slot_fsm2[4] = EMI1_SLOT6; - lane_to_slot_fsm2[5] = EMI1_SLOT6; - lane_to_slot_fsm2[6] = EMI1_SLOT6; - lane_to_slot_fsm2[7] = EMI1_SLOT6; + + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm2[4] = EMI1_SLOT4; + lane_to_slot_fsm2[5] = EMI1_SLOT4; + lane_to_slot_fsm2[6] = EMI1_SLOT4; + lane_to_slot_fsm2[7] = EMI1_SLOT4; + } else { + /* No MDIO physical connection */ + lane_to_slot_fsm2[4] = EMI1_SLOT6; + lane_to_slot_fsm2[5] = EMI1_SLOT6; + lane_to_slot_fsm2[6] = EMI1_SLOT6; + lane_to_slot_fsm2[7] = EMI1_SLOT6; + } break; default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } @@ -242,9 +524,69 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + int *riser_phy_addr; + char *env_hwconfig = getenv("hwconfig"); + + if (hwconfig_f("xqsgmii", env_hwconfig)) + riser_phy_addr = &xqsgii_riser_phy_addr[0]; + else + riser_phy_addr = &sgmii_riser_phy_addr[0]; + + if (dpmac_id > WRIOP1_DPMAC9) + goto serdes2; + switch (serdes1_prtcl) { + case 0x07: + + lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id); + slot = lane_to_slot_fsm1[lane]; + + switch (++slot) { + case 1: + /* Slot housing a SGMII riser card? */ + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 1]); + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; + bus = mii_dev_for_muxval(EMI1_SLOT1); + wriop_set_mdio(dpmac_id, bus); + dpmac_info[dpmac_id].phydev = phy_connect( + dpmac_info[dpmac_id].bus, + dpmac_info[dpmac_id].phy_addr, + NULL, + dpmac_info[dpmac_id].enet_if); + phy_config(dpmac_info[dpmac_id].phydev); + break; + case 2: + /* Slot housing a SGMII riser card? */ + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 1]); + dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; + bus = mii_dev_for_muxval(EMI1_SLOT2); + wriop_set_mdio(dpmac_id, bus); + dpmac_info[dpmac_id].phydev = phy_connect( + dpmac_info[dpmac_id].bus, + dpmac_info[dpmac_id].phy_addr, + NULL, + dpmac_info[dpmac_id].enet_if); + phy_config(dpmac_info[dpmac_id].phydev); + break; + case 3: + break; + case 4: + break; + case 5: + break; + case 6: + break; + } + break; + default: + printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + break; } +serdes2: switch (serdes2_prtcl) { case 0x07: case 0x08: @@ -285,11 +627,86 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) } break; default: - printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); break; } } + +void ls2085a_handle_phy_interface_qsgmii(int dpmac_id) +{ + int lane = 0, slot; + struct mii_dev *bus; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) + >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + switch (serdes1_prtcl) { + case 0x33: + switch (dpmac_id) { + case 1: + case 2: + case 3: + case 4: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A); + break; + case 5: + case 6: + case 7: + case 8: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B); + break; + case 9: + case 10: + case 11: + case 12: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C); + break; + case 13: + case 14: + case 15: + case 16: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D); + break; + } + + slot = lane_to_slot_fsm1[lane]; + + switch (++slot) { + case 1: + /* Slot housing a QSGMII riser card? */ + wriop_set_phy_address(dpmac_id, dpmac_id - 1); + dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; + bus = mii_dev_for_muxval(EMI1_SLOT1); + wriop_set_mdio(dpmac_id, bus); + dpmac_info[dpmac_id].phydev = phy_connect( + dpmac_info[dpmac_id].bus, + dpmac_info[dpmac_id].phy_addr, + NULL, + dpmac_info[dpmac_id].enet_if); + + phy_config(dpmac_info[dpmac_id].phydev); + break; + case 3: + break; + case 4: + break; + case 5: + break; + case 6: + break; + } + break; + default: + printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } + + qsgmii_configure_repeater(dpmac_id); +} + void ls2085a_handle_phy_interface_xsgmii(int i) { struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; @@ -324,9 +741,20 @@ int board_eth_init(bd_t *bis) { int error; #ifdef CONFIG_FSL_MC_ENET + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) + >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK) + >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + struct memac_mdio_info *memac_mdio0_info; struct memac_mdio_info *memac_mdio1_info; unsigned int i; + char *env_hwconfig; + + env_hwconfig = getenv("hwconfig"); initialize_dpmac_to_slot(); @@ -363,6 +791,7 @@ int board_eth_init(bd_t *bis) for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { switch (wriop_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: + ls2085a_handle_phy_interface_qsgmii(i); break; case PHY_INTERFACE_MODE_SGMII: ls2085a_handle_phy_interface_sgmii(i); @@ -372,11 +801,26 @@ int board_eth_init(bd_t *bis) break; default: break; + + if (i == 16) + i = NUM_WRIOP_PORTS; } } error = cpu_eth_init(bis); + + if (hwconfig_f("xqsgmii", env_hwconfig)) { + if (serdes1_prtcl == 0x7) + sgmii_configure_repeater(1); + if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 || + serdes2_prtcl == 0x49) + sgmii_configure_repeater(2); + } #endif error = pci_eth_init(bis); return error; } + +#ifdef CONFIG_FSL_MC_ENET + +#endif diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index f380ecc..5903aee 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -396,6 +396,23 @@ unsigned long get_board_ddr_clk(void); #define SGMII_CARD_PORT3_PHY_ADDR 0x1E #define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 +#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 +#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 +#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 +#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 +#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 +#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 +#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 +#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 +#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 +#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa +#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb +#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc +#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd +#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe +#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf + #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "DPNI1" #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ -- 1.9.1

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[U-Boot] [PATCH 3/4] net: phy/vitesse: Add support for VSC8584 phy
by Prabhakar Kushwaha 02 Sep '15

02 Sep '15

Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards used on LS2085QDS platforms. Signed-off-by: King Chung Lo(a)freescale.com <KingChungLo(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/net/phy/vitesse.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 20a6746..941d076 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -347,6 +347,16 @@ static struct phy_driver VSC8514_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8584_driver = { + .name = "Vitesse VSC8584", + .uid = 0x707c0, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8574_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + static struct phy_driver VSC8601_driver = { .name = "Vitesse VSC8601", .uid = 0x70420, @@ -417,6 +427,7 @@ int phy_vitesse_init(void) phy_register(&VSC8211_driver); phy_register(&VSC8221_driver); phy_register(&VSC8574_driver); + phy_register(&VSC8584_driver); phy_register(&VSC8514_driver); phy_register(&VSC8662_driver); phy_register(&VSC8664_driver); -- 1.9.1

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