September 2015 - U-Boot

[U-Boot] [PATCH v2 1/2] usb: zynqmp: Add XHCI driver support
by Siva Durga Prasad Paladugu 01 Sep '15

01 Sep '15

Added USB XHCI driver support for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- Changes for v2: - Moved all from xhci-zynqmp.h to .c file as per review comment - Removed ad-hoc function zynqmp_xhci_core_exit() as per review comment --- drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-zynqmp.c | 147 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/xhci-zynqmp.c diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index f70f38c..645b990 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o +obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c new file mode 100644 index 0000000..bb23afa --- /dev/null +++ b/drivers/usb/host/xhci-zynqmp.c @@ -0,0 +1,147 @@ +/* + * Copyright 2015 Xilinx, Inc. + * + * Zynq USB HOST xHCI Controller + * + * Author: Siva Durga Prasad Paladugu<sivadur(a)xilinx.com> + * + * This file was reused from Freescale USB xHCI + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <asm-generic/errno.h> +#include <asm/arch-zynqmp/hardware.h> +#include <linux/compat.h> +#include <linux/usb/xhci-zynqmp.h> +#include <linux/usb/dwc3.h> +#include "xhci.h" + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* Default to the ZYNQMP XHCI defines */ +#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 +#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC +#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) +#define USB3_PHY_RX_POWERON BIT(14) +#define USB3_PHY_TX_POWERON BIT(15) +#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) +#define USB3_PWRCTL_CLK_CMD_SHIFT 14 +#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 + +/* USBOTGSS_WRAPPER definitions */ +#define USBOTGSS_WRAPRESET BIT(17) +#define USBOTGSS_DMADISABLE BIT(16) +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) +#define USBOTGSS_STANDBYMODE_SMRT BIT(5) +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) +#define USBOTGSS_IDLEMODE_SMRT BIT(3) +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) + +/* USBOTGSS_IRQENABLE_SET_0 bit */ +#define USBOTGSS_COREIRQ_EN BIT(1) + +/* USBOTGSS_IRQENABLE_SET_1 bits */ +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) +#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) + +struct zynqmp_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; +}; + +static struct zynqmp_xhci zynqmp_xhci; + +unsigned long ctr_addr[] = {ZYNQMP_USB0_XHCI_BASEADDR, + ZYNQMP_USB1_XHCI_BASEADDR}; + +__weak int __board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} + +void usb_phy_reset(struct dwc3 *dwc3_reg) +{ + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + + mdelay(200); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); +} + +static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci) +{ + int ret = 0; + + ret = dwc3_core_init(zynqmp_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return ret; +} + +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct zynqmp_xhci *ctx = &zynqmp_xhci; + int ret = 0; + + ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + + ret = board_usb_init(index, USB_INIT_HOST); + if (ret != 0) { + puts("Failed to initialize board for USB\n"); + return ret; + } + + ret = zynqmp_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + *hcor = (struct xhci_hcor *)((uint32_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + /* + * Currently zynqmp socs do not support PHY shutdown from + * sw. But this support may be added in future socs. + */ + + return 0; +} -- 1.7.1

2 9

[U-Boot] [PATCH][v2] thermal: imx: add imx7d soc thermal support
by Adrian Alonso 01 Sep '15

01 Sep '15

Add imx7 SoC thermal driver support Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- Changes for V2: Fix build error for missin macro check ;P drivers/thermal/imx_thermal.c | 86 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 81 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 7848dc3..f3b0ac3 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -25,6 +25,9 @@ #define FACTOR1 15976 #define FACTOR2 4297157 #define MEASURE_FREQ 327 +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 85 +#define TEMPERATURE_MAX 125 #define TEMPSENSE0_TEMP_CNT_SHIFT 8 #define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT) @@ -41,7 +44,8 @@ struct thermal_data { int maxc; }; -static int read_cpu_temperature_mx6(struct udevice *dev) +#if defined(CONFIG_MX6) +static int read_cpu_temperature(struct udevice *dev) { int temperature; unsigned int reg, n_meas; @@ -123,22 +127,87 @@ static int read_cpu_temperature_mx6(struct udevice *dev) return temperature; } +#elif defined(CONFIG_MX7) +static int read_cpu_temperature(struct udevice *dev) +{ + unsigned int reg, tmp, start; + unsigned int raw_25c, te1; + int temperature; + unsigned int *priv = dev_get_priv(dev); + u32 fuse = *priv; + struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) + ANATOP_BASE_ADDR; + /* + * fuse data layout: + * [31:21] sensor value @ 25C + * [20:18] hot temperature value + * [17:9] sensor value of room + * [8:0] sensor value of hot + */ + + raw_25c = fuse >> 21; + if (raw_25c == 0) + raw_25c = 25; + + te1 = (fuse >> 9) & 0x1ff; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_clr); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_set); + + /* write measure freq */ + reg = readl(&ccm_anatop->tempsense1); + reg &= ~TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK; + reg |= TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(MEASURE_FREQ); + writel(reg, &ccm_anatop->tempsense1); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); + + start = get_timer(0); + /* Wait max 100ms */ + do { + /* + * Since we can not rely on finish bit, use 1ms delay to get + * temperature. From RM, 17us is enough to get data, but + * to gurantee to get the data, delay 100ms here. + */ + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } while (get_timer(0) < (start + 100)); + + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); + + /* power down anatop thermal sensor */ + writel(TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK, &ccm_anatop->tempsense1_set); + writel(PMU_REF_REFTOP_SELFBIASOFF_MASK, &ccm_anatop->ref_clr); + + /* Single point */ + temperature = tmp - (te1 - raw_25c); + + return temperature; +} +#endif int imx_thermal_get_temp(struct udevice *dev, int *temp) { struct thermal_data *priv = dev_get_priv(dev); int cpu_tmp = 0; - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); while (cpu_tmp >= priv->critical) { printf("CPU Temperature (%dC) too close to max (%dC)", cpu_tmp, priv->maxc); puts(" waiting...\n"); udelay(5000000); - if (is_soc_type(MXC_SOC_MX6)) - cpu_tmp = read_cpu_temperature_mx6(dev); + cpu_tmp = read_cpu_temperature(dev); } *temp = cpu_tmp; @@ -167,6 +236,13 @@ static int imx_thermal_probe(struct udevice *dev) fuse); return -EPERM; } + } else if (is_soc_type(MXC_SOC_MX7)) { + /* No Calibration data in FUSE? */ + if ((fuse & 0x3ffff) == 0) + return -EPERM; + /* We do not support 105C TE2 */ + if (((fuse & 0x1c0000) >> 18) == 0x6) + return -EPERM; } /* set critical cooling temp */ -- 2.1.4

3 2

[U-Boot] [PATCH 00/19] Janitorial: powerpc: remove PowerPC non-generic boards
by Masahiro Yamada 01 Sep '15

01 Sep '15

I sent the RFC version two weeks ago to announce the final call for PowerPC unmaintained boards. Some were converted to Generic Board, and some were not. This series really intends to delete non-generic PowerPC boards. I added entries to doc/README.scrapyard in this version. Masahiro Yamada (19): powerpc: ppc4xx: remove alpr support powerpc: ppc4xx: remove csb272, csb472 support powerpc: ppc4xx: remove lwmon5 support powerpc: ppc4xx: remove p3p440 support powerpc: ppc4xx: remove pcs440ep support powerpc: ppc4xx: remove sbc405 support powerpc: ppc4xx: remove zeus support powerpc: mpc5xx: remove cmi_mpc5xx support powerpc: mpc85xx: remove stxgp3, stxssa support powerpc: mpc85xx: remove MPC8540ADS support powerpc: mpc85xx: remove MPC8541CDS support powerpc: mpc85xx: remove MPC8544DS support powerpc: mpc85xx: remove MPC8548CDS support powerpc: mpc85xx: remove MPC8555CDS support powerpc: mpc85xx: remove MPC8560ADS support powerpc: mpc85xx: remove MPC8568MDS support powerpc: mpc85xx: remove MPC8569MDS support powerpc: mpc86xx: remove MPC8610HPCD support powerpc: mpc86xx: remove sbc8641d support arch/powerpc/cpu/mpc5xx/Kconfig | 4 - arch/powerpc/cpu/mpc85xx/Kconfig | 40 -- arch/powerpc/cpu/mpc85xx/cpu.c | 18 - arch/powerpc/cpu/mpc85xx/pci.c | 23 - arch/powerpc/cpu/mpc85xx/speed.c | 7 +- arch/powerpc/cpu/mpc86xx/Kconfig | 8 - arch/powerpc/cpu/ppc4xx/Kconfig | 33 -- arch/powerpc/cpu/ppc4xx/start.S | 15 - arch/powerpc/include/asm/config_mpc85xx.h | 13 - arch/powerpc/include/asm/fsl_lbc.h | 4 +- arch/powerpc/include/asm/global_data.h | 6 - arch/powerpc/include/asm/immap_85xx.h | 5 +- board/cmi/Kconfig | 9 - board/cmi/MAINTAINERS | 6 - board/cmi/Makefile | 8 - board/cmi/README | 84 --- board/cmi/cmi.c | 57 -- board/cmi/flash.c | 501 ----------------- board/csb272/Kconfig | 9 - board/csb272/MAINTAINERS | 6 - board/csb272/Makefile | 9 - board/csb272/csb272.c | 171 ------ board/csb272/init.S | 196 ------- board/csb472/Kconfig | 9 - board/csb472/MAINTAINERS | 6 - board/csb472/Makefile | 9 - board/csb472/csb472.c | 138 ----- board/csb472/init.S | 192 ------- board/freescale/mpc8540ads/Kconfig | 12 - board/freescale/mpc8540ads/MAINTAINERS | 6 - board/freescale/mpc8540ads/Makefile | 11 - board/freescale/mpc8540ads/ddr.c | 46 -- board/freescale/mpc8540ads/law.c | 42 -- board/freescale/mpc8540ads/mpc8540ads.c | 242 -------- board/freescale/mpc8540ads/tlb.c | 95 ---- board/freescale/mpc8541cds/Kconfig | 12 - board/freescale/mpc8541cds/MAINTAINERS | 7 - board/freescale/mpc8541cds/Makefile | 12 - board/freescale/mpc8541cds/ddr.c | 56 -- board/freescale/mpc8541cds/law.c | 42 -- board/freescale/mpc8541cds/mpc8541cds.c | 427 -------------- board/freescale/mpc8541cds/tlb.c | 96 ---- board/freescale/mpc8544ds/Kconfig | 12 - board/freescale/mpc8544ds/MAINTAINERS | 6 - board/freescale/mpc8544ds/Makefile | 12 - board/freescale/mpc8544ds/README | 122 ---- board/freescale/mpc8544ds/ddr.c | 59 -- board/freescale/mpc8544ds/law.c | 18 - board/freescale/mpc8544ds/mpc8544ds.c | 320 ----------- board/freescale/mpc8544ds/tlb.c | 75 --- board/freescale/mpc8548cds/Kconfig | 12 - board/freescale/mpc8548cds/MAINTAINERS | 8 - board/freescale/mpc8548cds/Makefile | 12 - board/freescale/mpc8548cds/ddr.c | 56 -- board/freescale/mpc8548cds/law.c | 19 - board/freescale/mpc8548cds/mpc8548cds.c | 358 ------------ board/freescale/mpc8548cds/tlb.c | 87 --- board/freescale/mpc8555cds/Kconfig | 12 - board/freescale/mpc8555cds/MAINTAINERS | 7 - board/freescale/mpc8555cds/Makefile | 12 - board/freescale/mpc8555cds/ddr.c | 56 -- board/freescale/mpc8555cds/law.c | 42 -- board/freescale/mpc8555cds/mpc8555cds.c | 428 -------------- board/freescale/mpc8555cds/tlb.c | 96 ---- board/freescale/mpc8560ads/Kconfig | 12 - board/freescale/mpc8560ads/MAINTAINERS | 6 - board/freescale/mpc8560ads/Makefile | 11 - board/freescale/mpc8560ads/ddr.c | 46 -- board/freescale/mpc8560ads/law.c | 42 -- board/freescale/mpc8560ads/mpc8560ads.c | 462 --------------- board/freescale/mpc8560ads/tlb.c | 95 ---- board/freescale/mpc8568mds/Kconfig | 12 - board/freescale/mpc8568mds/MAINTAINERS | 6 - board/freescale/mpc8568mds/Makefile | 13 - board/freescale/mpc8568mds/bcsr.c | 61 -- board/freescale/mpc8568mds/bcsr.h | 93 ---- board/freescale/mpc8568mds/ddr.c | 56 -- board/freescale/mpc8568mds/law.c | 41 -- board/freescale/mpc8568mds/mpc8568mds.c | 356 ------------ board/freescale/mpc8568mds/tlb.c | 84 --- board/freescale/mpc8569mds/Kconfig | 12 - board/freescale/mpc8569mds/MAINTAINERS | 7 - board/freescale/mpc8569mds/Makefile | 13 - board/freescale/mpc8569mds/README | 77 --- board/freescale/mpc8569mds/bcsr.c | 50 -- board/freescale/mpc8569mds/bcsr.h | 72 --- board/freescale/mpc8569mds/ddr.c | 66 --- board/freescale/mpc8569mds/law.c | 41 -- board/freescale/mpc8569mds/mpc8569mds.c | 585 ------------------- board/freescale/mpc8569mds/tlb.c | 95 ---- board/freescale/mpc8610hpcd/Kconfig | 12 - board/freescale/mpc8610hpcd/MAINTAINERS | 6 - board/freescale/mpc8610hpcd/Makefile | 9 - board/freescale/mpc8610hpcd/README | 73 --- board/freescale/mpc8610hpcd/ddr.c | 59 -- board/freescale/mpc8610hpcd/law.c | 22 - board/freescale/mpc8610hpcd/mpc8610hpcd.c | 329 ----------- board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 71 --- board/lwmon5/Kconfig | 9 - board/lwmon5/MAINTAINERS | 7 - board/lwmon5/Makefile | 9 - board/lwmon5/config.mk | 18 - board/lwmon5/init.S | 75 --- board/lwmon5/kbd.c | 490 ---------------- board/lwmon5/lwmon5.c | 558 ------------------- board/lwmon5/sdram.c | 247 -------- board/pcs440ep/Kconfig | 9 - board/pcs440ep/MAINTAINERS | 6 - board/pcs440ep/Makefile | 9 - board/pcs440ep/config.mk | 23 - board/pcs440ep/flash.c | 607 -------------------- board/pcs440ep/init.S | 56 -- board/pcs440ep/pcs440ep.c | 755 ------------------------- board/prodrive/alpr/Kconfig | 12 - board/prodrive/alpr/MAINTAINERS | 6 - board/prodrive/alpr/Makefile | 9 - board/prodrive/alpr/alpr.c | 215 ------- board/prodrive/alpr/config.mk | 16 - board/prodrive/alpr/fpga.c | 239 -------- board/prodrive/alpr/init.S | 53 -- board/prodrive/alpr/nand.c | 124 ----- board/prodrive/p3p440/Kconfig | 12 - board/prodrive/p3p440/MAINTAINERS | 6 - board/prodrive/p3p440/Makefile | 9 - board/prodrive/p3p440/config.mk | 16 - board/prodrive/p3p440/init.S | 38 -- board/prodrive/p3p440/p3p440.c | 177 ------ board/prodrive/p3p440/p3p440.h | 24 - board/sbc405/Kconfig | 9 - board/sbc405/MAINTAINERS | 6 - board/sbc405/Makefile | 8 - board/sbc405/sbc405.c | 91 --- board/sbc405/strataflash.c | 774 -------------------------- board/sbc8641d/Kconfig | 9 - board/sbc8641d/MAINTAINERS | 6 - board/sbc8641d/Makefile | 10 - board/sbc8641d/README | 28 - board/sbc8641d/ddr.c | 56 -- board/sbc8641d/law.c | 40 -- board/sbc8641d/sbc8641d.c | 261 --------- board/stx/stxgp3/Kconfig | 12 - board/stx/stxgp3/MAINTAINERS | 6 - board/stx/stxgp3/Makefile | 12 - board/stx/stxgp3/ddr.c | 46 -- board/stx/stxgp3/flash.c | 499 ----------------- board/stx/stxgp3/law.c | 42 -- board/stx/stxgp3/stxgp3.c | 331 ----------- board/stx/stxgp3/tlb.c | 114 ---- board/stx/stxssa/Kconfig | 12 - board/stx/stxssa/MAINTAINERS | 7 - board/stx/stxssa/Makefile | 11 - board/stx/stxssa/ddr.c | 47 -- board/stx/stxssa/law.c | 44 -- board/stx/stxssa/stxssa.c | 370 ------------ board/stx/stxssa/tlb.c | 90 --- board/zeus/Kconfig | 9 - board/zeus/MAINTAINERS | 6 - board/zeus/Makefile | 8 - board/zeus/README | 73 --- board/zeus/update.c | 89 --- board/zeus/zeus.c | 410 -------------- configs/MPC8540ADS_defconfig | 3 - configs/MPC8541CDS_defconfig | 3 - configs/MPC8541CDS_legacy_defconfig | 4 - configs/MPC8544DS_defconfig | 5 - configs/MPC8548CDS_36BIT_defconfig | 6 - configs/MPC8548CDS_defconfig | 5 - configs/MPC8548CDS_legacy_defconfig | 6 - configs/MPC8555CDS_defconfig | 3 - configs/MPC8555CDS_legacy_defconfig | 4 - configs/MPC8560ADS_defconfig | 3 - configs/MPC8568MDS_defconfig | 3 - configs/MPC8569MDS_ATM_defconfig | 6 - configs/MPC8569MDS_defconfig | 5 - configs/MPC8610HPCD_defconfig | 4 - configs/alpr_defconfig | 7 - configs/cmi_mpc5xx_defconfig | 6 - configs/csb272_defconfig | 4 - configs/csb472_defconfig | 4 - configs/lcd4_lwmon5_defconfig | 6 - configs/lwmon5_defconfig | 4 - configs/p3p440_defconfig | 4 - configs/pcs440ep_defconfig | 4 - configs/sbc405_defconfig | 4 - configs/sbc8641d_defconfig | 4 - configs/stxgp3_defconfig | 5 - configs/stxssa_4M_defconfig | 5 - configs/stxssa_defconfig | 5 - configs/zeus_defconfig | 4 - doc/README.scrapyard | 22 +- drivers/ddr/fsl/ctrl_regs.c | 4 - drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 3 - drivers/input/keyboard.c | 6 +- drivers/video/mb862xx.c | 3 +- include/configs/MPC8540ADS.h | 448 --------------- include/configs/MPC8541CDS.h | 465 ---------------- include/configs/MPC8544DS.h | 513 ----------------- include/configs/MPC8548CDS.h | 604 -------------------- include/configs/MPC8555CDS.h | 461 --------------- include/configs/MPC8560ADS.h | 488 ---------------- include/configs/MPC8568MDS.h | 490 ---------------- include/configs/MPC8569MDS.h | 582 ------------------- include/configs/MPC8610HPCD.h | 666 ---------------------- include/configs/alpr.h | 351 ------------ include/configs/cmi_mpc5xx.h | 240 -------- include/configs/csb272.h | 282 ---------- include/configs/csb472.h | 281 ---------- include/configs/lwmon5.h | 692 ----------------------- include/configs/p3p440.h | 302 ---------- include/configs/pcs440ep.h | 457 --------------- include/configs/sbc405.h | 252 --------- include/configs/sbc8641d.h | 590 -------------------- include/configs/stxgp3.h | 354 ------------ include/configs/stxssa.h | 440 --------------- include/configs/zeus.h | 350 ------------ include/status_led.h | 13 - 216 files changed, 29 insertions(+), 24342 deletions(-) delete mode 100644 board/cmi/Kconfig delete mode 100644 board/cmi/MAINTAINERS delete mode 100644 board/cmi/Makefile delete mode 100644 board/cmi/README delete mode 100644 board/cmi/cmi.c delete mode 100644 board/cmi/flash.c delete mode 100644 board/csb272/Kconfig delete mode 100644 board/csb272/MAINTAINERS delete mode 100644 board/csb272/Makefile delete mode 100644 board/csb272/csb272.c delete mode 100644 board/csb272/init.S delete mode 100644 board/csb472/Kconfig delete mode 100644 board/csb472/MAINTAINERS delete mode 100644 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mode 100644 configs/stxssa_defconfig delete mode 100644 configs/zeus_defconfig delete mode 100644 include/configs/MPC8540ADS.h delete mode 100644 include/configs/MPC8541CDS.h delete mode 100644 include/configs/MPC8544DS.h delete mode 100644 include/configs/MPC8548CDS.h delete mode 100644 include/configs/MPC8555CDS.h delete mode 100644 include/configs/MPC8560ADS.h delete mode 100644 include/configs/MPC8568MDS.h delete mode 100644 include/configs/MPC8569MDS.h delete mode 100644 include/configs/MPC8610HPCD.h delete mode 100644 include/configs/alpr.h delete mode 100644 include/configs/cmi_mpc5xx.h delete mode 100644 include/configs/csb272.h delete mode 100644 include/configs/csb472.h delete mode 100644 include/configs/lwmon5.h delete mode 100644 include/configs/p3p440.h delete mode 100644 include/configs/pcs440ep.h delete mode 100644 include/configs/sbc405.h delete mode 100644 include/configs/sbc8641d.h delete mode 100644 include/configs/stxgp3.h delete mode 100644 include/configs/stxssa.h delete mode 100644 include/configs/zeus.h -- 1.9.1

4 23

[U-Boot] [PATCH V2] imx: vf610 add get_cpu_rev
by Peng Fan 01 Sep '15

01 Sep '15

Since we need to support runtime check for different drivers, we need to add get_cpu_rev for vf610, otherwise there will be build errors. This patch introduces a dummy CPU id which is not read from chip silicon. Later when we can get the real id from chip, can fix the value of MXC_CPU_VF610 then. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Suggested-by: Stefano Babic <sbabic(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- Changes v2: Take suggestion from Stefano, get_cpu_rev for vf610 should return an ID saying dummy ID, but not 0. arch/arm/cpu/armv7/vf610/generic.c | 6 ++++++ arch/arm/include/asm/arch-imx/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 05c401d..08b9ef4 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -9,6 +9,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> +#include <asm/imx-common/sys_proto.h> #include <netdev.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> @@ -266,6 +267,11 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif +u32 get_cpu_rev(void) +{ + return MXC_CPU_VF610 << 12; +} + #if defined(CONFIG_DISPLAY_CPUINFO) static char *get_reset_cause(void) { diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index be13b96..1c8d24e 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -21,6 +21,7 @@ #define MXC_CPU_MX6D 0x67 #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 +#define MXC_CPU_VF610 0xF6 /* dummy ID */ #define CS0_128 0 #define CS0_64M_CS1_64M 1 -- 1.8.4

2 1

[U-Boot] [PATCH v5 0/5] Add support for Thumb-1 builds
by Albert ARIBAUD 01 Sep '15

01 Sep '15

This series implements essential changes for thumb-1 support and activates thumb-1 build for openrd and tricorder as a proof of concept as well as a fix to bring the image sizes of openrd and tricorder targets back under an acceptable limit. For other targets, some additional files might need to be forced to ARM building, notably architecture-specific instances of lowlevel_init.S or of cpu.c. This should be handled on a case-by-case basis. IMPORTANT NOTE: The whole set has been build-tested across all ARM targets and no build regression was detected. Patch 1 has been confirmed to be binary-invariant. Patch 2 has been build- and run-tested on ED Mini V2 (switched temporarily to Thumb build) and confirmed to be binary-invariant for non-thumb target Wireless Space. Patches 3, 4 and 5 have been build-tested BUT HAVE NOT BEEN RUN-TESTED. ********************************************************* Open-RD and Tricorder owners, PLEASE run-test this series and report on the mailing list whether the target works. ********************************************************* Changes in v5: - switched tricorder[_flash] to Thumb-1 build Changes in v4: - Made stm32f429-discovery explicitly state that it builds for Thumb Changes in v3: - added arch/arm/lib/mem{set,cpy}.S to the list of modules which should always be built in ARM state. - Selected HAS_THUMB2 for CPU_V7M. - Fixed invalidate_l2_cache() when building for Thumb-1. Changes in v2: - fixed a typo in the commit message - added file arch/arm/thumb1/include/asm/proc-armv/system.h, which overrides arch/arm/include/asm/proc-armv/system.h when building for Thumb-1 and provides non-functional but Thumb-compilable IRQ and FIQ related macros and functions. Albert ARIBAUD (5): stm32f429-discovery: add CONFIG_SYS_THUMB_BUILD arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD kirkwood: support CONFIG_SYS_THUMB_BUILD openrd: switch to CONFIG_SYS_THUMB_BUILD tricorder: switch to CONFIG_SYS_THUMB_BUILD Makefile | 2 + arch/arm/Kconfig | 5 ++ arch/arm/cpu/arm926ejs/Makefile | 11 ++++ arch/arm/cpu/arm926ejs/cache.c | 5 ++ arch/arm/include/asm/cache.h | 4 ++ arch/arm/lib/Makefile | 24 +++++++++ arch/arm/lib/cache.c | 11 ++++ arch/arm/lib/memcpy.S | 4 +- arch/arm/lib/memset.S | 2 +- arch/arm/mach-kirkwood/Makefile | 6 +++ arch/arm/mach-orion5x/Makefile | 10 ++++ arch/arm/thumb1/include/asm/proc-armv/system.h | 69 ++++++++++++++++++++++++++ examples/standalone/Makefile | 10 ++++ include/configs/openrd.h | 1 + include/configs/stm32f429-discovery.h | 1 + include/configs/tricorder.h | 1 + scripts/Makefile.lib | 3 +- 17 files changed, 165 insertions(+), 4 deletions(-) create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h -- 2.1.0

2 7

[U-Boot] marvell: problems reading ddr spd
by Stas Sergeev 01 Sep '15

01 Sep '15

Hello. It seems u-boot uses wrong i2c address to read SPD on armada-xp. Namely, http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/ddr/marvell/axp/ddr3_axp.… 39 #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E 40 #else 41 #define BUS_WIDTH_ECC_TWSI_ADDR 0x4F 42 #endif Both 0x4e and 0x4f addresses do not exist, so ECC was never detected. We changed to 0x56 - usual SPD address. Then is started to work with some memory chips and hang with others. It appears ddr3_check_config() reads wrong SPD bytes, applies wrong masks etc. Disabling AUTO_DETECTION_SUPPORT was also troublesome, because of this piece: http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/ddr/marvell/axp/ddr3_init… 438 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT) 439 ecc = DRAM_ECC; 440 #endif 441 442 #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT) 443 ecc = 0; 444 if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC)) 445 ecc = 1; 446 #endif Am I right that on line 438 the inversion operator (!) is missing? At the end we got it to work, but with too many changes, which makes me to suspect there is some misunderstanding on my side. Can someone please hint me how that code should work and what is the address 0x4e? Why it doesn't exist for us?

1 0

[U-Boot] [PATCH] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
by Chin Liang See 01 Sep '15

01 Sep '15

Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> --- drivers/spi/cadence_qspi.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..512bf2d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -128,6 +128,9 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) cadence_spi_write_speed(bus, hz); + /* to ensure spi_calibration is run when SCLK frequency change */ + plat->max_hz = hz; + /* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { -- 1.7.7.4

2 6

[U-Boot] regard to writeable ubi
by ChengFang Lu 01 Sep '15

01 Sep '15

Hi,friends, I am studing uboot,but I found a issue that ubi can not be wrote, Who do help me to implement the writable ubi fs? Thanks! cflu

1 0

[U-Boot] [PATCH V2] mxc: ocotp fix hole in shadow registers
by Peng Fan 01 Sep '15

01 Sep '15

There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes v2: Discard is_cpu_type(MXC_CPU_MX7D), since 7D cpu type is still not upstreamed. arch/arm/include/asm/arch-mx6/imx-regs.h | 3 +- drivers/misc/mxc_ocotp.c | 78 ++++++++++++++++++++++++++++++-- 2 files changed, 75 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4d84a9b..a685ed2 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -630,9 +630,10 @@ struct ocotp_regs { u32 version; u32 rsvd7[0xdb]; + /* fuse banks */ struct fuse_bank { u32 fuse_regs[0x20]; - } bank[16]; + } bank[0]; }; struct fuse_bank0_regs { diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index d9b02c7..65ff815 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -57,6 +57,68 @@ #define WRITE_POSTAMBLE_US 2 +#if defined(CONFIG_MX6) || defined(CONFIG_VF610) +#define FUSE_BANK_SIZE 0x80 +#ifdef CONFIG_MX6SL +#define FUSE_BANKS 8 +#else +#define FUSE_BANKS 16 +#endif +#elif defined CONFIG_MX7 +#define FUSE_BANK_SIZE 0x40 +#define FUSE_BANKS 16 +#else +#error "Unsupported architecture\n" +#endif + +#if defined(CONFIG_MX6) +#include <asm/arch/sys_proto.h> + +/* + * There is a hole in shadow registers address map of size 0x100 + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. + * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, + * we should account for this hole in address space. + * + * Similar hole exists between bank 14 and bank 15 of size + * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. + * Note: iMX6SL has only 0-7 banks and there is no hole. + * Note: iMX6UL doesn't have this one. + * + * This function is to covert user input to physical bank index. + * Only needed when read fuse, because we use register offset, so + * need to calculate real register offset. + * When write, no need to consider hole, always use the bank/word + * index from fuse map. + */ +u32 fuse_bank_physical(int index) +{ + u32 phy_index; + + if (is_cpu_type(MXC_CPU_MX6SL)) { + phy_index = index; + } else if (is_cpu_type(MXC_CPU_MX6UL)) { + if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } else { + if (index >= 15) + phy_index = fuse_bank_physical(14) + (index - 15) + 2; + else if (index >= 6) + phy_index = fuse_bank_physical(5) + (index - 6) + 3; + else + phy_index = index; + } + return phy_index; +} +#else +u32 fuse_bank_physical(int index) +{ + return index; +} +#endif + static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) { while (readl(&regs->ctrl) & BM_CTRL_BUSY) @@ -73,9 +135,9 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, { *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; - if (bank >= ARRAY_SIZE((*regs)->bank) || - word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || - !assert) { + if (bank >= FUSE_BANKS || + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || + !assert) { printf("mxc_ocotp %s(): Invalid argument\n", caller); return -EINVAL; } @@ -113,12 +175,15 @@ int fuse_read(u32 bank, u32 word, u32 *val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; ret = prepare_read(&regs, bank, word, val, __func__); if (ret) return ret; - *val = readl(&regs->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + + *val = readl(&regs->bank[phy_bank].fuse_regs[word << 2]); return finish_access(regs, __func__); } @@ -259,12 +324,15 @@ int fuse_override(u32 bank, u32 word, u32 val) { struct ocotp_regs *regs; int ret; + u32 phy_bank; ret = prepare_write(&regs, bank, word, __func__); if (ret) return ret; - writel(val, &regs->bank[bank].fuse_regs[word << 2]); + phy_bank = fuse_bank_physical(bank); + + writel(val, &regs->bank[phy_bank].fuse_regs[word << 2]); return finish_access(regs, __func__); } -- 1.8.4

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[U-Boot] [PATCH] imx: vf610 add function get_cpu_rev
by Peng Fan 01 Sep '15

01 Sep '15

Since we need to support runtime check for different drivers, we need to add get_cpu_rev for vf610. This patch only introduce a empty implementation to avoid build errors, later more stuff can be added if need to check vf610 cpu types. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/armv7/vf610/generic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 05c401d..bd948cb 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -266,6 +266,17 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif +/* + * Empty function + * Several drivers use runtime check, which needs get_cpu_rev. + * If later we need to do runtime check for vf610, we can add + * more stuff here. + */ +u32 get_cpu_rev(void) +{ + return 0; +} + #if defined(CONFIG_DISPLAY_CPUINFO) static char *get_reset_cause(void) { -- 1.8.4

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