September 2015 - U-Boot

[U-Boot] [PATCHv2] arm: socfpga: Add support for the Terasic DE-0 Atlas board
by dinguyen＠opensource.altera.com 02 Sep '15

02 Sep '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- v2: add ethernet support moved board files to board/terasic/de0-nano-soc/ associate everything with 'de0-nano-soc' or 'de0_nano_soc' based on u-boot-socfpga/wip/boards branch --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 61 +++ arch/arm/mach-socfpga/Kconfig | 7 + board/terasic/de0-nano-soc/MAINTAINERS | 5 + board/terasic/de0-nano-soc/Makefile | 9 + board/terasic/de0-nano-soc/qts/iocsr_config.h | 658 +++++++++++++++++++++++++ board/terasic/de0-nano-soc/qts/pinmux_config.h | 220 +++++++++ board/terasic/de0-nano-soc/qts/pll_config.h | 85 ++++ board/terasic/de0-nano-soc/qts/sdram_config.h | 342 +++++++++++++ board/terasic/de0-nano-soc/socfpga.c | 72 +++ configs/socfpga_de0_nano_soc_defconfig | 20 + include/configs/socfpga_de0_nano_soc.h | 87 ++++ 12 files changed, 1567 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts create mode 100644 board/terasic/de0-nano-soc/MAINTAINERS create mode 100644 board/terasic/de0-nano-soc/Makefile create mode 100644 board/terasic/de0-nano-soc/qts/iocsr_config.h create mode 100644 board/terasic/de0-nano-soc/qts/pinmux_config.h create mode 100644 board/terasic/de0-nano-soc/qts/pll_config.h create mode 100644 board/terasic/de0-nano-soc/qts/sdram_config.h create mode 100644 board/terasic/de0-nano-soc/socfpga.c create mode 100644 configs/socfpga_de0_nano_soc_defconfig create mode 100644 include/configs/socfpga_de0_nano_soc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c53f5fd..5b2e3d6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts new file mode 100644 index 0000000..b649c9a --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -0,0 +1,61 @@ +/* + * Copyright Altera Corporation (C) 2015 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE0-Nano(Atlas)"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 420f66a..12c8b72 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -18,6 +18,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_TERASIC_DE0_NANO + bool "Terasic DE0-Nano-Atlas (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -31,12 +35,14 @@ endchoice config SYS_BOARD default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT default "denx" if TARGET_SOCFPGA_DENX_MCVEVK @@ -46,6 +52,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK diff --git a/board/terasic/de0-nano-soc/MAINTAINERS b/board/terasic/de0-nano-soc/MAINTAINERS new file mode 100644 index 0000000..351c456 --- /dev/null +++ b/board/terasic/de0-nano-soc/MAINTAINERS @@ -0,0 +1,5 @@ +SOCFPGA ATLAS BOARD +M: Dinh Nguyen <dinguyen(a)opensource.altera.com> +S: Maintained +F: include/configs/socfpga_de0_nano_soc.h +F: configs/socfpga_de0_nano_soc_defconfig diff --git a/board/terasic/de0-nano-soc/Makefile b/board/terasic/de0-nano-soc/Makefile new file mode 100644 index 0000000..86f9b78 --- /dev/null +++ b/board/terasic/de0-nano-soc/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# (C) Copyright 2010, Thomas Chou <thomas(a)wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/terasic/de0-nano-soc/qts/iocsr_config.h b/board/terasic/de0-nano-soc/qts/iocsr_config.h new file mode 100644 index 0000000..9b4d709 --- /dev/null +++ b/board/terasic/de0-nano-soc/qts/iocsr_config.h @@ -0,0 +1,658 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x18060000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00010000, + 0x04000000, + 0x00000000, + 0x00000010, + 0x00004000, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x200300C0, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x00010000, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x4D034071, + 0x1A681A03, + 0x806180D0, + 0x34071C06, + 0x01A034D0, + 0x380D0000, + 0x0820680E, + 0x034D0340, + 0xD000001A, + 0x0680E380, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680618, + 0x4D034071, + 0x1A681A03, + 0x806180D0, + 0x34071C06, + 0x01A00040, + 0x180D0002, + 0x71C06806, + 0x034D0340, + 0xD01A681A, + 0x06806180, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xD32CA3D6, + 0xF551451E, + 0x034CD348, + 0x821A0000, + 0x0000D000, + 0x030C0680, + 0xD659647A, + 0x1ED32CA3, + 0x48F55145, + 0x00034CD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0x932CA3DE, + 0xF651451E, + 0x035CD348, + 0x821A0041, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED32CA3, + 0x48F55145, + 0x00035492, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x0C864000, + 0x59647A03, + 0xD32CA3DE, + 0xF551451E, + 0x035CB2C8, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED2AAA3, + 0xC8F55965, + 0x00035CB2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xD32CA3DE, + 0xF551451E, + 0x035CD348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDE59647A, + 0x1ED32CA3, + 0x48F55145, + 0x00035CD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/terasic/de0-nano-soc/qts/pinmux_config.h b/board/terasic/de0-nano-soc/qts/pinmux_config.h new file mode 100644 index 0000000..3854110 --- /dev/null +++ b/board/terasic/de0-nano-soc/qts/pinmux_config.h @@ -0,0 +1,220 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +/* pin MUX configuration data */ +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h new file mode 100644 index 0000000..6e5b998 --- /dev/null +++ b/board/terasic/de0-nano-soc/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PRELOADER_PLL_CONFIG_H_ +#define _PRELOADER_PLL_CONFIG_H_ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 3613281 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 12500000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 + +#endif /* _PRELOADER_PLL_CONFIG_H_ */ + diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h new file mode 100644 index 0000000..7084797 --- /dev/null +++ b/board/terasic/de0-nano-soc/qts/sdram_config.h @@ -0,0 +1,342 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __SDRAM_CONFIG_H +#define __SDRAM_CONFIG_H + +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 + +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090044, + 0x100a0010, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0024, + 0x10090008, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; +#endif /*#ifndef__SDRAM_CONFIG_H */ diff --git a/board/terasic/de0-nano-soc/socfpga.c b/board/terasic/de0-nano-soc/socfpga.c new file mode 100644 index 0000000..85700b0 --- /dev/null +++ b/board/terasic/de0-nano-soc/socfpga.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <micrel.h> +#include <netdev.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* + * PHY configuration + */ +#ifdef CONFIG_PHY_MICREL_KSZ9031 +int board_phy_config(struct phy_device *phydev) +{ + int ret; + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ret = ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x70); + if (ret) + return ret; + + ret = ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x7777); + if (ret) + return ret; + + ret = ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0); + if (ret) + return ret; + + ret = ksz9031_phy_extended_write(phydev, 0x2, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, + 0x03FC); + if (ret) + return ret; + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} +#endif diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig new file mode 100644 index 0000000..2b0d510 --- /dev/null +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_OF_CONTROL=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_SPL_DM=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SIMPLE_BUS=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h new file mode 100644 index 0000000..2508d03 --- /dev/null +++ b/include/configs/socfpga_de0_nano_soc.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_TERASIC_DE0_H__ +#define __CONFIG_TERASIC_DE0_H__ + +#include <asm/arch/socfpga_base_addrs.h> + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DFU +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_USB_MASS_STORAGE + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_BOOTCOMMAND "run ramboot" +#else +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" +#endif +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) + +/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 + +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS +#endif +#define CONFIG_G_DNL_MANUFACTURER "Terasic" + +/* Extra Environment */ +#define CONFIG_HOSTNAME socfpga_de0_nano_soc + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_TERASIC_DE0_H__ */ -- 2.4.5

5 8

[U-Boot] [PATCH 01/13] imx: arch-mx6: add is_soc_type helper macro
by Adrian Alonso 02 Sep '15

02 Sep '15

Add helper macro is_soc_type to identify iMX SoC family Signed-off-by: Adrian Alonso <aalonso(a)freescale.com> --- Changes for V2: Rework for common sys_proto header file arch/arm/include/asm/arch-imx/cpu.h | 2 ++ arch/arm/include/asm/imx-common/sys_proto.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index be13b96..708f13d 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -22,6 +22,8 @@ #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 +#define MXC_SOC_MX6 0x60 + #define CS0_128 0 #define CS0_64M_CS1_64M 1 #define CS0_64M_CS1_32M_CS2_32M 2 diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 6954ee9..c0a37e1 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -17,9 +17,12 @@ /* returns MXC_CPU_ value */ #define cpu_type(rev) (((rev) >> 12) & 0xff) +#define soc_type(rev) (((rev) >> 12) & 0xf0) /* both macros return/take MXC_CPU_ constants */ #define get_cpu_type() (cpu_type(get_cpu_rev())) +#define get_soc_type() (soc_type(get_cpu_rev())) #define is_cpu_type(cpu) (get_cpu_type() == cpu) +#define is_soc_type(soc) (get_soc_type() == soc) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) -- 2.1.4

2 13

[U-Boot] [PATCH v2] arm: socfpga: Fix memory error caused by re-enabling OCRAM ECC
by Jian Luo 02 Sep '15

02 Sep '15

Re-enabling OCRAM ECC can cause some value changes in SRAM. Just clear fake interrupt status and keep other bits intact. Signed-off-by: Jian Luo <jian.luo4(a)boschrexroth.de> --- Changes for v2: - add CC to custodian arch/arm/mach-socfpga/spl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..c858406 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -90,12 +90,14 @@ void board_init_f(ulong dummy) * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); - if (reg & SYSMGR_ECC_OCRAM_SERR) - writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); - if (reg & SYSMGR_ECC_OCRAM_DERR) - writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) { + reg &= ~SYSMGR_ECC_OCRAM_SERR; + writel(reg, &sysmgr_regs->eccgrp_ocram); + } + if (reg & SYSMGR_ECC_OCRAM_DERR) { + reg &= ~SYSMGR_ECC_OCRAM_DERR; + writel(reg, &sysmgr_regs->eccgrp_ocram); + } memset(__bss_start, 0, __bss_end - __bss_start); -- 1.9.1

2 1

[U-Boot] [PATCH] arm: socfpga: Fix memory error caused by re-enabling OCRAM ECC
by Jian Luo 02 Sep '15

02 Sep '15

Re-enabling OCRAM ECC can cause some value changes in SRAM. Just clear fake interrupt status and keep other bits intact. Signed-off-by: Jian Luo <jian.luo4(a)boschrexroth.de> --- arch/arm/mach-socfpga/spl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c index 775a827..c858406 100644 --- a/arch/arm/mach-socfpga/spl.c +++ b/arch/arm/mach-socfpga/spl.c @@ -90,12 +90,14 @@ void board_init_f(ulong dummy) * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); - if (reg & SYSMGR_ECC_OCRAM_SERR) - writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); - if (reg & SYSMGR_ECC_OCRAM_DERR) - writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, - &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) { + reg &= ~SYSMGR_ECC_OCRAM_SERR; + writel(reg, &sysmgr_regs->eccgrp_ocram); + } + if (reg & SYSMGR_ECC_OCRAM_DERR) { + reg &= ~SYSMGR_ECC_OCRAM_DERR; + writel(reg, &sysmgr_regs->eccgrp_ocram); + } memset(__bss_start, 0, __bss_end - __bss_start); -- 1.9.1

1 0

[U-Boot] [PATCH] powerpc/t1023rdb: change default core frequency to 1200MHz
by Shengzhou Liu 02 Sep '15

02 Sep '15

Per new requirement, change default core frequency from previous 1400MHz to 1200MHz to save power. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- board/freescale/t102xrdb/t1023_rcw.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg index 1d11a2e..f8f7282 100644 --- a/board/freescale/t102xrdb/t1023_rcw.cfg +++ b/board/freescale/t102xrdb/t1023_rcw.cfg @@ -1,8 +1,8 @@ #PBL preamble and RCW header for T1023RDB aa55aa55 010e0100 #SerDes Protocol: 0x77 -#Core/DDR: 1400Mhz/1600MT/s with single source clock -0810000e 00000000 00000000 00000000 +#Default Core=1200MHz, DDR=1600MT/s with single source clock +0810000c 00000000 00000000 00000000 3b800003 00000012 e8104000 21000000 00000000 00000000 00000000 00022800 00000130 04020200 00000000 00000006 -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] powerpc: convert selected boards to generic board structure
by York Sun 02 Sep '15

02 Sep '15

Convert MPC8540ADS, MPC8541CDS, MPC8544CDS, MPC8548CDS, MPC8555CDS, MPC8560ADS, MPC8568MDS, MPC8569MDS, MPC8610HPCD to use generic board structure. Signed-off-by: York Sun <yorksun(a)freescale.com> --- include/configs/MPC8540ADS.h | 3 +++ include/configs/MPC8541CDS.h | 3 +++ include/configs/MPC8544DS.h | 3 +++ include/configs/MPC8548CDS.h | 3 +++ include/configs/MPC8555CDS.h | 3 +++ include/configs/MPC8560ADS.h | 3 +++ include/configs/MPC8568MDS.h | 3 +++ include/configs/MPC8569MDS.h | 3 +++ include/configs/MPC8610HPCD.h | 3 +++ 9 files changed, 27 insertions(+) diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 931816b..a42c936 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -18,6 +18,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index d24d1ca..8942aae 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index ef268a8..62d6f3e 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a80221a..a2e9d5a 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 675ca87..2e8db5a 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 5a481d5..fabe6bf 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -18,6 +18,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 05e5a3d..7a2131b 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 78019b9..443e933 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index de56c48..9a487e0 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -13,6 +13,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ -- 1.7.9.5

1 1

[U-Boot] [v2] net/fman: Support both new and legacy FMan Compatibles
by Igal.Liberman 02 Sep '15

02 Sep '15

From: Igal Liberman <igal.liberman(a)freescale.com> Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Igal Liberman <igal.liberman(a)freescale.com> v1 --- v2: - Changed the subject of the patch v1: https://patchwork.ozlabs.org/patch/473501/ - Added Support to both new and legacy FMan compatibles --- arch/powerpc/cpu/mpc85xx/b4860_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/liodn.c | 64 +++++++++++++++++++++++++++++++--- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 4 +-- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 4 +-- arch/powerpc/cpu/mpc85xx/t1024_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t1040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t2080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 4 +-- arch/powerpc/include/asm/fsl_liodn.h | 53 ++++++++++++++++++++++------ drivers/net/fm/init.c | 27 ++++++++++---- 13 files changed, 135 insertions(+), 35 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index fd7f5fa..85eba0b 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -74,7 +74,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 7a2d4be..7a4465f 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -57,6 +57,23 @@ static void set_liodn(struct liodn_id_table *tbl, int size) } } +#ifdef CONFIG_SYS_DPAA_FMAN +static void set_fman_liodn(struct fman_liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + u32 liodn; + if (tbl[i].num_ids == 2) + liodn = (tbl[i].id[0] << 16) | tbl[i].id[1]; + else + liodn = tbl[i].id[0]; + + out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); + } +} +#endif + static void setup_sec_liodn_base(void) { ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; @@ -76,7 +93,7 @@ static void setup_sec_liodn_base(void) #ifdef CONFIG_SYS_DPAA_FMAN static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, - struct liodn_id_table *tbl, int size) + struct fman_liodn_id_table *tbl, int size) { int i; ccsr_fman_t *fm; @@ -180,12 +197,12 @@ void set_liodns(void) /* setup FMAN block(s) liodn bases & offsets if we have one */ #ifdef CONFIG_SYS_DPAA_FMAN - set_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); + set_fman_liodn(fman1_liodn_tbl, fman1_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); #if (CONFIG_SYS_NUM_FMAN == 2) - set_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); + set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif @@ -315,6 +332,43 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) } } +#ifdef CONFIG_SYS_DPAA_FMAN +static void fdt_fixup_liodn_tbl_fman(void *blob, + struct fman_liodn_id_table *tbl, + int sz) +{ + int i; + + for (i = 0; i < sz; i++) { + int off; + + if (tbl[i].compat == NULL) + continue; + + /* Try the new compatible first. + * If the node is missing, try the old. + */ + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat[0], tbl[i].compat_offset); + if (off < 0) + off = fdt_node_offset_by_compat_reg(blob, + tbl[i].compat[1], tbl[i].compat_offset); + + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for FMan Port: %s\n", + fdt_strerror(off)); + } else { + debug("WARNING: could not set fsl,liodn for FMan Portport: %s.\n", + fdt_strerror(off)); + } + } +} +#endif + void fdt_fixup_liodn(void *blob) { #ifdef CONFIG_SYS_SRIO @@ -323,9 +377,9 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN - fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); + fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); #if (CONFIG_SYS_NUM_FMAN == 2) - fdt_fixup_liodn_tbl(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); + fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz); diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 6e3cddd..8b6d274 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -61,7 +61,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 10), SET_FMAN_RX_1G_LIODN(1, 1, 11), SET_FMAN_RX_1G_LIODN(1, 2, 12), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 2b57703..ff8216b 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 10), SET_FMAN_RX_1G_LIODN(1, 1, 11), SET_FMAN_RX_1G_LIODN(1, 2, 12), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 94a5143..174eb04 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -54,7 +54,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 11), SET_FMAN_RX_1G_LIODN(1, 1, 12), SET_FMAN_RX_1G_LIODN(1, 2, 13), @@ -64,7 +64,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { +struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 16), SET_FMAN_RX_1G_LIODN(2, 1, 17), SET_FMAN_RX_1G_LIODN(2, 2, 18), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 0f292cf..99e3e91 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 10), SET_FMAN_RX_1G_LIODN(1, 1, 11), SET_FMAN_RX_1G_LIODN(1, 2, 12), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 98a568f..1c99f9f 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -48,7 +48,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 11), SET_FMAN_RX_1G_LIODN(1, 1, 12), SET_FMAN_RX_1G_LIODN(1, 2, 13), @@ -59,7 +59,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { +struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 17), SET_FMAN_RX_1G_LIODN(2, 1, 18), SET_FMAN_RX_1G_LIODN(2, 2, 19), diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index 8a1092e..8f95e33 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -50,7 +50,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 8091722..b98c7bc 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -55,7 +55,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index eda7f59..868f2d5 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -83,7 +83,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 470b080..14ada9e 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -112,7 +112,7 @@ struct liodn_id_table liodn_tbl[] = { int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); #ifdef CONFIG_SYS_DPAA_FMAN -struct liodn_id_table fman1_liodn_tbl[] = { +struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 0, 88), SET_FMAN_RX_1G_LIODN(1, 1, 89), SET_FMAN_RX_1G_LIODN(1, 2, 90), @@ -124,7 +124,7 @@ struct liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #if (CONFIG_SYS_NUM_FMAN == 2) -struct liodn_id_table fman2_liodn_tbl[] = { +struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 88), SET_FMAN_RX_1G_LIODN(2, 1, 89), SET_FMAN_RX_1G_LIODN(2, 2, 90), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 6206bee..8c91e72 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -44,6 +44,18 @@ struct liodn_id_table { unsigned long reg_offset; }; +struct fman_liodn_id_table { + /* Freescale FMan Device Tree binding was updated for FMan. + * We need to support both new and old compatibles in order not to + * break backward compatibility. + */ + const char *compat[2]; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid); extern void set_liodns(void); extern void fdt_fixup_liodn(void *blob); @@ -54,6 +66,14 @@ extern void fdt_fixup_liodn(void *blob); #define SET_LIODN_BASE_2(idA, idB) \ { .id = { idA, idB }, .num_ids = 2 } +#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\ + { .compat[0] = name1, \ + .compat[1] = name2, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ @@ -133,24 +153,37 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) +#ifdef CONFIG_SYS_FMAN_V3 /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-1g-rx", liodn, \ - FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ - FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) /* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ - SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \ - FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) +#else +/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ +#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) +/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ +#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ + SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \ + liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ + CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) +#endif /* * handle both old and new versioned SEC properties: * "fsl,secX.Y" became "fsl,sec-vX.Y" during development @@ -199,7 +232,7 @@ extern void fdt_fixup_liodn(void *blob); extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; -extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; +extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; #ifdef CONFIG_SYS_SRIO extern struct srio_liodn_id_table srio_liodn_tbl[]; extern int srio_liodn_tbl_sz; diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 9a8a007..b3ff4c5 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ +#include <errno.h> #include <common.h> #include <asm/io.h> #include <asm/fsl_serdes.h> @@ -230,7 +231,7 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) __attribute__((weak, alias("__def_board_ft_fman_fixup_port"))); -static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) +int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { int off; uint32_t ph; @@ -239,11 +240,13 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; off = fdt_node_offset_by_compat_reg(blob, prop, paddr); + if (off == -FDT_ERR_NOTFOUND) + return -EINVAL; if (info->enabled) { fdt_fixup_phy_connection(blob, off, info->enet_if); board_ft_fman_fixup_port(blob, prop, paddr, info->port, off); - return ; + return 0; } #ifdef CONFIG_SYS_FMAN_V3 @@ -281,7 +284,7 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4))) #endif ) - return; + return 0; #endif /* board code might have caused offset to change */ off = fdt_node_offset_by_compat_reg(blob, prop, paddr); @@ -294,6 +297,8 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ph = fdt_get_phandle(blob, off); do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), "status", "disabled", strlen("disabled") + 1, 1); + + return 0; } void fdt_fixup_fman_ethernet(void *blob) @@ -305,10 +310,18 @@ void fdt_fixup_fman_ethernet(void *blob) ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac"); #else for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - if (fm_info[i].type == FM_ETH_1G_E) - ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac"); - else - ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac"); + /* Try the new compatible first. + * If the node is missing, try the old. + */ + if (fm_info[i].type == FM_ETH_1G_E) { + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec")) + ft_fixup_port(blob, &fm_info[i], + "fsl,fman-1g-mac"); + } else { + if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec")) + ft_fixup_port(blob, &fm_info[i], + "fsl,fman-10g-mac"); + } } #endif } -- 1.7.9.5

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[U-Boot] [PATCH v1 0/2] Fix init_ram for e6500 and e5500
by York Sun 02 Sep '15

02 Sep '15

We have been using locked cache for init_ram for MPC85xx for quite a long time. It works until e6500 comes. On e6500, L1 cache is write-through. L2 cache has to be enabled to hold the data. We have not locked L2 cache and we used reserved space in ccsr to make the address valid. Now the reserved address is no longer reserved, causing overlapping with SerDes module. The first patch changes the physical address of init_ram for e6500 and e5500 to another reserved space to avoid overlapping. The second patch locks L2 cache instead of L1 cache for e6500. York Sun (2): powerpc: configs: Fix init_ram physical address for several boards powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram arch/powerpc/cpu/mpc85xx/start.S | 10 +++++++++- include/configs/B4860QDS.h | 4 ++-- include/configs/T102xQDS.h | 4 ++-- include/configs/T102xRDB.h | 4 ++-- include/configs/T1040QDS.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/t4qds.h | 2 +- 10 files changed, 21 insertions(+), 13 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH v2 0/2] Rename DDR4 target names
by York Sun 02 Sep '15

02 Sep '15

Freescale T1 series supports both DDR3 and DDR4. We have boards for each type of memory. To make the naming consistence and easy to understand, use _DDR4 instead of _D4 for the names. The same applies to Layerscape LS1 series, which already has _ddr4 in the name. LS2 series doesn't support DDR3, so the emulator target for DDR3 is dropped. This name change doesn't apply to RDB board because the DDR4 version is actually different board from DDR3 version. Changes in v2: Drop changes for RDB boards because DDR4 version is actually different board from DDR3 version. York Sun (2): armv8/ls2085a_emu: Drop DDR3 emulation target powerpc/defconfig: Rename defconfig file for T1040QDS/T1024QDS DDR4 targets board/freescale/ls2085a/MAINTAINERS | 1 - board/freescale/t102xqds/MAINTAINERS | 4 ++-- board/freescale/t1040qds/MAINTAINERS | 2 +- ...fconfig => T1024QDS_DDR4_SECURE_BOOT_defconfig} | 0 ...040QDS_D4_defconfig => T1040QDS_DDR4_defconfig} | 0 configs/ls2085a_emu_D4_defconfig | 14 -------------- configs/ls2085a_emu_defconfig | 2 +- 7 files changed, 4 insertions(+), 19 deletions(-) rename configs/{T1024QDS_D4_SECURE_BOOT_defconfig => T1024QDS_DDR4_SECURE_BOOT_defconfig} (100%) rename configs/{T1040QDS_D4_defconfig => T1040QDS_DDR4_defconfig} (100%) delete mode 100644 configs/ls2085a_emu_D4_defconfig -- 1.7.9.5

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[U-Boot] [PATCH] powerpc/t1024qds: Add missing T1024QDS_DDR4_defconfig
by York Sun 02 Sep '15

02 Sep '15

T1024QDS with DDR4 has been supported. Add the missing defconfig. Signed-off-by: York Sun <yorksun(a)freescale.com> CC: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- configs/T1024QDS_DDR4_defconfig | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 configs/T1024QDS_DDR4_defconfig diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig new file mode 100644 index 0000000..174fbca --- /dev/null +++ b/configs/T1024QDS_DDR4_defconfig @@ -0,0 +1,5 @@ +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_T102XQDS=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4" +CONFIG_SPI_FLASH=y -- 1.7.9.5

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