September 2015 - U-Boot

[U-Boot] [PATCH] net: eth: Do sanity test on eth dev before eth_get_ops(dev)->start
by Bin Meng 11 Sep '15

11 Sep '15

In eth_init(), eth_get_dev() can return NULL. We should do sanity test on eth dev before calling its start function. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- net/eth.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/eth.c b/net/eth.c index 26520d3..6ec3a86 100644 --- a/net/eth.c +++ b/net/eth.c @@ -370,6 +370,10 @@ int eth_init(void) eth_try_another(0); /* This will ensure the new "current" attempted to probe */ current = eth_get_dev(); + if (!current) { + printf("No ethernet found.\n"); + break; + } } while (old_current != current); return ret; -- 1.8.2.1

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[U-Boot] dm eth rotation is broken under some circumstances
by Bin Meng 11 Sep '15

11 Sep '15

Hi Joe, I found under some circumstances the eth rotation functionality is broken. Test scenario: 1). Say we have two ethernet devices, eth0 and eth1. Both devices are not probed yet (or probe failed due to ethaddr and eth1addr not set) Now we set the eth1addr to a valid MAC address, set ethact to NULL. Test a "ping 10.10.0.100", it fails. The supposed eth rotation should switch to eth1 for 'ping', right? But debugging shows that eth1's probe routine never gets called (see log below). => ping 10.10.0.100 Error: eth_designware#0 address not set. Error: eth_designware#0 address not set. Error: eth_designware#0 address not set. Error: eth_designware#0 address not set. No ethernet found. Error: eth_designware#0 address not set. ping failed; host 10.10.0.100 is not alive 2). The same test scenario above, but set ethact to eth1, we should get "ping 10.10.0.100" successfully pinged. Unfortunately, it still fails, reporting 'No ethernet found". => ping 10.10.0.100 Error: eth_designware#0 address not set. Error: eth_designware#0 address not set. Error: eth_designware#0 address not set. Error: eth_designware#1 address not set. Error: eth_designware#0 address not set. Error: eth_designware#0 address not set. No ethernet found. Error: eth_designware#0 address not set. ping failed; host 10.10.0.100 is not alive This time eth1's probe routine gets called, but it still failed (see log "Error: eth_designware#1 address not set.") This is because with eth0 probe failure before, when eth1 get probed, eth1's dev->seq will be set to 0 as it is the first ethernet device seen by dm eth, so its corresponding MAC address is ethaddr, NOT eth1addr. So its probe phase will still fail in eth_post_probe(), and rotation does not work as expected. I think this "dev->seq" match to "eth%daddr" is something we should think about with driver model conversion. So far the eth rotation seems worked pretty well if everything is good (i.e. probe OK), but on some exception path like above two it does not function as expected :( Regards, Bin

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[U-Boot] [PATCH v3 2/5] spi: cadence_qspi: Fix fdt read of spi-max-frequency
by Chin Liang See 10 Sep '15

10 Sep '15

Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> --- Changes for v3 - Use of fdt_getprop_u32_default_node instead casting Changes for v2 - Add unsigned casting for plat->max_hz --- drivers/spi/cadence_qspi.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 0e7450c..95236a3 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -12,6 +12,7 @@ #include <spi.h> #include <asm/errno.h> #include "cadence_qspi.h" +#include <fdt_support.h> #define CQSPI_STIG_READ 0 #define CQSPI_STIG_WRITE 1 @@ -295,10 +296,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->regbase = (void *)data[0]; plat->ahbbase = (void *)data[2]; - /* Use 500KHz as a suitable default */ - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - /* All other paramters are embedded in the child node */ subnode = fdt_first_subnode(blob, node); if (subnode < 0) { @@ -306,6 +303,10 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) return -ENODEV; } + /* Use 500 KHz as a suitable default */ + plat->max_hz = fdt_getprop_u32_default_node(blob, subnode, 0, + "spi-max-frequency", 500000); + /* Read other parameters from DT */ plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256); plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16); -- 1.7.7.4

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[U-Boot] [PATCH v3 1/5] spi: cadence_qspi: Ensure spi_calibration is run when sclk change
by Chin Liang See 10 Sep '15

10 Sep '15

Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Vikas Manocha <vikas.manocha(a)st.com> Cc: Jagannadh Teki <jteki(a)openedev.com> Cc: Pavel Machek <pavel(a)denx.de> Acked-by: Marek Vasut <marex(a)denx.de> Reviewed-by: Jagan Teki <jteki(a)openedev.com> --- Changes for v2 - remove frequency set before calibration - introducing previous_hz to store requested frequency - prevent calibration run when request same frequency --- drivers/spi/cadence_qspi.c | 20 ++++++++++++-------- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 34a0f46..0e7450c 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -37,15 +37,18 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) } /* Calibration sequence to determine the read data capture delay register */ -static int spi_calibration(struct udevice *bus) +static int spi_calibration(struct udevice *bus, uint hz) { - struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; unsigned int idcode = 0, temp = 0; int err = 0, i, range_lo = -1, range_hi = -1; + /* if calibrated frequency same as reqeusted, skip it */ + if (priv->qspi_calibrated_hz == hz) + return 0; + /* start with slowest clock (1 MHz) */ cadence_spi_write_speed(bus, 1000000); @@ -64,7 +67,7 @@ static int spi_calibration(struct udevice *bus) } /* use back the intended clock and find low range */ - cadence_spi_write_speed(bus, plat->max_hz); + cadence_spi_write_speed(bus, hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); @@ -111,7 +114,7 @@ static int spi_calibration(struct udevice *bus) (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ - priv->qspi_calibrated_hz = plat->max_hz; + priv->qspi_calibrated_hz = hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; @@ -126,14 +129,15 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); - cadence_spi_write_speed(bus, hz); - /* Calibration required for different SCLK speed or chip select */ - if (priv->qspi_calibrated_hz != plat->max_hz || + if (priv->previous_hz != hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { - err = spi_calibration(bus); + err = spi_calibration(bus, hz); if (err) return err; + + /* prevent calibration run when same as previous request */ + priv->previous_hz = hz; } /* Enable QSPI */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 98e57aa..2912e36 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -38,6 +38,7 @@ struct cadence_spi_priv { int qspi_is_init; unsigned int qspi_calibrated_hz; unsigned int qspi_calibrated_cs; + unsigned int previous_hz; }; /* Functions call declaration */ -- 1.7.7.4

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[U-Boot] [PATCH] mx6sabre_common: Add Fastboot support
by Fabio Estevam 10 Sep '15

10 Sep '15

From: Fabio Estevam <fabio.estevam(a)freescale.com> Tested basic fastboot commands, such as: On the mx6qsabresd U-boot prompt: => fastboot 0 On the host PC: $ fastboot getvar bootloader-version -i 0x0525 bootloader-version: U-Boot 2015.10-rc2-23960-g2462cce-dirty finished. total time: 0.000s $ fastboot reboot -i 0x0525 --> board reboots fine. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx6sabre_common.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6a57841..c5b4d30 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -238,6 +238,12 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 #endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ -- 1.9.1

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[U-Boot] [PATCH] sunxi: Ensure that 'mksunxiboot' tool produces deterministic output
by Siarhei Siamashka 10 Sep '15

10 Sep '15

Currently some uninitialized padding bytes are written to the output file, as can be confirmed with valgrind: $ valgrind tools/mksunxiboot spl/u-boot-spl.bin spl/sunxi-spl.bin ==5581== Syscall param write(buf) points to uninitialised byte(s) ==5581== at 0x4F0F940: __write_nocancel (in /lib64/libc-2.20.so) ==5581== by 0x400839: main (in /tmp/u-boot/tools/mksunxiboot) ==5581== Address 0xffeff5d3c is on thread 1's stack ==5581== in frame #1, created by main (???) This patch fixes the problem by clearing the whole structure instead of just a portion of it. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- tools/mksunxiboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c index 3361251..676d392 100644 --- a/tools/mksunxiboot.c +++ b/tools/mksunxiboot.c @@ -99,7 +99,7 @@ int main(int argc, char *argv[]) return EXIT_FAILURE; } - memset(img.pad, 0, BLOCK_SIZE); + memset(&img, 0, sizeof(img)); /* get input file size */ file_size = lseek(fd_in, 0, SEEK_END); -- 2.4.6

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[U-Boot] [PATCH] sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devices
by Stefan Roese 10 Sep '15

10 Sep '15

This patch adds support for NAND chips with 4KiB page size and 24/1024 ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the ICnova-A20 SoM. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Hans de Goede <hdegoede(a)redhat.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> --- drivers/mtd/nand/sunxi_nand_spl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index bf9b1b1..5985534 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -321,6 +321,7 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest, { 8192, 40, 1024, 5 }, { 16384, 56, 1024, 5 }, { 8192, 24, 1024, 5 }, + { 4096, 24, 1024, 5 }, }; static int nand_config = -1; int i; -- 2.5.1

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[U-Boot] [PATCH] sunxi: Fix wrong serial console setup in Forfun Q88DB tablet
by Siarhei Siamashka 10 Sep '15

10 Sep '15

The Forfun Q88DB tablet was unbootable since commit b6006baf9c2553543e3384983d23d95efbf24fa6 ("sunxi: Move all boards to the driver-model"). Appears that this is caused by the wrong serial console setup in the SPL. The serial console should use PG3/PG4 pins according to the FEX file. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- configs/forfun_q88db_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) While this should be a correct fix, the reason why the tablet failed to boot is a bit unclear. Without the correct CONS_INDEX setup, we should just get the serial console routed to the nonexisting pins B19/B20, and this is expected to be harmless. Maybe the DM code in the main U-Boot binary can't initialize serial console properly if we have a mismatch between the settings in the dts file and the CONS_INDEX settings in the SPL? diff --git a/configs/forfun_q88db_defconfig b/configs/forfun_q88db_defconfig index 30cead7..30e0937 100644 --- a/configs/forfun_q88db_defconfig +++ b/configs/forfun_q88db_defconfig @@ -13,7 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set -- 2.4.6

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[U-Boot] Fastboot is not detected
by Fabio Estevam 10 Sep '15

10 Sep '15

Hi, I am trying to add fastboot support for mx6qsabresd and I did the following changes on against top of head U-boot: --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -238,6 +238,12 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 #define CONFIG_G_DNL_MANUFACTURER "FSL" + +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 #endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ On the U-boot prompt I run: => fastboot 0 and then in the host PC I try to read the bootloader version: $ fastboot getvar bootloader-version < waiting for device > (and it gets stuck here) After a CTRL+C I have also tried: $ sudo fastboot devices $ ,but nothing is reported. I am able to mount the SD card via 'ums 0 mmc 1' command, so the USB OTG connection is fine. Does anyone have any suggestions? Thanks, Fabio Estevam

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[U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC
by Thierry Reding 10 Sep '15

10 Sep '15

From: Thierry Reding <treding(a)nvidia.com> Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet <kwizart(a)gmail.com> Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- arch/arm/include/asm/arch-tegra124/clock.h | 3 +++ arch/arm/mach-tegra/tegra124/clock.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h index e202cc5a7f46..ff99b9dfafda 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -16,6 +16,9 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_PLLC_MISC_0 */ +#define PLLC_IDDQ (1 << 26) + /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ #define SOR0_CLK_SEL0 (1 << 14) #define SOR0_CLK_SEL1 (1 << 15) diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index aa046e8950f7..1e71146236e9 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -809,6 +809,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz -- 2.5.0

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