December 2022 - U-Boot

[PATCH 1/4] configs: defconfig: Enable UBI and UBIFS for Agilex and Stratix10
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Sin Hui Kho <sin.hui.kho(a)intel.com> Enabling configs required for UBI and UBIFS commands. Set environment in a UBI volume. So, remove CONFIG_ENV_IS_IN_NAND as the environment is now in UBI volume. Signed-off-by: Sin Hui Kho <sin.hui.kho(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_nand_atf_defconfig | 11 +++++++++-- configs/socfpga_agilex_nand_defconfig | 11 +++++++++-- configs/socfpga_stratix10_nand_atf_defconfig | 11 +++++++++-- configs/socfpga_stratix10_nand_defconfig | 11 +++++++++-- 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index bfc893fd39..16509d868b 100644 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -90,4 +89,12 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig index 3f95aac147..7ba5016c2e 100644 --- a/configs/socfpga_agilex_nand_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -46,7 +46,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -83,4 +82,12 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig index a9abd85e68..4a4b426b99 100644 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -53,7 +53,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -91,4 +90,12 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig index 48c20e5b11..a148eac83f 100644 --- a/configs/socfpga_stratix10_nand_defconfig +++ b/configs/socfpga_stratix10_nand_defconfig @@ -46,7 +46,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" -CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -84,4 +83,12 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_UBI=y +CONFIG_CMD_UBIFS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" \ No newline at end of file -- 2.26.2

1 3

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf64
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf64 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 758aca20fd..86e97dcb4e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -170,6 +170,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] arm: socfpga: Export Board ID as U-boot Environment Variable
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Yau Wai Gan <yau.wai.gan(a)intel.com> Board ID is exported as environment variable for use to boot Linux FIT configuration. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/misc_soc64.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 49b241b7b8..d092268fea 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; +u8 socfpga_get_board_id(void); + /* * FPGA programming support for SoC FPGA Stratix 10 */ @@ -57,10 +59,15 @@ int print_cpuinfo(void) int arch_misc_init(void) { char qspi_string[13]; + char id[3]; sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); + /* Export board_id as environment variable */ + sprintf(id, "%u", socfpga_get_board_id()); + env_set("board_id", id); + return 0; } #endif -- 2.26.2

1 0

[PATCH] arm: socfpga: Enable U-boot FIT Config Name Match with Board ID
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Yau Wai Gan <yau.wai.gan(a)intel.com> U-boot FIT configuration shall be selected based on the Board ID that is set. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/board.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 11abf864f5..a9086d9fbe 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -131,13 +131,16 @@ u8 socfpga_get_board_id(void) } -#ifdef CONFIG_SPL_BUILD -__weak int board_fit_config_name_match(const char *name) +#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +int board_fit_config_name_match(const char *name) { - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + char board_name[10]; - return 0; + sprintf(board_name, "board_%u", socfpga_get_board_id()); + + debug("Board name: %s\n", board_name); + + return strcmp(name, board_name); } #endif -- 2.26.2

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf32
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf32 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index dbf8b8e298..758aca20fd 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -168,6 +168,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] arm: socfpga: Add function to get Board ID
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Yau Wai Gan <yau.wai.gan(a)intel.com> Board ID is defined in JTAG User Code register. This function retrieves the Board ID and perform validation on it. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/board.c | 39 +++++++++++++++++++ .../mach-socfpga/include/mach/mailbox_s10.h | 1 + 2 files changed, 40 insertions(+) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 914a44970d..11abf864f5 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -7,9 +7,11 @@ #include <common.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> #include <asm/global_data.h> #include <asm/io.h> #include <errno.h> @@ -23,6 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; +#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF + void s_init(void) { #ifndef CONFIG_ARM64 /* @@ -92,6 +96,41 @@ int g_dnl_board_usb_cable_connected(void) } #endif +u8 socfpga_get_board_id(void) +{ + u8 board_id = 0; + u32 jtag_usercode; + int err; + +#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF) + err = smc_get_usercode(&jtag_usercode); +#else + u32 resp_len = 1; + + err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT, 0, + NULL, 0, &resp_len, &jtag_usercode); +#endif + + if (err) { + puts("Fail to read JTAG Usercode. Default Board ID to 0\n"); + return board_id; + } + + debug("Valid JTAG Usercode: %u\n", jtag_usercode); + + if (jtag_usercode == DEFAULT_JTAG_USERCODE) { + debug("JTAG Usercode is not set. Default Board ID to 0\n"); + } else if (jtag_usercode >= 0 && jtag_usercode <= 255) { + board_id = jtag_usercode; + debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id); + } else { + puts("Board ID is not in range 0 to 255\n"); + } + + return board_id; +} + + #ifdef CONFIG_SPL_BUILD __weak int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597e..2cc7c89044 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -119,6 +119,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_RECONFIG_DATA 8 #define MBOX_RECONFIG_STATUS 9 #define MBOX_VAB_SRC_CERT 11 +#define MBOX_GET_USERCODE 19 #define MBOX_QSPI_OPEN 50 #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 -- 2.26.2

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf16
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf16 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 158b0057a5..dbf8b8e298 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -166,6 +166,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf80
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf80 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 5d8a08bfe2..158b0057a5 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -164,6 +164,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lb02g
by Victor Lim 11 Dec '22

11 Dec '22

adding gd55lb02g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b9381042ac..5d8a08bfe2 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -162,6 +162,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lb01g
by Victor Lim 11 Dec '22

11 Dec '22

adding gd55lb01g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 213a404604..b9381042ac 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -160,6 +160,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0