December 2022 - U-Boot

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lx512
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lx512 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 8bead629f4..370d1f7698 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -190,6 +190,8 @@ const struct flash_info spi_nor_ids[] = { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.25.1

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lt02g
by Victor Lim 11 Dec '22

11 Dec '22

adding gd55lt02g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index a90b1a2e3c..8bead629f4 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -184,6 +184,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55lt01g
by Victor Lim 11 Dec '22

11 Dec '22

adding gd55lt01g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 0419dca074..a90b1a2e3c 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -182,6 +182,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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[PATCH] spl: fit: nand: fix fit loading on bad blocks
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> The offset at which the image to be loaded from NAND is located is retrieved from the itb header. The presence of bad blocks in the area of the NAND where the itb image is located could invalidate the offset which must therefore be adjusted taking into account the state of the sectors concerned. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- common/spl/spl_nand.c | 3 +- drivers/mtd/nand/raw/denali.c | 91 ++++++++++++++++++++++++++++++++++- 2 files changed, 92 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 7b7579a2df..d94148ec71 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -45,10 +45,11 @@ static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs, int err; ulong sector; - sector = *(int *)load->priv; offs *= load->bl_len; size *= load->bl_len; + sector = *(int *)load->priv; offs = sector + nand_spl_adjust_offset(sector, offs - sector); + err = nand_spl_load_image(offs, size, dst); if (err) return 0; diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index c827f80281..290c12ac96 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2014 Panasonic Corporation * Copyright (C) 2013-2014, Altera Corporation <www.altera.com> - * Copyright (C) 2009-2010, Intel Corporation and its suppliers. + * Copyright (C) 2009-2022, Intel Corporation and its suppliers. */ #include <common.h> @@ -1374,3 +1374,92 @@ free_buf: return ret; } + +#ifdef CONFIG_SPL_BUILD +struct mtd_info *nand_get_mtd(void) +{ + struct mtd_info *mtd; + + mtd = get_nand_dev_by_index(nand_curr_device); + if (!mtd) + hang(); + + return mtd; +} + +int nand_spl_load_image(u32 offset, u32 len, void *dst) +{ + size_t count = len, actual = 0, page_align_overhead = 0; + u32 page_align_offset = 0; + u8 *page_buffer; + int err = 0; + struct mtd_info *mtd; + if (!len || !dst) + return -EINVAL; + + mtd = get_nand_dev_by_index(nand_curr_device); + if (!mtd) + hang(); + mtd = nand_get_mtd(); + + if ((offset & (mtd->writesize - 1)) != 0) { + page_buffer = malloc_cache_aligned(mtd->writesize); + if (!page_buffer) { + debug("Error: allocating buffer\n"); + return -ENOMEM; + } + page_align_overhead = offset % mtd->writesize; + page_align_offset = (offset / mtd->writesize) * mtd->writesize; + count = mtd->writesize; + err = nand_read_skip_bad(mtd, page_align_offset, &count, + &actual, mtd->size, page_buffer); + if (err) + return err; + count -= page_align_overhead; + count = min((size_t)len, count); + memcpy(dst, page_buffer + page_align_overhead, count); + free(page_buffer); + len -= count; + if (!len) + return err; + offset += count; + dst += count; + count = len; + } + return nand_read_skip_bad(mtd, offset, &count, &actual, mtd->size, dst); +} + +/* + * This function is to adjust the load offset to skip bad blocks. + * The Denali NAND load image does skip bad blocks during read, + * hence this function is returning the offset as it is. + * The offset at which the image to be loaded from NAND is located is + * retrieved from the itb header. The presence of bad blocks in the area + * of the NAND where the itb image is located could invalidate the offset + * which must therefore be adjusted taking into account the state of the + * sectors concerned + */ +u32 nand_spl_adjust_offset(u32 sector, u32 offs) +{ + u32 sector_align_offset, sector_align_end_offset; + struct mtd_info *mtd; + + mtd = nand_get_mtd(); + + sector_align_offset = sector & (~(mtd->erasesize - 1)); + + sector_align_end_offset = (sector + offs) & (~(mtd->erasesize - 1)); + + while (sector_align_offset <= sector_align_end_offset) { + if (nand_block_isbad(mtd, sector_align_offset)) { + offs += mtd->erasesize; + sector_align_end_offset += mtd->erasesize; + } + sector_align_offset += mtd->erasesize; + } + + return offs; +} + +void nand_deselect(void) {} +#endif -- 2.26.2

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lt512
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lt512 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7dd1b63faa..0419dca074 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -180,6 +180,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lt256
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lt256 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 6634e9ceb1..7dd1b63faa 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -178,6 +178,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf511
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf511 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4aeaccd6d1..6634e9ceb1 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -176,6 +176,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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[PATCH] include: configs: socfpga: Add environment variables for distro boot
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Yau Wai Gan <yau.wai.gan(a)intel.com> Added environment variables needed to support distro boot. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- include/configs/socfpga_soc64_common.h | 81 +++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 5b1d243153..f7f3bc1f13 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -54,6 +54,84 @@ #define CONFIG_BOOTFILE "Image" #endif +#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS) +#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if IS_ENABLED(CONFIG_CMD_SF) +#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) +#else +#define BOOT_TARGET_DEVICES_QSPI(func) +#endif + +#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ + "bootcmd_qspi=sf probe && " \ + "sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize} && " \ + "echo QSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo QSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ + "qspi " + +#if IS_ENABLED(CONFIG_CMD_NAND) +# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) +#else +# define BOOT_TARGET_DEVICES_NAND(func) +#endif + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_nand=ubi part root && " \ + "ubi readvol ${scriptaddr} script && " \ + "echo NAND: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo NAND: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + "nand " + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_QSPI(func) \ + BOOT_TARGET_DEVICES_NAND(func) + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0x2000000\0" \ + "fdt_addr_r=0x6000000\0" \ + "qspiscriptaddr=0x02110000\0" \ + "scriptsize=0x00010000\0" \ + "qspibootimageaddr=0x02120000\0" \ + "bootimagesize=0x03200000\0" \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=" CONFIG_BOOTFILE "\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then" \ + " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; fi; fi\0" \ + "scriptaddr=0x05FF0000\0" \ + "scriptfile=boot.scr\0" \ + "nandroot=ubi0:rootfs\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "rsu_status=rsu dtb; rsu display_dcmf_version; "\ + "rsu display_dcmf_status; rsu display_max_retry\0" \ + "smc_fid_rd=0xC2000007\0" \ + "smc_fid_wr=0xC2000008\0" \ + "smc_fid_upd=0xC2000009\0 " \ + BOOTENV + +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ "qspibootimageaddr=0x020E0000\0" \ "qspifdtaddr=0x020D0000\0" \ @@ -106,7 +184,8 @@ "rsu display_dcmf_status; rsu display_max_retry\0" \ "smc_fid_rd=0xC2000007\0" \ "smc_fid_wr=0xC2000008\0" \ - "smc_fid_upd=0xC2000009\0 " \ + "smc_fid_upd=0xC2000009\0 " +#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/ /* * External memory configurations -- 2.26.2

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf255
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf255 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index d3dba87c22..4aeaccd6d1 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -174,6 +174,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lf128
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lf128 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 86e97dcb4e..d3dba87c22 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -172,6 +172,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

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