December 2022 - U-Boot

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lb512
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lb512 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 00c46f75be..213a404604 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -158,6 +158,8 @@ const struct flash_info spi_nor_ids[] = { }, {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25lb256
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25lb256 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 133550dd3b..00c46f75be 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -156,6 +156,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) -- 2.25.1

1 0

[PATCH] arm: socfpga: soc64: Add support for board_boot_order()
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Sin Hui Kho <sin.hui.kho(a)intel.com> Add board_boot_order() to retrieve the list of boot devices from spl-boot-order property in device tree. This board_boot_order() will use for all Intel SOC64 device for single SPL binary. Signed-off-by: Sin Hui Kho <sin.hui.kho(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/spl_soc64.c | 93 +++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index ba6efc1d86..2b2377da69 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -23,3 +23,96 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } #endif + +/* This function is to map specified node onto SPL boot devices */ +static int spl_node_to_boot_device(int node) +{ + struct udevice *parent; + + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) + return BOOT_DEVICE_MMC1; + else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent)) + return BOOT_DEVICE_NAND; + else + return -1; +} + +static void default_spl_boot_list(u32 *spl_boot_list, int length) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + + if (length > 1) + spl_boot_list[1] = BOOT_DEVICE_SPI; + + if (length > 2) + spl_boot_list[2] = BOOT_DEVICE_NAND; +} + +void board_boot_order(u32 *spl_boot_list) +{ + int idx = 0; + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + const char *conf; + int elem; + int boot_device; + int node; + int length; + + /* expect valid initialized spl_boot_list */ + if (!spl_boot_list) + return; + + length = 1; + while (spl_boot_list[length] == spl_boot_list[length - 1]) + length++; + + debug("%s: chosen_node is %d\n", __func__, chosen_node); + if (chosen_node < 0) { + printf("%s: /chosen not found, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + if (idx >= length) { + printf("%s: limit %d to spl_boot_list exceeded\n", __func__, + length); + break; + } + + /* Resolve conf item as a path in device tree */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT\n", __func__, conf); + continue; + } + + /* Try to map spl node back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx] = boot_device; + debug("%s: spl_boot_list[%d] = %u\n", __func__, idx, + spl_boot_list[idx]); + idx++; + } + + if (idx == 0) { + if (!conf && !elem) { + printf("%s: spl-boot-order invalid, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + } else { + printf("%s: no valid element spl-boot-order list\n", __func__); + } + } +} \ No newline at end of file -- 2.26.2

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55x02g
by Victor Lim 11 Dec '22

11 Dec '22

adding gd55x02g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index f6ca16ac62..133550dd3b 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -144,6 +144,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | -- 2.25.1

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55x01g
by Victor Lim 11 Dec '22

11 Dec '22

adding gd55x01g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 741b40fbde..f6ca16ac62 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -142,6 +142,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | -- 2.25.1

1 0

[PATCH 1/6] doc: dtbinding: Add doc for privilege regs settings
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Add a document to describe firewall and privilege register settings binding information. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- .../misc/socfpga_secreg.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 doc/device-tree-bindings/misc/socfpga_secreg.txt diff --git a/doc/device-tree-bindings/misc/socfpga_secreg.txt b/doc/device-tree-bindings/misc/socfpga_secreg.txt new file mode 100644 index 0000000000..66df51f613 --- /dev/null +++ b/doc/device-tree-bindings/misc/socfpga_secreg.txt @@ -0,0 +1,26 @@ +* Firewall and privilege register settings in device tree + +Required properties: +-------------------- + +- compatible: should contain "intel,socfpga-secreg" +- intel,offset-settings: 32-bit offset address of block register, and then + followed by 32-bit value settings. + +Example: +-------- + + socfpga_secreg: socfpga-secreg { + compatible = "intel,socfpga-secreg"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + i_sys_mgr@ffd12000 { + reg = <0xffd12000 0x00000228>; + intel,offset-settings = + <0x00000020 0xff010000>, + <0x00000024 0xffffffff>; + u-boot,dm-pre-reloc; + }; + }; -- 2.26.2

1 5

[PATCH] ddr: altera: n5x: Include DDR4 for the same hardcoding settings
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Below settings are required for DDR4 to get some DDR chips properly retention entry and exit. Register INIT0 = 0xF87F_80D0 = bits [31-30] = [11] Register PWRCTL = 0xF87F_8030 = bit [5] = 1 Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 79 +++++----------------------------- 1 file changed, 10 insertions(+), 69 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index b4d52f7ac2..d2049520c8 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -341,7 +341,10 @@ enum region_size { enum reset_type { POR_RESET, WARM_RESET, - COLD_RESET + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG }; enum ddr_type { @@ -394,16 +397,6 @@ enum message_mode { STREAMING_MESSAGE }; -/* Reset type */ -enum reset_type { - POR_RESET, - WARM_RESET, - COLD_RESET, - NCONFIG, - JTAG_CONFIG, - RSU_RECONFIG -}; - enum data_type { HEADER_ONLY, HEADER_DATA @@ -1013,14 +1006,13 @@ static int init_umctl2(phys_addr_t umctl2_handoff_base, /* Setting selfref_sw to 1, based on lpddr4 requirement */ setbits_le32(umctl2_base + DDR4_PWRCTL_OFFSET, DDR4_PWRCTL_SELFREF_SW); - /* Backup user settings, restore after DDR up running */ user_backup++; *user_backup = readl(umctl2_base + DDR4_INIT0_OFFSET) & DDR4_INIT0_SKIP_RAM_INIT; /* - * Setting INIT0.skip_dram_init to 0x3, based on lpddr4 + * Setting INIT0.skip_dram_init to 0x3, based on ddr4 / lpddr4 * requirement */ setbits_le32(umctl2_base + DDR4_INIT0_OFFSET, @@ -1614,8 +1606,6 @@ static bool is_cal_bak_data_valid(void) static int init_phy(struct ddr_handoff *ddr_handoff_info, bool *need_calibrate, bool is_ddr_hang_be4_rst) { - u32 handoff_table[ddr_handoff_info->phy_handoff_length]; - u32 i, value; u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); int ret; @@ -2815,24 +2805,6 @@ static int ddr_post_config(struct ddr_handoff *handoff, bool *need_calibrate) return ret; } -static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg) -{ - return boot_scratch_cold0_reg & - ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK; -} - -static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg) -{ - return boot_scratch_cold0_reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK; -} - -static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg) -{ - return (boot_scratch_cold0_reg & - ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >> - ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT; -} - void reset_type_debug_print(u32 boot_scratch_cold0_reg) { switch (get_reset_type(boot_scratch_cold0_reg)) { @@ -2850,37 +2822,6 @@ void reset_type_debug_print(u32 boot_scratch_cold0_reg) } } -bool is_ddr_init(void) -{ - u32 reg = readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_BOOT_SCRATCH_COLD0); - - reset_type_debug_print(reg); - - if (get_reset_type(reg) == POR_RESET) { - debug("%s: DDR init is required\n", __func__); - return true; - } - - if (get_reset_type(reg) == WARM_RESET) { - debug("%s: DDR init is skipped\n", __func__); - return false; - } - - if (get_reset_type(reg) == COLD_RESET) { - if (is_ddr_retention_enabled(reg) && - is_ddr_bitstream_sha_matching(reg)) { - debug("%s: DDR retention bit is set\n", __func__); - debug("%s: Matching in DDR bistream\n", __func__); - debug("%s: DDR init is skipped\n", __func__); - return false; - } - } - - debug("%s: DDR init is required\n", __func__); - return true; -} - int sdram_mmr_init_full(struct udevice *dev) { u32 user_backup[2], user_backup_2nd[2]; @@ -2898,11 +2839,11 @@ int sdram_mmr_init_full(struct udevice *dev) printf("Checking SDRAM configuration in progress ...\n"); ret = populate_ddr_handoff(&ddr_handoff_info); - if (ret) { - debug("%s: Failed to populate DDR handoff\n", - __func__); - return ret; - } + if (ret) { + debug("%s: Failed to populate DDR handoff\n", + __func__); + return ret; + } /* Set the MPFE NoC mux to correct DDR controller type */ use_ddr4(ddr_handoff_info.cntlr_t); -- 2.26.2

1 0

[PATCH] configs: socfpga: soc64: Disable CONFIG_SPL_RAW_IMAGE_SUPPORT
by Jit Loon Lim 11 Dec '22

11 Dec '22

From: Sin Hui Kho <sin.hui.kho(a)intel.com> Enable the SPL to support loading u-boot image with header or in FIT format only. SPL shall proceed to the next boot device in the boot order list when proper u-boot image is unavailable in current device. This requires disabling the raw image support in SPL. This change is common for all Intel SOC64 devices. Signed-off-by: Sin Hui Kho <sin.hui.kho(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_nand_atf_defconfig | 3 ++- configs/socfpga_agilex_nand_defconfig | 3 ++- configs/socfpga_agilex_qspi_atf_defconfig | 3 ++- configs/socfpga_agilex_qspi_defconfig | 3 ++- configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 2 +- configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_stratix10_nand_atf_defconfig | 3 ++- configs/socfpga_stratix10_nand_defconfig | 3 ++- configs/socfpga_stratix10_qspi_atf_defconfig | 3 ++- ...defconfig => socfpga_stratix10_qspi_defconfig} | 15 ++++++++------- 16 files changed, 30 insertions(+), 15 deletions(-) mode change 100755 => 100644 configs/socfpga_agilex_nand_atf_defconfig mode change 100755 => 100644 configs/socfpga_agilex_nand_defconfig mode change 100755 => 100644 configs/socfpga_agilex_qspi_atf_defconfig mode change 100755 => 100644 configs/socfpga_agilex_qspi_defconfig mode change 100755 => 100644 configs/socfpga_stratix10_nand_atf_defconfig mode change 100755 => 100644 configs/socfpga_stratix10_qspi_atf_defconfig copy configs/{socfpga_agilex_qspi_defconfig => socfpga_stratix10_qspi_defconfig} (84%) mode change 100755 => 100644 diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index cc11fc1912..4f5a188a1f 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -93,3 +93,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index f7e767fbbe..bdc5e97026 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -86,3 +86,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig old mode 100755 new mode 100644 index 58a28481f6..bfc893fd39 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -89,4 +89,5 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set \ No newline at end of file +# CONFIG_SPL_USE_TINY_PRINTF is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig old mode 100755 new mode 100644 index f3b3c0b602..3f95aac147 --- a/configs/socfpga_agilex_nand_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -82,4 +82,5 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set \ No newline at end of file +# CONFIG_SPL_USE_TINY_PRINTF is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_qspi_atf_defconfig b/configs/socfpga_agilex_qspi_atf_defconfig old mode 100755 new mode 100644 index 9d97d34c77..b250156fe5 --- a/configs/socfpga_agilex_qspi_atf_defconfig +++ b/configs/socfpga_agilex_qspi_atf_defconfig @@ -78,4 +78,5 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_qspi_defconfig b/configs/socfpga_agilex_qspi_defconfig old mode 100755 new mode 100644 index ee6b7b8660..34e6850ea1 --- a/configs/socfpga_agilex_qspi_defconfig +++ b/configs/socfpga_agilex_qspi_defconfig @@ -72,4 +72,5 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 3c41f16162..be513d4a57 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -94,3 +94,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 5e94a923bc..840e985a45 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -99,3 +99,4 @@ CONFIG_SHA512_ALGO=y CONFIG_SHA384=y CONFIG_FS_LOADER=y CONFIG_SPL_ENV_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 1f69277c8c..bf17d83561 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -87,4 +87,4 @@ CONFIG_SHA512_ALGO=y CONFIG_SHA384=y CONFIG_FS_LOADER=y CONFIG_SPL_ENV_SUPPORT=y - +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 0f55959a45..0a0deb67a0 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -101,3 +101,4 @@ CONFIG_SHA512_ALGO=y CONFIG_SHA384=y CONFIG_FS_LOADER=y CONFIG_SPL_ENV_SUPPORT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 6be4210c7d..adb78975a9 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -93,3 +93,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 07e9f20a41..ad80d35275 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -90,3 +90,4 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig old mode 100755 new mode 100644 index 29c96bf6f1..a9abd85e68 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -90,4 +90,5 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig index f41d2dc82c..48c20e5b11 100644 --- a/configs/socfpga_stratix10_nand_defconfig +++ b/configs/socfpga_stratix10_nand_defconfig @@ -83,4 +83,5 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_stratix10_qspi_atf_defconfig b/configs/socfpga_stratix10_qspi_atf_defconfig old mode 100755 new mode 100644 index d9e55de4dc..6fcb9d7ae0 --- a/configs/socfpga_stratix10_qspi_atf_defconfig +++ b/configs/socfpga_stratix10_qspi_atf_defconfig @@ -78,4 +78,5 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_qspi_defconfig b/configs/socfpga_stratix10_qspi_defconfig old mode 100755 new mode 100644 similarity index 84% copy from configs/socfpga_agilex_qspi_defconfig copy to configs/socfpga_stratix10_qspi_defconfig index ee6b7b8660..a0a2590818 --- a/configs/socfpga_agilex_qspi_defconfig +++ b/configs/socfpga_stratix10_qspi_defconfig @@ -11,24 +11,24 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0xFFE00000 -CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y # CONFIG_PSCI_RESET is not set CONFIG_ARMV8_PSCI=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_qspi" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_qspi" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" -CONFIG_SPL_CACHE=y +CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;run rsu_status;run qspiboot" CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y @@ -72,4 +72,5 @@ CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_PANIC_HANG=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set \ No newline at end of file -- 2.26.2

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd25x512
by Victor Lim 11 Dec '22

11 Dec '22

adding gd25x512 to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index a4eebebc7d..741b40fbde 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -140,6 +140,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | -- 2.25.1

1 0

[PATCH] patch v2: SPI NOR: zynqmp: zynq: gd55t02g
by Victor Lim 11 Dec '22

11 Dec '22

Adding gd55t02g to the file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 6301b4704b..a4eebebc7d 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -138,6 +138,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, { INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | -- 2.25.1

1 0