June 2021 - U-Boot

[RFC PATCH] dfu: handle short frame result of UPLOAD in state_dfu_idle
by Patrick Delaunay 15 Jun '21

15 Jun '21

In DFU v1.1 specification [1] the DFU_UPLOAD (Short Frame) is handled only in dfuUPLOADIDLE state: - Figure A.1 Interface state transition diagram - the state description in chapter A.2 A.2.3 State 2 dfuIDLE on Receipt of the DFU_UPLOAD request,and bitCanUpload = 1 the Next State is dfuUPLOADIDLE A.2.10 State 9 dfuUPLOAD-IDLE When the length of the data transferred by the device in response to a DFU_UPLOAD request is less than wLength. (Short frame) the Next State is dfuIDLE In current code, when an UPLOAD is completely performed after the first request (for example with wLength=200 and data read = 9), the DFU state stay at dfuUPLOADIDLE until receiving a DFU_UPLOAD or a DFU_ABORT request even it is unnecessary as the previous DFU_UPLOAD request already reached the EOF. This RFC patch proposes to finish the DFU uploading (don't go to dfuUPLOADIDLE) and completes the control-read operation (go to DFU_STATE_dfuIDLE) when the first UPLOAD response has a short frame as an end of file (EOF) indicator even if it is not explicitly allowed in the DFU specification but this seems logical. [1] https://www.usb.org/sites/default/files/DFU_1.1.pdf Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- This case is correctly handle in dfu-util, see dfu_load.c dfuload_do_upload() { .... while (1) { ... rc = dfu_upload(dif->dev_handle, dif->interface, xfer_size, transaction++, buf); .... dfu_file_write_crc(fd, 0, buf, rc); total_bytes += rc; if (total_bytes < 0) errx(EX_SOFTWARE, "\nReceived too many bytes (wraparound)"); if (rc < xfer_size) { /* last block, return */ ret = 0; break; } } } In the upload loop the code doesn't make difference for the first request and the next one: the last block is detected as soon as the received data < requested size. So it is safe to do the same in U-Boot's DFU stack, skip the dfuUPLOADIDLE state when the upload operation is finished after the first request. This patch avoid to ABORT the unfinished UPLOAD request before the next command. Patrick. drivers/usb/gadget/f_dfu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 4bedc7d3a1..e9340ff5cb 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -336,6 +336,8 @@ static int state_dfu_idle(struct f_dfu *f_dfu, f_dfu->dfu_state = DFU_STATE_dfuUPLOAD_IDLE; f_dfu->blk_seq_num = 0; value = handle_upload(req, len); + if (value >= 0 && value < len) + f_dfu->dfu_state = DFU_STATE_dfuIDLE; break; case USB_REQ_DFU_ABORT: /* no zlp? */ -- 2.17.1

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[PATCH v2] riscv: andes_plic: Fix riscv_get_ipi() mask
by Bin Meng 15 Jun '21

15 Jun '21

Current logic in riscv_get_ipi() for Andes PLICSW does not look correct. The mask to test IPI pending bits for a hart should be left shifted by (8 * gd->arch.boot_hart), just the same as what is done in riscv_send_ipi(). Fixes: 8b3e97badf97 ("riscv: add functions for reading the IPI status") Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Reviewed-by: Rick Chen <rick(a)andestech.com> Tested-by: Rick Chen <rick(a)andestech.com> --- Changes in v2: - remove RFT tag - update commit message with "Fixes" tag along with the commit id arch/riscv/lib/andes_plic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 221a5fe324..5e113ee8c9 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { + unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); - *pending = !!(*pending & SEND_IPI_TO_HART(hart)); + *pending = !!(*pending & ipi); return 0; } -- 2.25.1

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Re: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit
by Rick Chen 15 Jun '21

15 Jun '21

> From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Friday, June 04, 2021 1:51 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; U-Boot Mailing List <u-boot(a)lists.denx.de> > Subject: [PATCH 4/5] riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit > > All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > arch/riscv/dts/ae350_32.dts | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes
by Rick Chen 15 Jun '21

15 Jun '21

> From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Friday, June 04, 2021 1:51 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; U-Boot Mailing List <u-boot(a)lists.denx.de> > Subject: [PATCH 3/5] riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes > > PLIC nodes don't have child nodes, so #address-cells is not needed. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > arch/riscv/dts/ae350_32.dts | 2 -- > arch/riscv/dts/ae350_64.dts | 2 -- > 2 files changed, 4 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header
by Rick Chen 15 Jun '21

15 Jun '21

> From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Friday, June 04, 2021 1:51 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; U-Boot Mailing List <u-boot(a)lists.denx.de> > Subject: [PATCH 1/5] riscv: ae350: dts: Add SPDX license header > > The SPDX license header is currently missing. Add one. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > arch/riscv/dts/ae350_32.dts | 2 ++ > arch/riscv/dts/ae350_64.dts | 2 ++ > 2 files changed, 4 insertions(+) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config
by Rick Chen 15 Jun '21

15 Jun '21

Hi Bin, > From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Friday, June 04, 2021 1:51 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; U-Boot Mailing List <u-boot(a)lists.denx.de> > Subject: [PATCH 5/5] riscv: ae350: dts: Add missing "u-boot,dm-spl" for SPL config > > At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot. Can you describe how do you verify and provide the steps about that SPL boot fail that I can duplicate it. :) Thanks, Rick. > > Let's add all the required "u-boot,dm-spl" for SPL config. > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > --- > > arch/riscv/dts/ae350-u-boot.dtsi | 52 ++++++++++++++++++++++++++++++++ > arch/riscv/dts/ae350_32.dts | 1 + > arch/riscv/dts/ae350_64.dts | 1 + > 3 files changed, 54 insertions(+) > create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi > > diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi > new file mode 100644 > index 0000000000..0d4201cfae > --- /dev/null > +++ b/arch/riscv/dts/ae350-u-boot.dtsi > @@ -0,0 +1,52 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +/ { > + cpus { > + u-boot,dm-spl; > + CPU0: cpu@0 { > + u-boot,dm-spl; > + CPU0_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + CPU1: cpu@1 { > + u-boot,dm-spl; > + CPU1_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + CPU2: cpu@2 { > + u-boot,dm-spl; > + CPU2_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + CPU3: cpu@3 { > + u-boot,dm-spl; > + CPU3_intc: interrupt-controller { > + u-boot,dm-spl; > + }; > + }; > + }; > + > + memory@0 { > + u-boot,dm-spl; > + }; > + > + soc { > + u-boot,dm-spl; > + > + plic1: interrupt-controller@e6400000 { > + u-boot,dm-spl; > + }; > + > + plmt0@e6000000 { > + u-boot,dm-spl; > + }; > + }; > + > + serial0: serial@f0300000 { > + u-boot,dm-spl; > + }; > + > +}; > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 70576846f2..083f676333 100644 > --- a/arch/riscv/dts/ae350_32.dts > +++ b/arch/riscv/dts/ae350_32.dts > @@ -3,6 +3,7 @@ > /dts-v1/; > > #include "binman.dtsi" > +#include "ae350-u-boot.dtsi" > > / { > #address-cells = <1>; > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 564e94a1db..74cff9122d 100644 > --- a/arch/riscv/dts/ae350_64.dts > +++ b/arch/riscv/dts/ae350_64.dts > @@ -3,6 +3,7 @@ > /dts-v1/; > > #include "binman.dtsi" > +#include "ae350-u-boot.dtsi" > > / { > #address-cells = <2>; > -- > 2.25.1 > > CONFIDENTIALITY NOTICE: > > This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. > > Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

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[PATCH v1 0/1] sunxi: h3: Add initial ZeroPi support
by Yu-Tung Chang 15 Jun '21

15 Jun '21

This commit adds support to FriendlyARM ZeroPi board. Board Schematic: http://wiki.friendlyarm.com/wiki/images/7/71/ZeroPi_20190731_Schematic.pdf - v1 . fix trailing whitespace Yu-Tung Chang (1): sunxi: h3: Add initial ZeroPi support arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-h3-zeropi.dts | 48 ++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 6 ++++ configs/zeropi_defconfig | 13 +++++++++ 4 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-h3-zeropi.dts create mode 100644 configs/zeropi_defconfig -- 2.31.1

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Re: [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask
by Rick Chen 15 Jun '21

15 Jun '21

Hi Bin > From: Bin Meng <bmeng.cn(a)gmail.com> > Sent: Monday, June 14, 2021 11:48 AM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; U-Boot Mailing List <u-boot(a)lists.denx.de> > Subject: Re: [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask > > On Wed, Jun 9, 2021 at 3:55 PM Bin Meng <bmeng.cn(a)gmail.com> wrote: > > > > Current logic in riscv_get_ipi() for Andes PLICSW does not look good > > to me. The mask to test IPI pending bits for a hart should be left > > shifted by (8 * gd->arch.boot_hart), just the same as what is done in > > riscv_send_ipi(). > > > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > > > > --- > > It looks there is no datasheet released from Andes that describes how > > PLICSW works, and its register fields. I can only get an understanding > > from current U-Boot and OpenSBI PLICSW driver. > > > > This requires testing on Andes hardware, which I don't have access to. > > > > arch/riscv/lib/andes_plic.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > Ping? Though there will be only one hart will jump to U-Boot proper currently, and this delay loop seem to be unnecessary. But it is still a good catch. Thanks, Rick Tested-by: Rick Chen <rick(a)andestech.com> Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH] ARM: renesas: Mallocate bootparams on Gen3
by Marek Vasut 15 Jun '21

15 Jun '21

The bootparams do not have to be at fixed location, they can be dynamically mallocated instead. Make it so to get rid of another fixed assignment. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Biju Das <biju.das.jz(a)bp.renesas.com> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> --- board/renesas/condor/condor.c | 3 --- board/renesas/draak/draak.c | 3 --- board/renesas/eagle/eagle.c | 3 --- board/renesas/ebisu/ebisu.c | 3 --- board/renesas/salvator-x/salvator-x.c | 3 --- board/renesas/ulcb/ulcb.c | 3 --- include/configs/rcar-gen3-common.h | 2 ++ 7 files changed, 2 insertions(+), 18 deletions(-) diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c index e930de31b2..2dd2c1534c 100644 --- a/board/renesas/condor/condor.c +++ b/board/renesas/condor/condor.c @@ -21,9 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - return 0; } diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 1d76f95aed..395825f6dc 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -54,9 +54,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index bb32e3d2c5..3417b50f3b 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -65,9 +65,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - return 0; } diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c index 9d4af8d3a6..9a70192596 100644 --- a/board/renesas/ebisu/ebisu.c +++ b/board/renesas/ebisu/ebisu.c @@ -32,9 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - return 0; } diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 071076a336..e4592cafec 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -53,9 +53,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 7ba1948659..b9431c0c57 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -51,9 +51,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index b9762f5beb..99ef27bccd 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -17,6 +17,8 @@ #define CONFIG_SPL_TARGET "spl/u-boot-spl.scif" #endif +#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K + /* boot option */ #define CONFIG_CMDLINE_TAG -- 2.30.2

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[PATCH] ARM: renesas: Turn on PIE for Gen3
by Marek Vasut 15 Jun '21

15 Jun '21

Turn on PIE, so that the U-Boot binary can be started from any arbitrary location in DRAM instead of a predefined fixed one. Note that this patch is not setting SYS_TEXT_BASE=0x0 yet, since that triggers relocation bugs in env code that are yet to be fixed. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Biju Das <biju.das.jz(a)bp.renesas.com> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> --- arch/arm/mach-rmobile/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 41322b2c4c..69e40cf382 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -17,6 +17,7 @@ config RCAR_GEN3 select PINCTRL select PINCONF select PINCTRL_PFC + select POSITION_INDEPENDENT select SUPPORT_SPL imply CMD_FS_UUID imply CMD_GPT -- 2.30.2

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