June 2021 - U-Boot

[PATCH] arm: snapdragon: Fix typo in clk_bcr_update()
by Sheep Sun 16 Jun '21

16 Jun '21

Fix typo in clock-snapdragon.c Signed-off-by: Sheep Sun <sunxiaoyang2003(a)gmail.com> --- arch/arm/mach-snapdragon/clock-snapdragon.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index fbe0b5212f..2b76371718 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -56,15 +56,15 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); } -#define APPS_CMD_RGCR_UPDATE BIT(0) +#define APPS_CMD_RCGR_UPDATE BIT(0) -/* Update clock command via CMD_RGCR */ -void clk_bcr_update(phys_addr_t apps_cmd_rgcr) +/* Update clock command via CMD_RCGR */ +void clk_bcr_update(phys_addr_t apps_cmd_rcgr) { - setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE); + setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE); /* Wait for frequency to be updated. */ - while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE) + while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE) ; } -- 2.30.2

2 1

[PATCH] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 16 Jun '21

16 Jun '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 103 +++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 164 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 61 ++++++++++++ board/phytium/pomelo/pll.c | 75 ++++++++++++++ board/phytium/pomelo/pomelo.c | 120 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 40 ++++++++ configs/pomelo_defconfig | 36 +++++++ include/configs/pomelo.h | 45 +++++++++ 14 files changed, 760 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..6110fcddad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1800,6 +1800,13 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + help + Support for pomelo platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2019,6 +2026,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..c26692c17e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1098,6 +1098,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..4961682058 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000100000; +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu8: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu9: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu12: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu13: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..950449392b --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig + diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..e15917609b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CONFIG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..88756f5fc1 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + unsigned char dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + unsigned char data_width; /* 0: x4; 1: x8; 2: x16 */ + unsigned char mirror_type; /* 0: stardard; 1: mirror */ + unsigned char ecc_type; /* 0: no-ecc; 1:ecc */ + unsigned char dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + unsigned char rank_num; + unsigned char row_num; + unsigned char col_num; + + unsigned char bg_num; /*only DDR4*/ + unsigned char bank_num; + unsigned short int module_manufacturer_id; + unsigned short int taamin; + unsigned short int trcdmin; + + unsigned short int trpmin; + unsigned short int trasmin; + unsigned short int trcmin; + unsigned short int tfawmin; + + unsigned short int trrd_smin; /*only DDR4*/ + unsigned short int trrd_lmin; /*only DDR4*/ + unsigned short int tccd_lmin; /*only DDR4*/ + unsigned short int twrmin; + + unsigned short int twtr_smin; /*only DDR4*/ + unsigned short int twtr_lmin; /*only DDR4*/ + unsigned short int twtrmin; /*only DDR3*/ + unsigned short int trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + unsigned char f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + unsigned char f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + unsigned char f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + unsigned char bc00; + unsigned char bc01; + unsigned char bc02; + unsigned char bc03; + unsigned char bc04; + + unsigned char bc05; + unsigned char f5bc5x; + unsigned char f5bc6x; + /******************* LRDIMM special *****************/ + unsigned char vrefdq_pr0; + unsigned char vrefdq_mdram; + unsigned char rtt_mdram_1866; + unsigned char rtt_mdram_2400; + unsigned char rtt_mdram_3200; + + unsigned char drive_dram; + unsigned char odt_dram_1866; + unsigned char odt_dram_2400; + unsigned char odt_dram_3200; + unsigned char park_dram_1866; + unsigned char park_dram_2400; + unsigned char park_dram_3200; + unsigned char rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + + unsigned char ch_enable; + unsigned char misc1_enable; + unsigned char misc2_enable; + unsigned char force_spd_enable; + unsigned char misc3_enable; + unsigned char train_debug; + unsigned char train_recover; + unsigned char rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static unsigned char init_dimm_param(unsigned char ch, struct mcu_config *pm) +{ + printf("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(unsigned char *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(unsigned char *data) +{ + unsigned char ch; + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + printf("error x0: 0x%lx, x1: 0x%lx\n", res.a0, res.a1); + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..3754d8eb9b --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pcu_ctr { + unsigned int base_config[3]; + unsigned int equalization[3]; + unsigned char rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int independent_tree; + unsigned int base_cfg; + unsigned char rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CONFIG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..1227b7dd80 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pll_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int core_pll; + unsigned int res1; + unsigned int lmu_pll; + unsigned int res2; + unsigned int res3; + unsigned int res4; + unsigned int res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +unsigned int get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} + +void check_reset(void) +{ + unsigned int rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..693e891d20 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + printf("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + printf("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + printf("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + printf("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..8ec0fa797b --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct common_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned long long core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + + if (res.a0 != 0) { + printf("error ret %lx\n", res.a0); + while (true) + ; + } +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..3e6c18196d --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..69c4195d86 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage_old\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x17c000\0" \ + "distro_bootcmd=run load_kernel; run boot_fdt" + +#endif -- 2.17.1

1 0

Please pull u-boot-marvell/master
by Stefan Roese 16 Jun '21

16 Jun '21

Hi Tom, please pull the fix for the Marvell Turris boards: ---------------------------------------------------------------- - Turris: Fix bootcmd_rescue (Pali) ---------------------------------------------------------------- Here the Azure build without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=95&view=results Thanks, Stefan The following changes since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94: Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 029bb91e806ed36dd48f0f967429bd5107464979: arm: mvebu: turris_{omnia, mox}: ensure running bootcmd_rescue always works (2021-06-15 07:21:54 +0200) ---------------------------------------------------------------- Pali Rohár (1): arm: mvebu: turris_{omnia, mox}: ensure running bootcmd_rescue always works board/CZ.NIC/turris_mox/turris_mox.c | 14 +++++++++++--- board/CZ.NIC/turris_omnia/turris_omnia.c | 13 ++++++++++--- 2 files changed, 21 insertions(+), 6 deletions(-)

2 1

[PATCH v3 00/11] clk: k210: Rewrite K210 clock without CCF
by Sean Anderson 16 Jun '21

16 Jun '21

This is something I've been meaning to do for a while but only just got around to. The CCF has been quite unwieldy in a few ways: * It is very rigid, and there are not easy ways to hook into it without rewriting many things. See e.g. things like the bypass clock and all the _half clocks which were created because CCF didn't support the dividers used on the k210. While preparing this series, I encountered several edge cases which I had initially overlooked (or which were not supported in the initial release). These would have been very difficult to fix with CCF, but were much easier to address because each funcion is implemented in one place. * There is a lot of magic going on under the curtains because of all the CCF code which lives in many different files. Some things live in drivers, but many things live in e.g. clk-uclass.c. So many things live in so many files and it can be very difficult to get a handle on what exactly happens. Complicating this is that there is a conflation of struct clk as a handle and struct clk as a device. In this regard, refcounting is completely broken. IMO we should just do away with refcounts and only disable clocks when explicitly asked for. * It is very dependent on runtime initialization. Typically, everything is initialized by calling into various register() functions, usually with several wrappers to avoid specifying all the arguments. This balloons the runtime memory usage since there are so many devices created. It also makes it hard to debug, since if you do it the "typical" way it is easy to accidentally assign a clock to the wrong register. * It inflates code size by pulling in not just some dead code (e.g. this driver does not use divider tables but they are in clk-divider anyway) but also pulling in numerous imx-specific clocks. This could be fixed, but I don't want to due to the other reasons listed. I am very happy to have completely excised it from my driver. IMO there should be big warning signs on the CCF warning not to use it for new code. This would hopefully dissuade those like myself who had no idea that CCF was *not* in fact a good way to write a clock driver. Overall there is a total savings of 12k from this series. text data bss dec hex filename 292485 32672 12624 337781 52775 before/u-boot 283125 29856 12624 325605 4f7e5 after/u-boot This series depends on https://patchwork.ozlabs.org/project/uboot/list/?series=238211 Changes in v3: - Always define clk_defaults_stage, even if clk_set_defaults is a dummy - Fix inverted condition for setting defaults - Fix val not being set for K210_DIV_POWER - Add CLK_K210_SET_RATE to defconfig so these changes apply Changes in v2: - Convert stage to enum - Only force probe clocks pre-reloc - Rebase on u-boot/master Sean Anderson (11): clk: Allow force setting clock defaults before relocation clk: k210: Rewrite to remove CCF clk: k210: Move pll into the rest of the driver clk: k210: Implement soc_clk_dump clk: k210: Re-add support for setting rate clk: k210: Don't set PLL rates if we are already at the correct rate clk: k210: Remove bypass driver clk: k210: Move k210 clock out of its own subdirectory k210: dts: Set PLL1 to the same rate as PLL0 k210: Don't imply CCF test: Add K210 PLL tests to sandbox defconfigs MAINTAINERS | 4 +- arch/riscv/dts/k210.dtsi | 2 + board/sipeed/maix/Kconfig | 2 - configs/sandbox64_defconfig | 2 + configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 2 + configs/sipeed_maix_bitm_defconfig | 2 +- drivers/clk/Kconfig | 14 +- drivers/clk/Makefile | 2 +- drivers/clk/clk-uclass.c | 27 +- drivers/clk/clk_kendryte.c | 1320 +++++++++++++++++++++++ drivers/clk/kendryte/Kconfig | 12 - drivers/clk/kendryte/Makefile | 1 - drivers/clk/kendryte/bypass.c | 273 ----- drivers/clk/kendryte/clk.c | 668 ------------ drivers/clk/kendryte/pll.c | 585 ---------- drivers/clk/rockchip/clk_rk3308.c | 2 +- drivers/core/device.c | 2 +- drivers/net/gmac_rockchip.c | 2 +- include/clk.h | 30 +- include/dt-bindings/clock/k210-sysctl.h | 94 +- include/kendryte/bypass.h | 31 - include/kendryte/clk.h | 35 - include/kendryte/pll.h | 34 - 24 files changed, 1437 insertions(+), 1711 deletions(-) create mode 100644 drivers/clk/clk_kendryte.c delete mode 100644 drivers/clk/kendryte/Kconfig delete mode 100644 drivers/clk/kendryte/Makefile delete mode 100644 drivers/clk/kendryte/bypass.c delete mode 100644 drivers/clk/kendryte/clk.c delete mode 100644 drivers/clk/kendryte/pll.c delete mode 100644 include/kendryte/bypass.h delete mode 100644 include/kendryte/clk.h -- 2.31.0

4 24

[PATCH 1/5] riscv: ae350: dts: Add SPDX license header
by Bin Meng 15 Jun '21

15 Jun '21

The SPDX license header is currently missing. Add one. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/riscv/dts/ae350_32.dts | 2 ++ arch/riscv/dts/ae350_64.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index a0ab5e9be2..ef110c54ae 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + /dts-v1/; #include "binman.dtsi" diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index f654f4809a..6abf42e904 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + /dts-v1/; #include "binman.dtsi" -- 2.25.1

2 9

[PATCH 0/2] AM64: Update the locations of various elements in SRAM
by Aswath Govindraju 15 Jun '21

15 Jun '21

The following series of patches, - Update the location of TF-A - Indicate reserved locations for DMSC code and secure proxy Aswath Govindraju (2): configs: am64x_evm_a53_defconfig: Move TF-A load address to 0x701c4000 arm: dts: k3-am64-main: Indicate the memory reserved for DMSC-lite code and secure proxy communication buffer arch/arm/dts/k3-am64-main.dtsi | 12 ++++++++++-- configs/am64x_evm_a53_defconfig | 2 +- 2 files changed, 11 insertions(+), 3 deletions(-) -- 2.17.1

1 2

[PATCH] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 15 Jun '21

15 Jun '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 34 +++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 164 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 +++++++++++ board/phytium/pomelo/pll.c | 74 ++++++++++++++ board/phytium/pomelo/pomelo.c | 120 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 39 ++++++++ configs/pomelo_defconfig | 36 +++++++ include/configs/pomelo.h | 45 +++++++++ 14 files changed, 688 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..6110fcddad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1800,6 +1800,13 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + help + Support for pomelo platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2019,6 +2026,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..c26692c17e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1098,6 +1098,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..e9602cb3a8 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000100000; +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..950449392b --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig + diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..e15917609b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CONFIG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..b3471721f2 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <common.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + unsigned char dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + unsigned char data_width; /* 0: x4; 1: x8; 2: x16 */ + unsigned char mirror_type; /* 0: stardard; 1: mirror */ + unsigned char ecc_type; /* 0: no-ecc; 1:ecc */ + unsigned char dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + unsigned char rank_num; + unsigned char row_num; + unsigned char col_num; + + unsigned char bg_num; /*only DDR4*/ + unsigned char bank_num; + unsigned short int module_manufacturer_id; + unsigned short int taamin; + unsigned short int trcdmin; + + unsigned short int trpmin; + unsigned short int trasmin; + unsigned short int trcmin; + unsigned short int tfawmin; + + unsigned short int trrd_smin; /*only DDR4*/ + unsigned short int trrd_lmin; /*only DDR4*/ + unsigned short int tccd_lmin; /*only DDR4*/ + unsigned short int twrmin; + + unsigned short int twtr_smin; /*only DDR4*/ + unsigned short int twtr_lmin; /*only DDR4*/ + unsigned short int twtrmin; /*only DDR3*/ + unsigned short int trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + unsigned char f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + unsigned char f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + unsigned char f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + unsigned char bc00; + unsigned char bc01; + unsigned char bc02; + unsigned char bc03; + unsigned char bc04; + + unsigned char bc05; + unsigned char f5bc5x; + unsigned char f5bc6x; + /******************* LRDIMM special *****************/ + unsigned char vrefdq_pr0; + unsigned char vrefdq_mdram; + unsigned char rtt_mdram_1866; + unsigned char rtt_mdram_2400; + unsigned char rtt_mdram_3200; + + unsigned char drive_dram; + unsigned char odt_dram_1866; + unsigned char odt_dram_2400; + unsigned char odt_dram_3200; + unsigned char park_dram_1866; + unsigned char park_dram_2400; + unsigned char park_dram_3200; + unsigned char rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + + unsigned char ch_enable; + unsigned char misc1_enable; + unsigned char misc2_enable; + unsigned char force_spd_enable; + unsigned char misc3_enable; + unsigned char train_debug; + unsigned char train_recover; + unsigned char rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static unsigned char init_dimm_param(unsigned char ch, struct mcu_config *pm) +{ + printf("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(unsigned char *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(unsigned char *data) +{ + unsigned char ch; + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + printf("error x0: 0x%lx, x1: 0x%lx\n", res.a0, res.a1); + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..6d7792f0be --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <common.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pcu_ctr { + unsigned int base_config[3]; + unsigned int equalization[3]; + unsigned char rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int independent_tree; + unsigned int base_cfg; + unsigned char rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CONFIG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..095131e815 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pll_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int core_pll; + unsigned int res1; + unsigned int lmu_pll; + unsigned int res2; + unsigned int res3; + unsigned int res4; + unsigned int res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +unsigned int get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} + +void check_reset(void) +{ + unsigned int rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..6442bb80d3 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <common.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + printf("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + printf("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + printf("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + printf("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..c000b3f369 --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <common.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct common_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned long long core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + + if (res.a0 != 0) { + printf("error ret %lx\n", res.a0); + while (true) + ; + } +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..3e6c18196d --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..69c4195d86 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage_old\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x17c000\0" \ + "distro_bootcmd=run load_kernel; run boot_fdt" + +#endif -- 2.17.1

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[PATCH] drivers/mmc/rpmb.c: Fix driver routing memory alignment with tmp buffer
by Timothée Cercueil 15 Jun '21

15 Jun '21

From: litchipi <litchi.pi(a)protonmail.com> Fix mmc_rpmb_route_frames() implementation to comply with most MMC drivers that expect some alignment of MMC data frames in memory. When called from drivers/tee/optee/rpmb.c, the address passed is not aligned properly. OP-TEE OS inserts a 6-byte header before a raw RPMB frame which makes RPMB data buffer not 32bit aligned. To prevent breaking ABI with OPTEE-OS RPC memrefs, allocate a temporary buffer to copy the data into an aligned memory. Many RPMB drivers implicitly expect 32bit alignment of the eMMC frame including arm_pl180_mmci.c, sandbox_mmc.c and stm32_sdmmc2.c Signed-off-by: Timothée Cercueil <timothee.cercueil(a)st.com> Signed-off-by: litchipi <litchi.pi(a)protonmail.com> Change-Id: Iec7554cf6be1219e2d80eb7b45d8d60531c9a7d6 Signed-off-by: Timothée Cercueil <litchi.pi(a)protonmail.com> --- drivers/mmc/rpmb.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index ea7e506666..b68d98573c 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -480,10 +480,24 @@ int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen, * and possibly just delay an eventual error which will be harder * to track down. */ + void *rpmb_data = NULL; + int ret; if (reqlen % sizeof(struct s_rpmb) || rsplen % sizeof(struct s_rpmb)) return -EINVAL; - return rpmb_route_frames(mmc, req, reqlen / sizeof(struct s_rpmb), - rsp, rsplen / sizeof(struct s_rpmb)); + if (!IS_ALIGNED((uintptr_t)req, ARCH_DMA_MINALIGN)) { + /* Memory alignment is required by MMC driver */ + rpmb_data = malloc(reqlen); + if (!rpmb_data) + return -ENOMEM; + + memcpy(rpmb_data, req, reqlen); + req = rpmb_data; + } + + ret = rpmb_route_frames(mmc, req, reqlen / sizeof(struct s_rpmb), + rsp, rsplen / sizeof(struct s_rpmb)); + free(rpmb_data); + return ret; } -- 2.17.1

2 1

[PATCH] efi_loader: FMP cleanups
by Ilias Apalodimas 15 Jun '21

15 Jun '21

Right now we allow both of the FMPs (RAW and FIT based) to be installed at the same time. Moreover we only install those if a CapsuleUpdate is requested. Since we now have an ESRT table, it makes more sense to unconditionally install the FMP, so any userspace applications (e.g fwupd) can make use of them and trigger an update. While at it clean up the FMP installation as well. Chapter 23 of the EFI spec (rev 2.9) says: "A specific updatable hardware firmware store must be represented by exactly one FMP instance". This is not the case for us, since both of our FMP protocols can be installed at the same time and are controlled by a single 'dfu_alt_info' env variable. So make the config option a choice and allow the user to install one of them at any given time. The overall changes show up in fwupd pre-patch: fwupdmgr get-devices No detected devices post-patch (with FIT FMP installed): fwupdmgr get-devices WARNING: Required efivarfs filesystem was not found See https://github.com/fwupd/fwupd/wiki/PluginFlag:efivar-not-mounted for more information. Unknown Product │ └─Unknown Firmware: Device ID: 605080e08f71dabb86d0781c28f7d923edabf7d6 Current version: 0 Vendor: DMI:U-Boot Update Error: Not updatable as efivarfs was not found GUIDs: ae13ff2d-9ad4-4e25-9ac8-6d80b3b22147 230c8b18-8d9b-53ec-838b-6cfc0383493a ← main-system-firmware 1a1da7d4-0a24-51b5-8a1a-1e3274328094 ← UEFI\RES_{AE13FF2D-9AD4-4E25-9AC8-6D80B3B22147} Device Flags: • Internal device • System requires external power source • Needs a reboot after installation • Device is usable for the duration of the update Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- configs/sandbox64_defconfig | 1 - configs/sandbox_defconfig | 1 - configs/xilinx_zynqmp_virt_defconfig | 1 - include/efi_loader.h | 1 + lib/efi_loader/Kconfig | 48 +++++++++++++++------------- lib/efi_loader/efi_capsule.c | 22 ++++--------- lib/efi_loader/efi_setup.c | 4 +++ 7 files changed, 37 insertions(+), 41 deletions(-) diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 9a373bab6fe3..af18b6c7826e 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -233,7 +233,6 @@ CONFIG_LZ4=y CONFIG_ERRNO_STR=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index bdbf714e2bd9..24313fdfa53d 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -280,7 +280,6 @@ CONFIG_LZ4=y CONFIG_ERRNO_STR=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_EFI_SECURE_BOOT=y CONFIG_TEST_FDTDEC=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index e939b04ef6a5..0c2d1a70a5a1 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -188,5 +188,4 @@ CONFIG_EFI_SET_TIME=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y -CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/include/efi_loader.h b/include/efi_loader.h index 0a9c82a257e1..b81180cfda8b 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -972,4 +972,5 @@ efi_status_t efi_esrt_register(void); * - error code otherwise. */ efi_status_t efi_esrt_populate(void); +efi_status_t efi_load_capsule_drivers(void); #endif /* _EFI_LOADER_H */ diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 6242caceb7f9..da6f5faf5adb 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -161,6 +161,31 @@ config EFI_CAPSULE_FIRMWARE_MANAGEMENT Select this option if you want to enable capsule-based firmware update using Firmware Management Protocol. +choice EFI_CAPSULE_TYPE + prompt "Capsule type (RAW/FIT)" + depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT + +config EFI_CAPSULE_FIRMWARE_FIT + bool "FMP driver for FIT images" + depends on FIT + select UPDATE_FIT + select DFU + select EFI_CAPSULE_FIRMWARE + help + Select this option if you want to enable firmware management protocol + driver for FIT image + +config EFI_CAPSULE_FIRMWARE_RAW + bool "FMP driver for raw images" + select DFU_WRITE_ALT + select DFU + select EFI_CAPSULE_FIRMWARE + help + Select this option if you want to enable firmware management protocol + driver for raw image + +endchoice + config EFI_CAPSULE_AUTHENTICATE bool "Update Capsule authentication" depends on EFI_CAPSULE_FIRMWARE @@ -181,29 +206,6 @@ config EFI_CAPSULE_AUTHENTICATE Select this option if you want to enable capsule authentication -config EFI_CAPSULE_FIRMWARE_FIT - bool "FMP driver for FIT image" - depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT - depends on FIT - select UPDATE_FIT - select DFU - select EFI_CAPSULE_FIRMWARE - default n - help - Select this option if you want to enable firmware management protocol - driver for FIT image - -config EFI_CAPSULE_FIRMWARE_RAW - bool "FMP driver for raw image" - depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT - select DFU - select DFU_WRITE_ALT - select EFI_CAPSULE_FIRMWARE - default n - help - Select this option if you want to enable firmware management protocol - driver for raw image - config EFI_DEVICE_PATH_TO_TEXT bool "Device path to text protocol" default y diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 9ead0d2c7816..3b4214a8d4cc 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -918,31 +918,27 @@ static void efi_capsule_scan_done(void) } /** - * arch_efi_load_capsule_drivers - initialize capsule drivers + * efi_load_capsule_drivers - initialize capsule drivers * - * Architecture or board specific initialization routine + * Generic FMP drivers backed by DFU * * Return: status code */ -efi_status_t __weak arch_efi_load_capsule_drivers(void) +efi_status_t efi_load_capsule_drivers(void) { - __maybe_unused efi_handle_t handle; + __maybe_unused efi_handle_t handle = NULL; efi_status_t ret = EFI_SUCCESS; - if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)) { - handle = NULL; + if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_FIT)) ret = EFI_CALL(efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL)); - } - if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) { - handle = NULL; + if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) ret = EFI_CALL(efi_install_multiple_protocol_interfaces( - &efi_root, + &handle, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)); - } return ret; } @@ -975,10 +971,6 @@ efi_status_t efi_launch_capsules(void) index = get_last_capsule(); - /* Load capsule drivers */ - ret = arch_efi_load_capsule_drivers(); - if (ret != EFI_SUCCESS) - return ret; /* * Find capsules on disk. diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 3c5cf9a4357e..0106efdc161b 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -254,6 +254,10 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + ret = efi_load_capsule_drivers(); + if (ret != EFI_SUCCESS) + goto out; + #if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO) ret = efi_gop_register(); if (ret != EFI_SUCCESS) -- 2.32.0.rc0

3 13

[PATCH u-boot-marvell] arm: mvebu: turris_{omnia, mox}: ensure running bootcmd_rescue always works
by Marek Behún 15 Jun '21

15 Jun '21

From: Pali Rohár <pali(a)kernel.org> One of the points of putting the rescue boot command into default environment is that user can invoke it without physical access to the board (without having to press the factory reset button), by running run bootcmd_rescue in U-Boot's console. Therefore we have to ensure that bootcmd_rescue is always set to default value, regardless of whether the factory reset button was pressed. Otherwise the variable will be empty for example after upgrade from previous U-Boot. Fixes: ec3784d62646 ("arm: mvebu: turris_mox: add support for board rescue mode") Fixes: 176c3e7760a2 ("arm: mvebu: turris_omnia: support invoking rescue boot from console") Signed-off-by: Pali Rohár <pali(a)kernel.org> Signed-off-by: Marek Behún <marek.behun(a)nic.cz> --- board/CZ.NIC/turris_mox/turris_mox.c | 14 +++++++++++--- board/CZ.NIC/turris_omnia/turris_omnia.c | 13 ++++++++++--- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 44c272c7cb..428cd23a19 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -440,10 +440,18 @@ static bool read_reset_button(void) static void handle_reset_button(void) { + const char * const vars[1] = { "bootcmd_rescue", }; + + /* + * Ensure that bootcmd_rescue has always stock value, so that running + * run bootcmd_rescue + * always works correctly. + */ + env_set_default_vars(1, (char * const *)vars, 0); + if (read_reset_button()) { - const char * const vars[3] = { + const char * const vars[2] = { "bootcmd", - "bootcmd_rescue", "distro_bootcmd", }; @@ -451,7 +459,7 @@ static void handle_reset_button(void) * Set the above envs to their default values, in case the user * managed to break them. */ - env_set_default_vars(3, (char * const *)vars, 0); + env_set_default_vars(2, (char * const *)vars, 0); /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index ade923f599..8b2f94f959 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -339,9 +339,17 @@ static int set_regdomain(void) static void handle_reset_button(void) { + const char * const vars[1] = { "bootcmd_rescue", }; int ret; u8 reset_status; + /* + * Ensure that bootcmd_rescue has always stock value, so that running + * run bootcmd_rescue + * always works correctly. + */ + env_set_default_vars(1, (char * const *)vars, 0); + ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); if (ret) { printf("omnia_mcu_read failed: %i, reset status unknown!\n", @@ -352,9 +360,8 @@ static void handle_reset_button(void) env_set_ulong("omnia_reset", reset_status); if (reset_status) { - const char * const vars[3] = { + const char * const vars[2] = { "bootcmd", - "bootcmd_rescue", "distro_bootcmd", }; @@ -362,7 +369,7 @@ static void handle_reset_button(void) * Set the above envs to their default values, in case the user * managed to break them. */ - env_set_default_vars(3, (char * const *)vars, 0); + env_set_default_vars(2, (char * const *)vars, 0); /* Ensure bootcmd_rescue is used by distroboot */ env_set("boot_targets", "rescue"); -- 2.31.1

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