June 2021 - U-Boot

[PATCH] board: sama5d3_xplained: add Falcon boot support
by Michael Opdenacker 14 Jun '21

14 Jun '21

This supports Falcon boot support for Microchip SAMA5D3 Xplained, tested on raw MMC, and on raw NAND. spl_start_uboot() is has the simplest possible implementation. It doesn't test the environment because enabling environment support currently causes the SPL to exceed its maximum size (64 KiB). It doesn't check the serial for incoming characters either because this functionality currently doesn't seem to work from the SPL on this board. Settings for Falcon boot from at FAT partition are also added to avoid compile failures when CONFIG_SPL_OS_BOOT is enabled, but this particular case is currently not functional as adding FAT and partition support cause the SPL to be too big again. Signed-off-by: Michael Opdenacker <michael.opdenacker(a)bootlin.com> --- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 7 +++++++ include/configs/sama5d3_xplained.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index db9603f584..c25bf42e0a 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -132,6 +132,13 @@ void spl_board_init(void) #endif } +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + static void ddr2_conf(struct atmel_mpddrc_config *ddr2) { ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 1113214bcf..4c25964b43 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -79,4 +79,18 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 +/* Falcon boot support on raw MMC */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +/* U-Boot proper stored by default at 0x200 (256 KiB) */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x22000000 + +/* Falcon boot support on FAT on MMC */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" + +/* Falcon boot support on raw NAND */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x1a0000 + #endif -- 2.25.1

2 1

[PATCH] configs: sam boards: add hash command
by Eugen Hristev 14 Jun '21

14 Jun '21

Add hash and hash verify commands. These would be useful for verifying copied data. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- configs/sam9x60ek_mmc_defconfig | 2 ++ configs/sam9x60ek_nandflash_defconfig | 2 ++ configs/sam9x60ek_qspiflash_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc1_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc_defconfig | 2 ++ configs/sama5d27_som1_ek_qspiflash_defconfig | 2 ++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 2 ++ configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 2 ++ configs/sama5d2_icp_mmc_defconfig | 2 ++ configs/sama5d2_ptc_ek_mmc_defconfig | 2 ++ configs/sama5d2_ptc_ek_nandflash_defconfig | 2 ++ configs/sama5d2_xplained_emmc_defconfig | 2 ++ configs/sama5d2_xplained_mmc_defconfig | 2 ++ configs/sama5d2_xplained_qspiflash_defconfig | 2 ++ configs/sama5d2_xplained_spiflash_defconfig | 2 ++ configs/sama5d3_xplained_mmc_defconfig | 2 ++ configs/sama5d3_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_mmc_defconfig | 2 ++ configs/sama5d4_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_spiflash_defconfig | 2 ++ configs/sama7g5ek_mmc1_defconfig | 2 ++ configs/sama7g5ek_mmc_defconfig | 2 ++ 22 files changed, 44 insertions(+) diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index 81d2724580..e5b5226324 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index 779b59f483..0cf940f8d7 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index 694c74bd63..57a87a67e9 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 66b5f25703..fbc07360d8 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index b7d3b64d15..6be9cc1896 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 4425fa610f..2467f4041f 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index c60d4c6be5..83901980ff 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 44124cdf49..3cb1ff62aa 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -46,6 +46,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 88d6e1f5b0..c9e82d03b8 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig index 8df3b3e6d5..b738e3fcab 100644 --- a/configs/sama5d2_ptc_ek_mmc_defconfig +++ b/configs/sama5d2_ptc_ek_mmc_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 6d57551b34..89ff40d16c 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index bd6dbff564..1f3f728442 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index add797b7ca..8c637c4e79 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 4dbe6de722..ea3e3b54b5 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 64ca9dd2a2..5b6d1f4442 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 3538dfd1bc..162a59d94e 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index c763a8dc59..978b4ed19a 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 03f2aa18b5..0754ead165 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 007ee7740e..05e67c7a7e 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -39,6 +39,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index af85192d0b..5828f375dc 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_NAND=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index c73b8de0ea..337b58bc91 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index 9326f53444..1dbf5276dc 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_MMC=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y -- 2.25.1

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[GIT PULL v2] TI changes for v2021.10 next
by Lokesh Vutla 14 Jun '21

14 Jun '21

Hi Tom, Please find the PR for master branch targeted for v2021.10-next branch with checkpatch warnings fixed. Details about the PR are updated in the tag message. Gitlab CI report: https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/7817 The following changes since commit e8f720ee1707b43a0e14ade87b40a1f84baeb2f3: Merge branch '2021-06-08-kconfig-migrations' into next (2021-06-09 08:19:13 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-ti.git tags/ti-v2021.10-next-v2 for you to fetch changes up to 5abb694d6016eaf497c3d9a3ec79382e217e7508: dma: ti: k3-udma: Add support for native configuration of chan/flow (2021-06-11 19:18:52 +0530) ---------------------------------------------------------------- - HSM re-architecture support for all K3 platforms - AM64 USB support - Driver model support for Davinci RTC ---------------------------------------------------------------- Aswath Govindraju (10): tools: k3_fit_atf: Add support for providing ATF load address using a Kconfig symbol arm: mach-k3: am642_init: Add support for USB boot mode arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modes board: ti: am64x: Set the core voltage of USB PHY to 0.85V arm: dts: k3-am64-main: Add USB DT nodes arm: dts: k3-am642-*-evm: Add USB support arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to peripheral for USB subsystem configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode arm: dts: k3-am64-main: Update the location of ATF in SRAM and increase its max size configs: am64: Enable configs to support USB host and device modes Dario Binacchi (8): rtc: davinci: enable compilation for omap architectures rtc: davinci: fix compiler errors rtc: davinci: replace 32bit access with 8bit access rtc: davinci: check BUSY bit before set TC registers rtc: davinci: use unlock/lock mechanism arm: dts: sync rtc node of am335x boards with Linux 5.9-rc7 rtc: davinci: add driver model support rtc: davinci: fix date loaded on reset Dave Gerlach (4): arm: mach-k3: Add platform data for j721e and j7200 arm: mach-k3: common: Drop main r5 start arm: mach-k3: j721e_init: Force early probe of clk-k3 driver configs: j7200_evm_r5: Enable raw access power management features Kevin Scholz (1): arm: dts: k3-j7200: ddr: Update to 0.5.0 version of DDR for LPDDR 2666MTs Lokesh Vutla (1): common: fit: Update board_fit_image_post_process() to pass fit and node_offset Pali Rohár (1): Nokia RX-51: Enable CONFIG_WDT to remove deprecation warning Tero Kristo (21): lib: rational: copy the rational fraction lib routines from Linux arm: mach-k3: introduce new config option for sysfw split remoteproc: k3-r5: remove sysfw PM calls if not supported clk: fixed_rate: add API for directly registering fixed rate clocks clk: fix clock tree dump to properly dump out every registered clock clk: do not attempt to fetch clock pointer with null device clk: add support for setting clk rate from cmdline clk: sci-clk: fix return value of set_rate clk: fix assigned-clocks to pass with deferring provider clk: fix set_rate to clean up cached rates for the hierarchy clk: add support for TI K3 SoC PLL clk: add support for TI K3 SoC clocks power: domain: Introduce driver for raw TI K3 PDs cmd: ti: pd: Add debug command for K3 power domains tools: k3_fit_atf: add DM binary to the FIT image arm: mach-k3: add support for detecting firmware images from FIT arm: mach-k3: do board config for PM only if supported arm: mach-k3: sysfw-loader: pass boardcfg to sciserver configs: j721e_evm_r5: Enable raw access power management features board: ti: j72xx: README: update build instructions and image formats arm: dts: k3-j72xx: correct MCU timer1 frequency Vignesh Raghavendra (7): mailbox: k3-sec-proxy: Add DM to DMSC communication thread firmware: ti_sci: Implement GET_RANGE with static data firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node ARM: dts: k3: Add cfg register space for ringacc and udmap soc: ti: k3-navss-ringacc: Add support for native configuration of rings dma: ti: k3-udma: Add support for native configuration of chan/flow arch/arm/dts/am335x-bone-common.dtsi | 5 + arch/arm/dts/am335x-evm.dts | 5 + arch/arm/dts/am335x-evmsk.dts | 5 + arch/arm/dts/am335x-osd335x-common.dtsi | 6 + arch/arm/dts/k3-am64-main.dtsi | 32 +- arch/arm/dts/k3-am642-evm-u-boot.dtsi | 13 + arch/arm/dts/k3-am642-evm.dts | 18 + arch/arm/dts/k3-am642-r5-evm.dts | 18 + arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 + .../arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 28 +- ...p4-1600.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} | 437 ++++++------ arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 19 +- .../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 16 +- arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 + arch/arm/mach-k3/Kconfig | 18 + arch/arm/mach-k3/Makefile | 2 +- arch/arm/mach-k3/am642_init.c | 46 +- arch/arm/mach-k3/common.c | 87 ++- arch/arm/mach-k3/common.h | 1 + arch/arm/mach-k3/config.mk | 5 + arch/arm/mach-k3/include/mach/am64_hardware.h | 11 +- arch/arm/mach-k3/include/mach/am64_spl.h | 6 +- arch/arm/mach-k3/j7200/Makefile | 5 + arch/arm/mach-k3/j7200/clk-data.c | 547 +++++++++++++++ arch/arm/mach-k3/j7200/dev-data.c | 77 ++ arch/arm/mach-k3/j721e/Makefile | 5 + arch/arm/mach-k3/j721e/clk-data.c | 781 +++++++++++++++++++++ arch/arm/mach-k3/j721e/dev-data.c | 75 ++ arch/arm/mach-k3/j721e_init.c | 12 + arch/arm/mach-k3/security.c | 2 +- arch/arm/mach-k3/sysfw-loader.c | 111 ++- arch/arm/mach-keystone/mon.c | 3 +- arch/arm/mach-socfpga/board.c | 3 +- board/nokia/rx51/rx51.c | 37 +- board/ti/am335x/board.c | 3 +- board/ti/am43xx/board.c | 3 +- board/ti/am57xx/board.c | 3 +- board/ti/am64x/evm.c | 14 + board/ti/dra7xx/evm.c | 3 +- board/ti/j721e/README | 9 +- cmd/clk.c | 80 ++- cmd/ti/Kconfig | 8 + cmd/ti/Makefile | 1 + cmd/ti/pd.c | 185 +++++ common/image-fit.c | 2 +- common/spl/spl_fit.c | 2 +- configs/am64x_evm_a53_defconfig | 40 ++ configs/am64x_evm_r5_defconfig | 38 +- configs/j7200_evm_r5_defconfig | 14 +- configs/j721e_evm_r5_defconfig | 12 +- configs/nokia_rx51_defconfig | 2 + .../firmware/ti,j721e-dm-sci.txt | 32 + drivers/clk/clk-uclass.c | 39 + drivers/clk/clk_fixed_rate.c | 45 ++ drivers/clk/ti/Kconfig | 24 + drivers/clk/ti/Makefile | 2 + drivers/clk/ti/clk-k3-pll.c | 283 ++++++++ drivers/clk/ti/clk-k3.c | 374 ++++++++++ drivers/clk/ti/clk-sci.c | 6 +- drivers/dma/ti/k3-udma-u-boot.c | 177 +++++ drivers/dma/ti/k3-udma.c | 42 +- drivers/firmware/ti_sci.c | 107 +++ drivers/firmware/ti_sci_static_data.h | 92 +++ drivers/mailbox/k3-sec-proxy.c | 2 +- drivers/power/domain/Kconfig | 7 + drivers/power/domain/Makefile | 1 + drivers/power/domain/ti-power-domain.c | 368 ++++++++++ drivers/remoteproc/ti_k3_r5f_rproc.c | 30 +- drivers/rtc/Kconfig | 7 + drivers/rtc/davinci.c | 460 ++++++++++-- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 ++ drivers/soc/ti/k3-navss-ringacc.c | 36 +- include/configs/am64x_evm.h | 15 +- include/configs/nokia_rx51.h | 3 - include/image.h | 5 +- include/k3-clk.h | 176 +++++ include/k3-dev.h | 85 +++ include/linux/clk-provider.h | 3 + include/linux/rational.h | 20 + lib/Kconfig | 7 + lib/Makefile | 2 + lib/rational.c | 99 +++ tools/k3_fit_atf.sh | 28 +- 83 files changed, 5167 insertions(+), 358 deletions(-) rename arch/arm/dts/{k3-j7200-ddr-evm-lp4-1600.dtsi => k3-j7200-ddr-evm-lp4-2666.dtsi} (90%) create mode 100644 arch/arm/mach-k3/j7200/Makefile create mode 100644 arch/arm/mach-k3/j7200/clk-data.c create mode 100644 arch/arm/mach-k3/j7200/dev-data.c create mode 100644 arch/arm/mach-k3/j721e/Makefile create mode 100644 arch/arm/mach-k3/j721e/clk-data.c create mode 100644 arch/arm/mach-k3/j721e/dev-data.c create mode 100644 cmd/ti/pd.c create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt create mode 100644 drivers/clk/ti/clk-k3-pll.c create mode 100644 drivers/clk/ti/clk-k3.c create mode 100644 drivers/dma/ti/k3-udma-u-boot.c create mode 100644 drivers/firmware/ti_sci_static_data.h create mode 100644 drivers/power/domain/ti-power-domain.c create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c create mode 100644 include/k3-clk.h create mode 100644 include/k3-dev.h create mode 100644 include/linux/rational.h create mode 100644 lib/rational.c -- 2.30.0

4 3

[PATCH] arm64: zynqmp: Add support for 64bit addresses in its
by Michal Simek 14 Jun '21

14 Jun '21

Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also generate u-boot.its with 64bit load/entry addresses to also support different configurations. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh index 700871dbe109..592be7f67066 100755 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -13,6 +13,8 @@ BL31_ELF="${BL31%.*}.elf" awk '/Entry point/ { print $3 }'` [ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0xfffea000" +ATF_LOAD_ADDR_LOW=`printf 0x%x $((ATF_LOAD_ADDR & 0xffffffff))` +ATF_LOAD_ADDR_HIGH=`printf 0x%x $((ATF_LOAD_ADDR >> 32))` [ -z "$BL32" ] && BL32="tee.bin" BL32_ELF="${BL32%.*}.elf" @@ -20,14 +22,20 @@ BL32_ELF="${BL32%.*}.elf" awk '/Entry point/ { print $3 }'` [ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0x60000000" +TEE_LOAD_ADDR_LOW=`printf 0x%x $((TEE_LOAD_ADDR & 0xffffffff))` +TEE_LOAD_ADDR_HIGH=`printf 0x%x $((TEE_LOAD_ADDR >> 32))` if [ -z "$BL33_LOAD_ADDR" ];then BL33_LOAD_ADDR=`awk '/CONFIG_SYS_TEXT_BASE/ { print $3 }' include/generated/autoconf.h` fi +BL33_LOAD_ADDR_LOW=`printf 0x%x $((BL33_LOAD_ADDR & 0xffffffff))` +BL33_LOAD_ADDR_HIGH=`printf 0x%x $((BL33_LOAD_ADDR >> 32))` DTB_LOAD_ADDR=`awk '/CONFIG_XILINX_OF_BOARD_DTB_ADDR/ { print $3 }' include/generated/autoconf.h` if [ ! -z "$DTB_LOAD_ADDR" ]; then - DTB_LOAD="load = <$DTB_LOAD_ADDR>;" + DTB_LOAD_ADDR_LOW=`printf 0x%x $((DTB_LOAD_ADDR & 0xffffffff))` + DTB_LOAD_ADDR_HIGH=`printf 0x%x $((DTB_LOAD_ADDR >> 32))` + DTB_LOAD="load = <$DTB_LOAD_ADDR_HIGH $DTB_LOAD_ADDR_LOW>;" else DTB_LOAD="" fi @@ -59,8 +67,8 @@ cat << __HEADER_EOF os = "u-boot"; arch = "arm64"; compression = "none"; - load = <$BL33_LOAD_ADDR>; - entry = <$BL33_LOAD_ADDR>; + load = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>; + entry = <$BL33_LOAD_ADDR_HIGH $BL33_LOAD_ADDR_LOW>; hash { algo = "md5"; }; @@ -76,8 +84,8 @@ cat << __ATF os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; - load = <$ATF_LOAD_ADDR>; - entry = <$ATF_LOAD_ADDR>; + load = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>; + entry = <$ATF_LOAD_ADDR_HIGH $ATF_LOAD_ADDR_LOW>; hash { algo = "md5"; }; @@ -94,8 +102,8 @@ cat << __TEE os = "tee"; arch = "arm64"; compression = "none"; - load = <$TEE_LOAD_ADDR>; - entry = <$TEE_LOAD_ADDR>; + load = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>; + entry = <$TEE_LOAD_ADDR_HIGH $TEE_LOAD_ADDR_LOW>; hash { algo = "md5"; }; -- 2.31.1

2 1

[PATCH 0/6] arm64: zynqmp: DT syncup patches
by Michal Simek 14 Jun '21

14 Jun '21

Hi, this series is trying to clean and sync DTS files. At the end we want to have all these files be in sync with the Linux kernel based on DT binding available in the Linux kernel. Thanks, Michal Michal Simek (6): arm64: zynqmp: Remove additional header from zc1232 DT arm64: zynqmp: Add maximum-speed property for dwc3 nodes arm64: zynqmp: Remove addition newline from zc1751 dc1 arm64: zynqmp: Remove unused dp_aclk clock arm64: zynqmp: Sync dp port location on zc1751 dc4 arm64: zynqmp: Sync psgtr location on zcu100/zcu106 arch/arm/dts/zynqmp-clk-ccf.dtsi | 7 ------- arch/arm/dts/zynqmp-zc1232-revA.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 16 ++++++++-------- arch/arm/dts/zynqmp-zcu100-revC.dts | 14 +++++++------- arch/arm/dts/zynqmp-zcu106-revA.dts | 15 ++++++++------- arch/arm/dts/zynqmp-zcu111-revA.dts | 1 + arch/arm/dts/zynqmp-zcu208-revA.dts | 1 + arch/arm/dts/zynqmp-zcu216-revA.dts | 1 + 9 files changed, 27 insertions(+), 31 deletions(-) -- 2.31.1

2 7

[PATCH 0/7] arm64: zynqmp: DT syncup patches next
by Michal Simek 14 Jun '21

14 Jun '21

Hi, this is the next series which is trying to clean and sync DTS files. At the end we want to have all these files be in sync with the Linux kernel based on DT binding available in the Linux kernel. Thanks, Michal Michal Simek (6): xilinx: Convert xlnx,eeprom property to nvmem alias arm64: zynqmp: Remove si5328 and si5382 nodes arm64: zynqmp: Remove can aliases from zc1751 arm64: zynqmp: Remove unused property from SD/USB arm64: zynqmp: Remove information about dma clock on zcu106 arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1 Srinivas Neeli (1): arm64: zynqmp: rtc: Update rtc calibration value ...ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 2 +- arch/arm/dts/zynq-syzygy-hub.dts | 2 +- arch/arm/dts/zynqmp-a2197-revA.dts | 3 ++- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 3 +-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 14 +++++------ arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 -- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 -- arch/arm/dts/zynqmp-zcu102-revA.dts | 12 ++-------- arch/arm/dts/zynqmp-zcu104-revA.dts | 20 ++++++++-------- arch/arm/dts/zynqmp-zcu104-revC.dts | 21 ++++++++--------- arch/arm/dts/zynqmp-zcu106-revA.dts | 23 ++----------------- arch/arm/dts/zynqmp-zcu111-revA.dts | 21 ++++++++--------- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- arch/arm/dts/zynqmp.dtsi | 10 +------- 21 files changed, 53 insertions(+), 100 deletions(-) -- 2.31.1

2 8

[PATCHv2] zynqmp: spl: support DRAM ECC initialization
by Jorge Ramirez-Ortiz 14 Jun '21

14 Jun '21

Use the ZDMA channel 0 to initialize the DRAM banks. This avoid spurious ECC errors that can occur when accessing unitialized memory. The feature is enabled by setting the option CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data: SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex) SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex) Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action. Signed-off-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> --- v2: extend commit message _BASE suffix for DRAM_BANK address DRAM_BANK2_BASE to 0x8.00.00.00.00 remove unnecessary includes from ecc_spl_init.c add ADMA_CH0_BASEADDR to hardware.h remove cache management timeout on loops retry once on DMA status error move DMA restore to reset values to its own function(*) removed extern clause from splc and added header file instead fixed duplicated call to board_early_init_r() (*) IP reset: there is no register to toggle (checked docs and linux kernel) opted for leaving the restore function as per FSBL arch/arm/mach-zynqmp/Kconfig | 35 ++++ arch/arm/mach-zynqmp/Makefile | 1 + arch/arm/mach-zynqmp/ecc_spl_init.c | 163 ++++++++++++++++++ .../mach-zynqmp/include/mach/ecc_spl_init.h | 13 ++ arch/arm/mach-zynqmp/include/mach/hardware.h | 2 + arch/arm/mach-zynqmp/spl.c | 4 + 6 files changed, 218 insertions(+) create mode 100644 arch/arm/mach-zynqmp/ecc_spl_init.c create mode 100644 arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index f1301f6661..39144d654e 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -92,6 +92,41 @@ config ZYNQMP_NO_DDR This option configures MMU with no DDR to avoid speculative access to DDR memory where DDR is not present. +config SPL_ZYNQMP_DRAM_ECC_INIT + bool "Initialize DRAM ECC" + depends on SPL + help + This option initializes all memory to 0xdeadbeef. Must be set if your + memory is of ECC type. + +config SPL_ZYNQMP_DRAM_BANK1_BASE + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank1 address" + default 0x00000000 + help + Start address of DRAM ECC bank1 + +config SPL_ZYNQMP_DRAM_BANK1_LEN + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank1 size" + default 0x80000000 + help + Size in bytes of the DRAM ECC bank1 + +config SPL_ZYNQMP_DRAM_BANK2_BASE + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank2 address" + default 0x800000000 + help + Start address of DRAM ECC bank2 + +config SPL_ZYNQMP_DRAM_BANK2_LEN + depends on SPL_ZYNQMP_DRAM_ECC_INIT + hex "DRAM Bank2 size" + default 0x0 + help + Size in bytes of the DRAM ECC bank2. A null size takes no action. + config SYS_MALLOC_F_LEN default 0x600 diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile index 8a3b074724..eb6c5112b3 100644 --- a/arch/arm/mach-zynqmp/Makefile +++ b/arch/arm/mach-zynqmp/Makefile @@ -7,4 +7,5 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o +obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o diff --git a/arch/arm/mach-zynqmp/ecc_spl_init.c b/arch/arm/mach-zynqmp/ecc_spl_init.c new file mode 100644 index 0000000000..f547d8e3a5 --- /dev/null +++ b/arch/arm/mach-zynqmp/ecc_spl_init.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2015 - 2020 Xilinx, Inc. + * + * Jorge Ramirez-Ortiz <jorge(a)foundries.io> + */ + +#include <common.h> +#include <cpu_func.h> +#include <asm/arch/hardware.h> +#include <asm/arch/ecc_spl_init.h> +#include <asm/io.h> +#include <linux/delay.h> + +#define ZDMA_TRANSFER_MAX_LEN (0x3FFFFFFFU - 7U) +#define ZDMA_CH_STATUS ((ADMA_CH0_BASEADDR) + 0x0000011CU) +#define ZDMA_CH_STATUS_STATE_MASK 0x00000003U +#define ZDMA_CH_STATUS_STATE_DONE 0x00000000U +#define ZDMA_CH_STATUS_STATE_ERR 0x00000003U +#define ZDMA_CH_CTRL0 ((ADMA_CH0_BASEADDR) + 0x00000110U) +#define ZDMA_CH_CTRL0_POINT_TYPE_MASK (u32)0x00000040U +#define ZDMA_CH_CTRL0_POINT_TYPE_NORMAL (u32)0x00000000U +#define ZDMA_CH_CTRL0_MODE_MASK (u32)0x00000030U +#define ZDMA_CH_CTRL0_MODE_WR_ONLY (u32)0x00000010U +#define ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT ((ADMA_CH0_BASEADDR) + 0x00000188U) +#define ZDMA_CH_WR_ONLY_WORD0 ((ADMA_CH0_BASEADDR) + 0x00000148U) +#define ZDMA_CH_WR_ONLY_WORD1 ((ADMA_CH0_BASEADDR) + 0x0000014CU) +#define ZDMA_CH_WR_ONLY_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000150U) +#define ZDMA_CH_WR_ONLY_WORD3 ((ADMA_CH0_BASEADDR) + 0x00000154U) +#define ZDMA_CH_DST_DSCR_WORD0 ((ADMA_CH0_BASEADDR) + 0x00000138U) +#define ZDMA_CH_DST_DSCR_WORD0_LSB_MASK 0xFFFFFFFFU +#define ZDMA_CH_DST_DSCR_WORD1 ((ADMA_CH0_BASEADDR) + 0x0000013CU) +#define ZDMA_CH_DST_DSCR_WORD1_MSB_MASK 0x0001FFFFU +#define ZDMA_CH_SRC_DSCR_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000130U) +#define ZDMA_CH_DST_DSCR_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000140U) +#define ZDMA_CH_CTRL2 ((ADMA_CH0_BASEADDR) + 0x00000200U) +#define ZDMA_CH_CTRL2_EN_MASK 0x00000001U +#define ZDMA_CH_ISR ((ADMA_CH0_BASEADDR) + 0x00000100U) +#define ZDMA_CH_ISR_DMA_DONE_MASK 0x00000400U +#define ECC_INIT_VAL_WORD 0xDEADBEEFU + +#define ZDMA_IDLE_TIMEOUT_USEC 1000000 +#define ZDMA_DONE_TIMEOUT_USEC 5000000 + +static void ecc_zdma_restore(void) +{ + /* Restore reset values for the DMA registers used */ + writel(ZDMA_CH_CTRL0, 0x00000080U); + writel(ZDMA_CH_WR_ONLY_WORD0, 0x00000000U); + writel(ZDMA_CH_WR_ONLY_WORD1, 0x00000000U); + writel(ZDMA_CH_WR_ONLY_WORD2, 0x00000000U); + writel(ZDMA_CH_WR_ONLY_WORD3, 0x00000000U); + writel(ZDMA_CH_DST_DSCR_WORD0, 0x00000000U); + writel(ZDMA_CH_DST_DSCR_WORD1, 0x00000000U); + writel(ZDMA_CH_SRC_DSCR_WORD2, 0x00000000U); + writel(ZDMA_CH_DST_DSCR_WORD2, 0x00000000U); + writel(ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT, 0x00000000U); +} + +static void ecc_dram_bank_init(u64 addr, u64 len) +{ + bool retry = true; + u32 timeout; + u64 bytes; + u32 size; + u64 src; + u32 reg; + + if (!len) + return; +retry: + bytes = len; + src = addr; + ecc_zdma_restore(); + while (bytes > 0) { + size = bytes > ZDMA_TRANSFER_MAX_LEN ? + ZDMA_TRANSFER_MAX_LEN : (u32)bytes; + + /* Wait until the DMA is in idle state */ + timeout = ZDMA_IDLE_TIMEOUT_USEC; + do { + udelay(1); + reg = readl(ZDMA_CH_STATUS); + reg &= ZDMA_CH_STATUS_STATE_MASK; + if (!timeout--) { + puts("error, ECC DMA failed to idle\n"); + goto done; + } + + } while ((reg != ZDMA_CH_STATUS_STATE_DONE) && + (reg != ZDMA_CH_STATUS_STATE_ERR)); + + /* Enable Simple (Write Only) Mode */ + reg = readl(ZDMA_CH_CTRL0); + reg &= (ZDMA_CH_CTRL0_POINT_TYPE_MASK | + ZDMA_CH_CTRL0_MODE_MASK); + reg |= (ZDMA_CH_CTRL0_POINT_TYPE_NORMAL | + ZDMA_CH_CTRL0_MODE_WR_ONLY); + writel(reg, ZDMA_CH_CTRL0); + + /* Fill in the data to be written */ + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD0); + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD1); + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD2); + writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD3); + + /* Write Destination Address */ + writel((u32)(src & ZDMA_CH_DST_DSCR_WORD0_LSB_MASK), + ZDMA_CH_DST_DSCR_WORD0); + writel((u32)((src >> 32) & ZDMA_CH_DST_DSCR_WORD1_MSB_MASK), + ZDMA_CH_DST_DSCR_WORD1); + + /* Size to be Transferred. Recommended to set both src and dest sizes */ + writel(size, ZDMA_CH_SRC_DSCR_WORD2); + writel(size, ZDMA_CH_DST_DSCR_WORD2); + + /* DMA Enable */ + reg = readl(ZDMA_CH_CTRL2); + reg |= ZDMA_CH_CTRL2_EN_MASK; + writel(reg, ZDMA_CH_CTRL2); + + /* Check the status of the transfer by polling on DMA Done */ + timeout = ZDMA_DONE_TIMEOUT_USEC; + do { + udelay(1); + reg = readl(ZDMA_CH_ISR); + reg &= ZDMA_CH_ISR_DMA_DONE_MASK; + if (!timeout--) { + puts("error, ECC DMA timeout\n"); + goto done; + } + } while (reg != ZDMA_CH_ISR_DMA_DONE_MASK); + + /* Clear DMA status */ + reg = readl(ZDMA_CH_ISR); + reg |= ZDMA_CH_ISR_DMA_DONE_MASK; + writel(ZDMA_CH_ISR_DMA_DONE_MASK, ZDMA_CH_ISR); + + /* Read the channel status for errors */ + reg = readl(ZDMA_CH_STATUS); + if (reg == ZDMA_CH_STATUS_STATE_ERR) { + if (retry) { + retry = false; + goto retry; + } + puts("error, ECC DMA error\n"); + break; + } + + bytes -= size; + src += size; + } +done: + ecc_zdma_restore(); +} + +void zynqmp_ecc_init(void) +{ + ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK1_BASE, + CONFIG_SPL_ZYNQMP_DRAM_BANK1_LEN); + ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK2_BASE, + CONFIG_SPL_ZYNQMP_DRAM_BANK2_LEN); +} diff --git a/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h b/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h new file mode 100644 index 0000000000..b4b6fcf53b --- /dev/null +++ b/arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2015 - 2020 Xilinx, Inc. + * + * Jorge Ramirez-Ortiz <jorge(a)foundries.io> + */ + +#ifndef __ARCH_ZYNQMP_ECC_INIT_H +#define __ARCH_ZYNQMP_ECC_INIT_H + +void zynqmp_ecc_init(void); + +#endif diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 3d3c48e247..fa612887a4 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -19,6 +19,8 @@ #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define ADMA_CH0_BASEADDR 0xFFA80000 + #define PS_MODE0 BIT(0) #define PS_MODE1 BIT(1) #define PS_MODE2 BIT(2) diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 88386b23e5..8fcae2c6a6 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -15,6 +15,7 @@ #include <asm/io.h> #include <asm/spl.h> #include <asm/arch/hardware.h> +#include <asm/arch/ecc_spl_init.h> #include <asm/arch/psu_init_gpl.h> #include <asm/arch/sys_proto.h> @@ -22,6 +23,9 @@ void board_init_f(ulong dummy) { board_early_init_f(); board_early_init_r(); +#ifdef CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT + zynqmp_ecc_init(); +#endif } static void ps_mode_reset(ulong mode) -- 2.31.1

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[PATCH] arm: snapdragon: Use correct GICC register on APQ8016
by Sheep Sun 14 Jun '21

14 Jun '21

The GICC register used by u-boot is 0x0a20c000, which is actually a GICC for WCNSS, the WLAN processor. U-boot runs on the Application Processor, therefore it should use APCS GICC instead. Hence, correct it with APCS GICC register address. Signed-off-by: Sheep Sun <sunxiaoyang2003(a)gmail.com> --- arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index 520e2e6bd7..d9a3b1af98 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -8,7 +8,7 @@ #define _MACH_SYSMAP_APQ8016_H #define GICD_BASE (0x0b000000) -#define GICC_BASE (0x0a20c000) +#define GICC_BASE (0x0b002000) /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) -- 2.30.2

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Reset cause register for Allwinner H3/R16 SOC's
by Suniel Mahesh 14 Jun '21

14 Jun '21

Hi All, I am working on an Allwinner R16 and H3 based targets and I am implementing system update. Is there any way(or a register) on Allwinner R16/H3 which can tell what is the cause of the reset(whether the reset is triggered by a watchdog or thermal or reset or a POR). Thanks & Regards -- Suniel Mahesh Embedded Linux and Kernel Engineer Amarula Solutions India

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[RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask
by Bin Meng 14 Jun '21

14 Jun '21

Current logic in riscv_get_ipi() for Andes PLICSW does not look good to me. The mask to test IPI pending bits for a hart should be left shifted by (8 * gd->arch.boot_hart), just the same as what is done in riscv_send_ipi(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- It looks there is no datasheet released from Andes that describes how PLICSW works, and its register fields. I can only get an understanding from current U-Boot and OpenSBI PLICSW driver. This requires testing on Andes hardware, which I don't have access to. arch/riscv/lib/andes_plic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 221a5fe324..5e113ee8c9 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { + unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); - *pending = !!(*pending & SEND_IPI_TO_HART(hart)); + *pending = !!(*pending & ipi); return 0; } -- 2.25.1

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