June 2021 - U-Boot

[PATCH V2] MAINTAINER, git-mailrc: Update the mmc maintainer
by Jaehoon Chung 15 Jun '21

15 Jun '21

Update to me as co-maintainer with Peng. Additionally, fix the alias in git-mailrc. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- Changelog on V2 - Keep original alias --- MAINTAINERS | 1 + doc/git-mailrc | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 86ff5e04a62b..a9257cde4df2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -882,6 +882,7 @@ F: arch/mips/dts/mrvl,cn73xx.dtsi MMC M: Peng Fan <peng.fan(a)nxp.com> +M: Jaehoon Chung <jh80.chung(a)samsung.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ diff --git a/doc/git-mailrc b/doc/git-mailrc index 34f936f4d83c..dc7b39b32faf 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -119,7 +119,7 @@ alias kerneldoc uboot, marex alias fdt uboot, sjg alias i2c uboot, hs alias kconfig uboot, masahiro -alias mmc uboot, freenix +alias mmc uboot, freenix, jaehoon alias nand uboot alias net uboot, jhersh alias phy uboot, jhersh -- 2.29.0

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[PATCH] net: use the same alias stem for ethernet as linux
by Michael Walle 14 Jun '21

14 Jun '21

Linux uses the prefix "ethernet" whereas u-boot uses "eth". This is from the linux tree: $ grep "eth[0-9].*=.*&" arch/**/*dts{,i}|wc -l 0 $ grep "ethernet[0-9].*=.*&" arch/**/*dts{,i}|wc -l 633 In u-boot device trees both prefixes are used. Until recently the only user of the ethernet alias was the sandbox test device tree. This changed with commit fc054d563bfb ("net: Introduce DSA class for Ethernet switches"). There, the MAC addresses are inherited based on the devices sequence IDs which is in turn given by the device tree. Before there are more users in u-boot and both worlds will differ even more, rename the alias prefix to "ethernet" to match the linux ones. Also adapt the test cases and rename any old aliases in the u-boot device trees. Cc: David Wu <david.wu(a)rock-chips.com> Signed-off-by: Michael Walle <michael(a)walle.cc> --- Vladimir, I didn't do another patch to rename any ethernet aliases to "eth". Though kontron boards contain "ethernetN" aliases, all in tree variants don't make use of it. So there is nothing to be fixed. arch/arm/dts/fsl-ls1028a-rdb.dts | 12 ++++++------ arch/sandbox/dts/test.dts | 10 +++++----- net/eth-uclass.c | 4 ++-- test/dm/ofnode.c | 2 +- test/dm/test-fdt.c | 2 +- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 3432fca352..82a8c0a0cd 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -15,12 +15,12 @@ compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; aliases { spi0 = &fspi; - eth0 = &enetc0; - eth1 = &enetc2; - eth2 = &mscc_felix_port0; - eth3 = &mscc_felix_port1; - eth4 = &mscc_felix_port2; - eth5 = &mscc_felix_port3; + ethernet0 = &enetc0; + ethernet1 = &enetc2; + ethernet2 = &mscc_felix_port0; + ethernet3 = &mscc_felix_port1; + ethernet4 = &mscc_felix_port2; + ethernet5 = &mscc_felix_port3; }; }; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 3ef3ba0b17..7a5d4aa71d 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -14,11 +14,11 @@ aliases { console = &uart0; - eth0 = "/eth@10002000"; - eth2 = &swp_0; - eth3 = &eth_3; - eth4 = &dsa_eth0; - eth5 = &eth_5; + ethernet0 = "/eth@10002000"; + ethernet2 = &swp_0; + ethernet3 = &eth_3; + ethernet4 = &dsa_eth0; + ethernet5 = &eth_5; gpio1 = &gpio_a; gpio2 = &gpio_b; gpio3 = &gpio_c; diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 0b4260dc5b..5146bd6666 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -605,8 +605,8 @@ static int eth_pre_remove(struct udevice *dev) return 0; } -UCLASS_DRIVER(eth) = { - .name = "eth", +UCLASS_DRIVER(ethernet) = { + .name = "ethernet", .id = UCLASS_ETH, .post_bind = eth_post_bind, .pre_unbind = eth_pre_unbind, diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index c539134296..3b708b63eb 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -213,7 +213,7 @@ static int dm_test_ofnode_read_aliases(struct unit_test_state *uts) ofnode node; int size; - node = ofnode_get_aliases_node("eth3"); + node = ofnode_get_aliases_node("ethernet3"); ut_assert(ofnode_valid(node)); ut_asserteq_str("sbe5", ofnode_get_name(node)); diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 6e83aeecd9..98972665f2 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -183,7 +183,7 @@ static int dm_test_alias_highest_id(struct unit_test_state *uts) { int ret; - ret = dev_read_alias_highest_id("eth"); + ret = dev_read_alias_highest_id("ethernet"); ut_asserteq(5, ret); ret = dev_read_alias_highest_id("gpio"); -- 2.20.1

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[PATCH] net: use a more deterministic approach to get the active ethernet device
by Michael Walle 14 Jun '21

14 Jun '21

If the environment variable "ethact" is not set, the first device in the uclass is returned. This depends on the probing order of the ethernet devices. Moreover it is not not configurable at all. Try to return the ethernet device with sequence id 0 first which then can be configured by the aliases in a device tree. Fall back to the old mechanism in case of an error. Signed-off-by: Michael Walle <michael(a)walle.cc> --- net/eth-uclass.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 34ca731d1e..0b4260dc5b 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -69,8 +69,11 @@ void eth_set_current_to_next(void) /* * Typically this will simply return the active device. * In the case where the most recent active device was unset, this will attempt - * to return the first device. If that device doesn't exist or fails to probe, - * this function will return NULL. + * to return the device with sequence id 0 (which can be configured by the + * device tree). If this fails, fall back to just getting the first device. + * The latter is non-deterministic and depends on the order of the probing. + * If that device doesn't exist or fails to probe, this function will return + * NULL. */ struct udevice *eth_get_dev(void) { @@ -80,9 +83,13 @@ struct udevice *eth_get_dev(void) if (!uc_priv) return NULL; - if (!uc_priv->current) - eth_errno = uclass_first_device(UCLASS_ETH, - &uc_priv->current); + if (!uc_priv->current) { + eth_errno = uclass_get_device_by_seq(UCLASS_ETH, 0, + &uc_priv->current); + if (eth_errno) + eth_errno = uclass_first_device(UCLASS_ETH, + &uc_priv->current); + } return uc_priv->current; } -- 2.20.1

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[RESEND PATCH v6 2/2] mmc: openpiton: add piton_mmc driver
by Tianrui Wei 14 Jun '21

14 Jun '21

This commit adds support to piton_mmc driver for OpenPiton-riscv64 In particular, this driver - V6 . change type of address . move declarations ahead . loop style update Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com> Signed-off-by: Jonathan Balkind <jbalkind(a)ucsb.edu> --- drivers/mmc/Kconfig | 9 +++ drivers/mmc/Makefile | 1 + drivers/mmc/piton_mmc.c | 169 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 drivers/mmc/piton_mmc.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 8901456967..096d6a930c 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -727,6 +727,15 @@ config MMC_SUNXI_HAS_MODE_SWITCH bool depends on MMC_SUNXI +config MMC_PITON + bool "MMC support for OpenPiton SoC" + depends on DM_MMC && BLK + help + This selects support for the SD host controller on + OpenPiton SoC. Note that this SD controller directly + exposes the contents of the SD card as memory mapped, + so there is no manual configuration required + config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" depends on DM_MMC && BLK && ARCH_AT91 diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 89d6af3db3..cc08b41d0d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o +obj-$(CONFIG_MMC_PITON) += piton_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c new file mode 100644 index 0000000000..32671d1a89 --- /dev/null +++ b/drivers/mmc/piton_mmc.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Jaehoon Chung <jh80.chung(a)samsung.com> + * Portions Copyright 2011-2019 NVIDIA Corporation + * Portions Copyright 2021 Tianrui Wei + * This file is adapted from tegra_mmc.c + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#include <asm/gpio.h> +#include <asm/io.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/types.h> +#include <log.h> +#include <mmc.h> + +struct piton_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct piton_mmc_priv { + void __iomem *piton_mmc_base_addr; /* peripheral id */ +}; + +/* + * see mmc_read_blocks to see how it is used. + * start block is hidden at cmd->arg + * also, initialize the block size at init + */ +static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + /* check first if this is a pure command */ + if (!data) + return 0; + + struct piton_mmc_priv *priv = dev_get_priv(dev); + u32 *buff, *start_addr; + size_t byte_cnt, start_block; + + buff = (u32 *)data->dest; + start_block = cmd->cmdarg; + start_addr = priv->piton_mmc_base_addr + start_block; + + /* if there is a read */ + if (data->flags & MMC_DATA_READ) { + for (byte_cnt = data->blocks * data->blocksize; byte_cnt; + byte_cnt -= sizeof(u32)) { + *buff++ = readl(start_addr++); + } + } else { + return -ENOSYS; + } + + return 0; +} + +static int piton_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct piton_mmc_priv *priv = dev_get_priv(dev); + struct piton_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg; + struct mmc *mmc; + /* fill in device description */ + struct blk_desc *bdesc; + + priv->piton_mmc_base_addr = (void *)dev_read_addr(dev); + cfg = &plat->cfg; + cfg->name = "PITON MMC"; + cfg->host_caps = MMC_MODE_8BIT; + cfg->f_max = 100000; + cfg->f_min = 400000; + cfg->voltages = MMC_VDD_21_22; + + mmc = &plat->mmc; + mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + mmc->capacity_user = 0x100000000; + mmc->capacity_user *= mmc->read_bl_len; + mmc->capacity_boot = 0; + mmc->capacity_rpmb = 0; + for (int i = 0; i < 4; i++) + mmc->capacity_gp[i] = 0; + mmc->capacity = 0x2000000000ULL; + mmc->has_init = 1; + + bdesc = mmc_get_blk_desc(mmc); + bdesc->lun = 0; + bdesc->hwpart = 0; + bdesc->type = 0; + bdesc->blksz = mmc->read_bl_len; + bdesc->log2blksz = LOG2(bdesc->blksz); + bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); + + return 0; +} + +/* test if the micro sd card is present + * always return 1, which means present + */ +static int piton_mmc_getcd(struct udevice *dev) +{ + /* + * always return 1 + */ + return 1; +} + +/* dummy function, piton_mmc don't need initialization + * in hw + */ +static const struct dm_mmc_ops piton_mmc_ops = { + .send_cmd = piton_mmc_send_cmd, + .get_cd = piton_mmc_getcd, +}; + +static int piton_mmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct piton_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + upriv->mmc = &plat->mmc; + upriv->mmc->has_init = 1; + upriv->mmc->capacity = 0x2000000000ULL; + upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + return 0; +} + +static int piton_mmc_bind(struct udevice *dev) +{ + struct piton_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT; + cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->f_min = 1000000; + cfg->f_max = 52000000; + cfg->b_max = U32_MAX; + + return mmc_bind(dev, &plat->mmc, cfg); +} + +static const struct udevice_id piton_mmc_ids[] = { + {.compatible = "openpiton,piton-mmc"}, + {/* sentinel */} +}; + +U_BOOT_DRIVER(piton_mmc_drv) = { + .name = "piton_mmc", + .id = UCLASS_MMC, + .of_match = piton_mmc_ids, + .ofdata_to_platdata = piton_mmc_ofdata_to_platdata, + .bind = piton_mmc_bind, + .probe = piton_mmc_probe, + .ops = &piton_mmc_ops, + .platdata_auto_alloc_size = sizeof(struct piton_mmc_plat), + .priv_auto_alloc_size = sizeof(struct piton_mmc_priv), +}; -- 2.32.0

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[PATCH v7 2/2] mmc: openpiton: add piton_mmc driver
by Tianrui Wei 14 Jun '21

14 Jun '21

This commit adds support to piton_mmc driver for OpenPiton-riscv64 In particular, this driver - V6 . change type of address . move declarations ahead . loop style update - V7 . dm updates . fix indentations Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com> Signed-off-by: Jonathan Balkind <jbalkind(a)ucsb.edu> --- drivers/mmc/Kconfig | 9 ++ drivers/mmc/Makefile | 1 + drivers/mmc/piton_mmc.c | 181 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 drivers/mmc/piton_mmc.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 8901456967..4948e194e7 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -727,6 +727,15 @@ config MMC_SUNXI_HAS_MODE_SWITCH bool depends on MMC_SUNXI +config MMC_PITON + bool "MMC support for OpenPiton SoC" + depends on DM_MMC && BLK + help + This selects support for the SD host controller on OpenPiton SoC. + Note that this SD controller directly exposes the contents of the + SD card as memory mapped, so there is no manual configuration + required + config GENERIC_ATMEL_MCI bool "Atmel Multimedia Card Interface support" depends on DM_MMC && BLK && ARCH_AT91 diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 89d6af3db3..d96ac90719 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o +obj-$(CONFIG_MMC_PITON) += piton_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c new file mode 100644 index 0000000000..8517ec8410 --- /dev/null +++ b/drivers/mmc/piton_mmc.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * Jaehoon Chung <jh80.chung(a)samsung.com> + * Portions Copyright 2011-2019 NVIDIA Corporation + * Portions Copyright 2021 Tianrui Wei + * This file is adapted from tegra_mmc.c + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#include <asm/gpio.h> +#include <asm/io.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <errno.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/types.h> +#include <linux/sizes.h> +#include <log.h> +#include <mmc.h> + + +#define PITON_MMC_DUMMY_F_MAX 20000000 +#define PITON_MMC_DUMMY_F_MIN 10000000 +#define PITON_MMC_DUMMY_CAPACITY SZ_4G << 3 +#define PITON_MMC_DUMMY_B_MAX SZ_4G + +struct piton_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct piton_mmc_priv { + void __iomem *piton_mmc_base_addr; /* peripheral id */ +}; + +/* + * see mmc_read_blocks to see how it is used. + * start block is hidden at cmd->arg + * also, initialize the block size at init + */ +static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + /* check first if this is a pure command */ + if (!data) + return 0; + + struct piton_mmc_priv *priv = dev_get_priv(dev); + u32 *buff, *start_addr, *write_src; + size_t byte_cnt, start_block; + + buff = (u32 *)data->dest; + write_src = (u32 *)data->src; + start_block = cmd->cmdarg; + start_addr = priv->piton_mmc_base_addr + start_block; + + /* if there is a read */ + if (data->flags & MMC_DATA_READ) { + for (byte_cnt = data->blocks * data->blocksize; byte_cnt; + byte_cnt -= sizeof(u32)) { + *buff++ = readl(start_addr++); + } + } else { + for (byte_cnt = data->blocks * data->blocksize; byte_cnt; + byte_cnt -= sizeof(u32)) { + writel(*write_src++,start_addr++); + } + + } + + return 0; +} + +static int piton_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct piton_mmc_priv *priv = dev_get_priv(dev); + struct piton_mmc_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg; + struct mmc *mmc; + /* fill in device description */ + struct blk_desc *bdesc; + + priv->piton_mmc_base_addr = (void *)dev_read_addr(dev); + cfg = &plat->cfg; + cfg->name = "PITON MMC"; + cfg->host_caps = MMC_MODE_8BIT; + cfg->f_max = PITON_MMC_DUMMY_F_MAX; + cfg->f_min = PITON_MMC_DUMMY_F_MIN; + cfg->voltages = MMC_VDD_21_22; + + mmc = &plat->mmc; + mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + mmc->capacity_user = PITON_MMC_DUMMY_CAPACITY; + mmc->capacity_user *= mmc->read_bl_len; + mmc->capacity_boot = 0; + mmc->capacity_rpmb = 0; + for (int i = 0; i < 4; i++) + mmc->capacity_gp[i] = 0; + mmc->capacity = PITON_MMC_DUMMY_CAPACITY; + mmc->has_init = 1; + + bdesc = mmc_get_blk_desc(mmc); + bdesc->lun = 0; + bdesc->hwpart = 0; + bdesc->type = 0; + bdesc->blksz = mmc->read_bl_len; + bdesc->log2blksz = LOG2(bdesc->blksz); + bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); + + return 0; +} + +/* test if the micro sd card is present + * always return 1, which means present + */ +static int piton_mmc_getcd(struct udevice *dev) +{ + /* + * always return 1 + */ + return 1; +} + +/* dummy function, piton_mmc don't need initialization + * in hw + */ +static const struct dm_mmc_ops piton_mmc_ops = { + .send_cmd = piton_mmc_send_cmd, + .get_cd = piton_mmc_getcd, +}; + +static int piton_mmc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct piton_mmc_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + upriv->mmc = &plat->mmc; + upriv->mmc->has_init = 1; + upriv->mmc->capacity = PITON_MMC_DUMMY_CAPACITY; + upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN; + return 0; +} + +static int piton_mmc_bind(struct udevice *dev) +{ + struct piton_mmc_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + + cfg->name = dev->name; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT; + cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->f_min = PITON_MMC_DUMMY_F_MIN; + cfg->f_max = PITON_MMC_DUMMY_F_MAX; + cfg->b_max = MMC_MAX_BLOCK_LEN; + + return mmc_bind(dev, &plat->mmc, cfg); +} + +static const struct udevice_id piton_mmc_ids[] = { + {.compatible = "openpiton,piton-mmc"}, + {/* sentinel */} +}; + +U_BOOT_DRIVER(piton_mmc_drv) = { + .name = "piton_mmc", + .id = UCLASS_MMC, + .of_match = piton_mmc_ids, + .of_to_plat = piton_mmc_ofdata_to_platdata, + .bind = piton_mmc_bind, + .probe = piton_mmc_probe, + .ops = &piton_mmc_ops, + .plat_auto = sizeof(struct piton_mmc_plat), + .priv_auto = sizeof(struct piton_mmc_priv), +}; -- 2.32.0

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[PATCH v7 1/2] board: riscv: add openpiton-riscv64 SoC support
by Tianrui Wei 14 Jun '21

14 Jun '21

This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper - V6 . separate defconfigs for u-boot and SPL . eliminate debug console output . style updates - V7 . update Kconfig for OpenPiton board . SPL defconfig update Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com> Signed-off-by: Jonathan Balkind <jbalkind(a)ucsb.edu> --- arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/openpiton-riscv64.dts | 153 ++++++++ board/openpiton/riscv64/Kconfig | 40 +++ board/openpiton/riscv64/MAINTAINERS | 8 + board/openpiton/riscv64/Makefile | 5 + board/openpiton/riscv64/openpiton-riscv64.c | 33 ++ configs/openpiton_riscv64_defconfig | 76 ++++ configs/openpiton_riscv64_spl_defconfig | 87 +++++ doc/board/index.rst | 1 + doc/board/openpiton/index.rst | 9 + doc/board/openpiton/riscv64.rst | 376 ++++++++++++++++++++ include/configs/openpiton-riscv64.h | 61 ++++ 13 files changed, 854 insertions(+) create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 board/openpiton/riscv64/Kconfig create mode 100644 board/openpiton/riscv64/MAINTAINERS create mode 100644 board/openpiton/riscv64/Makefile create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 configs/openpiton_riscv64_spl_defconfig create mode 100644 doc/board/openpiton/index.rst create mode 100644 doc/board/openpiton/riscv64.rst create mode 100644 include/configs/openpiton-riscv64.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b3d7fd84ce..4b0c3dffa6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" +config TARGET_OPENPITON_RISCV64 + bool "Support RISC-V cores on OpenPiton SoC" + endchoice config SYS_ICACHE_OFF @@ -60,6 +63,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 7778874831..b6e9166767 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb +dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts new file mode 100644 index 0000000000..45951e1236 --- /dev/null +++ b/arch/riscv/dts/openpiton-riscv64.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 Tianrui Wei <tianrui-wei(a)outlook.com> */ + +/* + * This dts is for a dual core instance of OpenPiton+Ariane built + * to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files + * are automatically generated by the OpenPiton build system and + * this configuration may not be what you need if your configuration + * is different from the below. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "openpiton,riscv64"; + + chosen { + stdout-path = "uart0:115200"; + }; + + aliases { + console = &uart0; + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <520835>; + + CPU0: cpu@0 { + clocks = <&clk0>; + u-boot,dm-spl; + device_type = "cpu"; + reg = <0>; + compatible = "openhwgroup,cva6", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + clocks = <&clk0>; + device_type = "cpu"; + reg = <1>; + compatible = "openhwgroup,cva6", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + }; + + clocks { + clk0: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <66667000>; + }; + }; + + memory@80000000 { + u-boot,dm-spl; + device_type = "memory"; + reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "openpiton,chipset", "simple-bus"; + ranges; + + uart0: uart@fff0c2c000 { + compatible = "ns16550", "openpiton,ns16550"; + reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <0>; + // regs are spaced on 8 bit boundary + }; + + eth: ethernet@fff0d00000 { + compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet"; + device_type = "network"; + reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >; + interrupt-parent = <&PLIC0>; + interrupts = <2>; + phy-handle = <&phy0>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x1>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + axi_ethernetlite_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = "ethernet-phy-id001C.C915"; + device_type = "ethernet-phy"; + reg = <1>; + }; + }; + }; + + sdhci_0: sdhci@f000000000 { + u-boot,dm-spl; + compatible = "openpiton,piton-mmc", "openpiton,mmc"; + reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >; + }; + + clint@fff1020000 { + compatible = "sifive,clint0", "openpiton,clint"; + interrupts-extended = < &CPU0_intc 3 + &CPU0_intc 7 + &CPU1_intc 3 + &CPU1_intc 7 >; + reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >; + clocks = <&clk0>; + }; + + PLIC0: plic@fff1100000 { + u-boot,dm-spl; + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0", "openpiton,plic"; + interrupt-controller; + interrupts-extended = < &CPU0_intc 11 + &CPU0_intc 9 + &CPU1_intc 11 + &CPU1_intc 9 >; + reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >; + riscv,max-priority = <7>; + riscv,ndev = <2>; + }; + }; +}; diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig new file mode 100644 index 0000000000..193c890046 --- /dev/null +++ b/board/openpiton/riscv64/Kconfig @@ -0,0 +1,40 @@ +if TARGET_OPENPITON_RISCV64 + +config SYS_BOARD + default "riscv64" + +config SYS_VENDOR + default "openpiton" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "openpiton-riscv64" + +config SYS_TEXT_BASE + default 0x81000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x81000000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x82000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU_RISCV + imply RISCV_TIMER + imply SPL_SIFIVE_CLINT + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_SMP + imply SPL_MMC + imply SMP + imply SPL_RISCV_MMODE + +endif diff --git a/board/openpiton/riscv64/MAINTAINERS b/board/openpiton/riscv64/MAINTAINERS new file mode 100644 index 0000000000..f91c000c83 --- /dev/null +++ b/board/openpiton/riscv64/MAINTAINERS @@ -0,0 +1,8 @@ +Openpiton BOARD +M: Tianrui Wei<tianrui-wei(a)outlook.com> +S: Maintained +F: board/openpiton/riscv64/ +F: include/configs/openpiton-riscv64.h +F: configs/openpiton_riscv64_defconfig +F: configs/openpiton_riscv64_spl_defconfig +F: drivers/mmc/piton_mmc.c diff --git a/board/openpiton/riscv64/Makefile b/board/openpiton/riscv64/Makefile new file mode 100644 index 0000000000..3bffa75a9a --- /dev/null +++ b/board/openpiton/riscv64/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Tianrui Wei +# Tianrui Wei <tianrui-wei(a)outlook.com> +obj-y += openpiton-riscv64.o diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c new file mode 100644 index 0000000000..f2282d1548 --- /dev/null +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * Copyright (c) 2021 Tianrui Wei + * + * + * Authors: + * Pragnesh Patel <pragnesh.patel(a)sifive.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ +#include <common.h> +#include <init.h> +#include <configs/openpiton-riscv64.h> +#include <dm.h> +#include <spl.h> + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { + BOOT_DEVICE_MMC1, + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +int board_init(void) +{ + return 0; +} diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig new file mode 100644 index 0000000000..cd66db2fe5 --- /dev/null +++ b/configs/openpiton_riscv64_defconfig @@ -0,0 +1,76 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +CONFIG_TARGET_OPENPITON_RISCV64=y +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +CONFIG_OF_BOARD_FIXUP=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_ENV_VARS_UBOOT_CONFIG=y +# CONFIG_EXPERT is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_PROMPT="openpiton$ " +# CONFIG_CMD_CPU is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_DATE is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set +CONFIG_OF_EMBED=y +# CONFIG_NET is not set +CONFIG_CPU=y +CONFIG_MMC=y +# CONFIG_MMC_WRITE is not set +# CONFIG_MMC_HW_PARTITIONING is not set +# CONFIG_MMC_VERBOSE is not set +CONFIG_MMC_PITON=y +CONFIG_RAM=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_FS_SQUASHFS=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_MD5=y +CONFIG_GETOPT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SPL_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig new file mode 100644 index 0000000000..16195be0d8 --- /dev/null +++ b/configs/openpiton_riscv64_spl_defconfig @@ -0,0 +1,87 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_PAYLOAD="" +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +CONFIG_TARGET_OPENPITON_RISCV64=y +CONFIG_NR_CPUS=32 +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_ENV_VARS_UBOOT_CONFIG=y +# CONFIG_EXPERT is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_SPL_BANNER_PRINT is not set +CONFIG_SPL_CPU=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SYS_PROMPT="openpiton$ " +# CONFIG_CMD_CPU is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_DATE is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +# CONFIG_NET is not set +CONFIG_CPU=y +CONFIG_MMC=y +# CONFIG_MMC_WRITE is not set +# CONFIG_MMC_HW_PARTITIONING is not set +# CONFIG_MMC_VERBOSE is not set +CONFIG_MMC_PITON=y +CONFIG_RAM=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_FS_SQUASHFS=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_MD5=y +CONFIG_GETOPT=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/index.rst b/doc/board/index.rst index a70d2de19d..6b1e246217 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -18,6 +18,7 @@ Board-specific doc intel/index kontron/index microchip/index + openpiton/index rockchip/index sifive/index sipeed/index diff --git a/doc/board/openpiton/index.rst b/doc/board/openpiton/index.rst new file mode 100644 index 0000000000..c469102c4b --- /dev/null +++ b/doc/board/openpiton/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +OpenPiton +========= + +.. toctree:: + :maxdepth: 2 + + riscv64 diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst new file mode 100644 index 0000000000..ed7d59db2c --- /dev/null +++ b/doc/board/openpiton/riscv64.rst @@ -0,0 +1,376 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Openpiton RISC-V SoC +==================== + +OpenPiton RISC-V SoC +-------------------- +OpenPiton is an open source, manycore processor and research platform. It is a +tiled manycore framework scalable from one to 1/2 billion cores. It supports a +number of ISAs including RISC-V with its P-Mesh cache coherence protocol and +networks on chip. It is highly configurable in both core and uncore components. +OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes +running full-stack Debian linux. + +RISCV-V Standard Bootflow +------------------------- +Currently, OpenPiton implements RISC-V standard bootflow in the following steps +mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux +This board supports S-mode u-boot as well as M-mode SPL + +Building OpenPition +--------------------- +If you'd like to build OpenPiton, please go to OpenPiton github repo +(at https://github.com/PrincetonUniversity/openpiton) to build from the latest +changes + +Building Images +--------------------------- + +SPL +--- + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + export ARCH=riscv + +3. make openpiton_riscv64_spl_defconfig +4. make + +U-Boot +------ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + export ARCH=riscv + +3. make openpiton_riscv64_defconfig +4. make + + +opensbi +------- + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + export ARCH=riscv + +3. Go to OpenSBI directory +4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin> + + +Using fw_payload.bin with linux +------------------------------- +Put the generated fw_payload.bin into the /boot directory on the root filesystem, +plug in the SD card, then flash the bitstream. Linux will boot automatically. + +Booting +------- +Once you plugin the sdcard and power up, you should see the U-Boot prompt. + +Sample Dual-core Debian boot log from OpenPiton +----------------------------------------------- + +.. code-block:: none + + Trying to boot from MMC1 + + OpenSBI v0.9-5-gd06cb61 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + + Platform Name : OPENPITON RISC-V + Platform Features : timer,mfdeleg + Platform HART Count : 3 + Firmware Base : 0x80000000 + Firmware Size : 104 KB + Runtime SBI Version : 0.2 + + Domain0 Name : root + Domain0 Boot HART : 0 + Domain0 HARTs : 0*,1*,2* + Domain0 Region00 : 0x0000000080000000-0x000000008001ffff () + Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X) + Domain0 Next Address : 0x0000000080200000 + Domain0 Next Arg1 : 0x0000000082200000 + Domain0 Next Mode : S-mode + Domain0 SysReset : yes + + Boot HART ID : 0 + Boot HART Domain : root + Boot HART ISA : rv64imafdcsu + Boot HART Features : scounteren,mcounteren + Boot HART PMP Count : 0 + Boot HART PMP Granularity : 0 + Boot HART PMP Address Bits: 0 + Boot HART MHPM Count : 0 + Boot HART MHPM Count : 0 + Boot HART MIDELEG : 0x0000000000000222 + Boot HART MEDELEG : 0x000000000000b109 + + + U-Boot 2021.01+ (Jun 12 2021 - 10:31:34 +0800) + + DRAM: 1 GiB + MMC: sdhci@f000000000: 0 (eMMC) + In: uart@fff0c2c000 + Out: uart@fff0c2c000 + Err: uart@fff0c2c000 + Hit any key to stop autoboot: 0 + 6492992 bytes read in 5310 ms (1.2 MiB/s) + ## Flattened Device Tree blob at 86000000 + Booting using the fdt blob at 0x86000000 + Loading Device Tree to 00000000bfffa000, end 00000000bffff007 ... OK + + Starting kernel ... + + [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 + [ 0.000000] Linux version 5.6.0-rc4-gb9d34f7e294d-dirty + [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') + [ 0.000000] printk: bootconsole [sbi0] enabled + [ 0.000000] Zone ranges: + [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Normal empty + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] On node 0 totalpages: 261632 + [ 0.000000] DMA32 zone: 4088 pages used for memmap + [ 0.000000] DMA32 zone: 0 pages reserved + [ 0.000000] DMA32 zone: 261632 pages, LIFO batch:63 + [ 0.000000] software IO TLB: mapped [mem 0xbaffa000-0xbeffa000] (64MB) + [ 0.000000] SBI specification v0.2 detected + [ 0.000000] SBI implementation ID=0x1 Version=0x9 + [ 0.000000] SBI v0.2 TIME extension detected + [ 0.000000] SBI v0.2 IPI extension detected + [ 0.000000] SBI v0.2 RFENCE extension detected + [ 0.000000] SBI v0.2 HSM extension detected + [ 0.000000] elf_hwcap is 0x112d + [ 0.000000] percpu: Embedded 16 pages/cpu s25368 r8192 d31976 u65536 + [ 0.000000] pcpu-alloc: s25368 r8192 d31976 u65536 alloc=16*4096 + [ 0.000000] pcpu-alloc: [0] 0 + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 257544 + [ 0.000000] Kernel command line: earlycon=sbi root=/dev/piton_sd1 + [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) + [ 0.000000] Sorting __ex_table... + [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off + [ 0.000000] Memory: 956252K/1046528K available (4357K kernel code, 286K rwdata, 1200K rodata, 168K init, 311K bss, 90276K re) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 + [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 + [ 0.000000] plic: mapped 2 interrupts with 1 handlers for 2 contexts. + [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] + [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1ec037a6a, max_idle_ns: 7052723236599 ns + [ 0.000138] sched_clock: 64 bits at 520kHz, resolution 1919ns, wraps every 4398046510738ns + [ 0.009429] printk: console [hvc0] enabled + [ 0.009429] printk: console [hvc0] enabled + [ 0.017850] printk: bootconsole [sbi0] disabled + [ 0.017850] printk: bootconsole [sbi0] disabled + [ 0.028029] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.04 BogoMIPS (lpj=5208) + [ 0.038753] pid_max: default: 32768 minimum: 301 + [ 0.050248] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.058661] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.069359] *** VALIDATE tmpfs *** + [ 0.089093] *** VALIDATE proc *** + [ 0.101135] *** VALIDATE cgroup *** + [ 0.105019] *** VALIDATE cgroup2 *** + [ 0.144310] rcu: Hierarchical SRCU implementation. + [ 0.162836] smp: Bringing up secondary CPUs ... + [ 0.167736] smp: Brought up 1 node, 1 CPU + [ 0.185982] devtmpfs: initialized + [ 0.216237] random: get_random_u32 called from bucket_table_alloc.isra.25+0x4e/0x15c with crng_init=0 + [ 0.236026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + [ 0.246916] futex hash table entries: 256 (order: 2, 16384 bytes, linear) + [ 0.266994] NET: Registered protocol family 16 + [ 0.763362] clocksource: Switched to clocksource riscv_clocksource + [ 0.770122] *** VALIDATE bpf *** + [ 0.782837] *** VALIDATE ramfs *** + [ 0.829997] NET: Registered protocol family 2 + [ 0.853577] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) + [ 0.864085] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.875373] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) + [ 0.887958] TCP: Hash tables configured (established 8192 bind 8192) + [ 0.902149] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.909904] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.924809] NET: Registered protocol family 1 + [ 0.948605] RPC: Registered named UNIX socket transport module. + [ 0.956003] RPC: Registered udp transport module. + [ 0.961565] RPC: Registered tcp transport module. + [ 0.966432] RPC: Registered tcp NFSv4.1 backchannel transport module. + [ 0.987180] Initialise system trusted keyrings + [ 0.998953] workingset: timestamp_bits=46 max_order=18 bucket_order=0 + [ 1.323977] *** VALIDATE nfs *** + [ 1.328520] *** VALIDATE nfs4 *** + [ 1.334422] NFS: Registering the id_resolver key type + [ 1.340148] Key type id_resolver registered + [ 1.345280] Key type id_legacy registered + [ 1.349820] nfs4filelayout_init: NFSv4 File Layout Driver Registering... + [ 1.357610] Installing knfsd (copyright (C) 1996 okir(a)monad.swb.de). + [ 1.866909] Key type asymmetric registered + [ 1.872460] Asymmetric key parser 'x509' registered + [ 1.878750] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) + [ 1.887480] io scheduler mq-deadline registered + [ 1.892864] io scheduler kyber registered + [ 3.905595] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 3.954332] fff0c2c000.uart: ttyS0 at MMIO 0xfff0c2c000 (irq = 1, base_baud = 4166687) is a 16550 + [ 4.254794] loop: module loaded + [ 4.258269] piton_sd:v1.0 Apr 26, 2019 + [ 4.258269] + [ 4.265170] gpt partition table header: + [ 4.265283] signature: 5452415020494645 + [ 4.269258] revision: 10000 + [ 4.273746] size: 5c + [ 4.276659] crc_header: 26b42404 + [ 4.278911] reserved: 0 + [ 4.282730] current lba: 1 + [ 4.285311] backup lda: 3b723ff + [ 4.288093] partition entries lba: 2 + [ 4.291835] number partition entries: 80 + [ 4.295529] size partition entries: 80 + [ 9.473253] piton_sd: piton_sd1 + [ 10.099676] libphy: Fixed MDIO Bus: probed + [ 10.148782] NET: Registered protocol family 10 + [ 10.183418] Segment Routing with IPv6 + [ 10.189384] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + [ 10.214449] NET: Registered protocol family 17 + [ 10.227413] Key type dns_resolver registered + [ 10.240561] Loading compiled-in X.509 certificates + [ 10.465264] EXT4-fs (piton_sd1): mounted filesystem with ordered data mode. Opts: (null) + [ 10.475922] VFS: Mounted root (ext4 filesystem) readonly on device 254:1. + [ 10.551865] devtmpfs: mounted + [ 10.562744] Freeing unused kernel memory: 168K + [ 10.567450] This architecture does not have kernel memory protection. + [ 10.574688] Run /sbin/init as init process + [ 10.578916] with arguments: + [ 10.582489] /sbin/init + [ 10.585312] with environment: + [ 10.588518] HOME=/ + [ 10.591459] TERM=linux + [ 18.154373] systemd[1]: System time before build time, advancing clock. + [ 18.565415] systemd[1]: systemd 238 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIB) + [ 18.596359] systemd[1]: Detected architecture riscv64. + + Welcome to Debian GNU/Linux buster/sid! + + [ 18.797150] systemd[1]: Set hostname to <openpiton>. + [ 31.609244] random: systemd: uninitialized urandom read (16 bytes read) + [ 31.630366] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe. + [ OK ] Listening on /dev/initctl Compatibility Named Pipe. + [ 31.674820] random: systemd: uninitialized urandom read (16 bytes read) + [ 31.806800] systemd[1]: Created slice system-serial\x2dgetty.slice. + [ OK ] Created slice system-serial\x2dgetty.slice. + [ 31.839855] random: systemd: uninitialized urandom read (16 bytes read) + [ 31.850670] systemd[1]: Reached target Slices. + [ OK ] Reached target Slices. + [ 32.128005] systemd[1]: Reached target Swap. + [ OK ] Reached target Swap. + [ 32.180337] systemd[1]: Listening on Journal Socket. + [ OK ] Listening on Journal Socket. + [ 32.416448] systemd[1]: Mounting Kernel Debug File System... + Mounting Kernel Debug File System... + [ 32.937934] systemd[1]: Starting Remount Root and Kernel File Systems... + Starting Remount Root and Kernel File Systems... + [ 33.117472] urandom_read: 4 callbacks suppressed + [ 33.117645] random: systemd: uninitialized urandom read (16 bytes read) + [ 33.214868] systemd[1]: Started Forward Password Requests to Wall Directory Watch. + [ OK ] Started Forward Password Requests to Wall Directory Watch. + [ 33.366745] random: systemd: uninitialized urandom read (16 bytes read) + [ 33.453262] systemd[1]: Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket (/dev/log). + [ 33.627020] random: systemd: uninitialized urandom read (16 bytes read) + [ 34.029973] systemd[1]: Starting Load Kernel Modules... + Starting Load Kernel Modules... + [ OK ] Created slice system-getty.slice. + [ OK ] Started Dispatch Password Requests to Console Directory Watch. + [ OK ] Reached target Local Encrypted Volumes. + [ OK ] Reached target Paths. + [ OK ] Reached target Remote File Systems. + [ OK ] Listening on udev Kernel Socket. + [ OK ] Listening on udev Control Socket. + [ OK ] Reached target Sockets. + Starting udev Coldplug all Devices... + Starting Journal Service... + [ 37.108761] systemd[1]: Starting Create Static Device Nodes in /dev... + Starting Create Static Device Nodes in /dev... + [ 37.941929] systemd[1]: Mounted Kernel Debug File System. + [ OK ] Mounted Kernel Debug File System. + [ 38.463855] systemd[1]: Started Remount Root and Kernel File Systems. + [ OK ] Started Remount Root and Kernel File Systems. + [ 39.614728] systemd[1]: Started Load Kernel Modules. + [ OK ] Started Load Kernel Modules. + [ 40.794332] systemd[1]: Starting Apply Kernel Variables... + Starting Apply Kernel Variables... + [ 41.928338] systemd[1]: Starting Load/Save Random Seed... + Starting Load/Save Random Seed... + [ 43.494757] systemd[1]: Started Create Static Device Nodes in /dev. + [ OK ] Started Create Static Device Nodes in /dev. + [ 44.795372] systemd[1]: Starting udev Kernel Device Manager... + Starting udev Kernel Device Manager... + [ 45.043065] systemd[1]: Reached target Local File Systems (Pre). + [ OK ] Reached target Local File Systems (Pre). + [ 45.224716] systemd[1]: Reached target Local File Systems. + [ OK ] Reached target Local File Systems. + [ 46.036491] systemd[1]: Started Apply Kernel Variables. + [ OK ] Started Apply Kernel Variables. + [ 46.947879] systemd[1]: Started Load/Save Random Seed. + [ OK ] Started Load/Save Random Seed. + [ 47.910242] systemd[1]: Starting Raise network interfaces... + Starting Raise network interfaces... + [ 48.119915] systemd[1]: Started Journal Service. + [ OK ] Started Journal Service. + Starting Flush Journal to Persistent Storage... + [ OK ] Started udev Kernel Device Manager. + [ 55.369915] systemd-journald[88]: Received request to flush runtime journal from PID 1 + [ OK ] Started Flush Journal to Persistent Storage. + Starting Create Volatile Files and Directories... + [ OK ] Started Raise network interfaces. + [ OK ] Reached target Network. + [FAILED] Failed to start Create Volatile Files and Directories. + See 'systemctl status systemd-tmpfiles-setup.service' for details. + Starting Update UTMP about System Boot/Shutdown... + [FAILED] Failed to start Network Time Synchronization. + See 'systemctl status systemd-timesyncd.service' for details. + [ OK ] Reached target System Time Synchronized. + [ OK ] Stopped Network Time Synchronization. + [ OK ] Started udev Coldplug all Devices. + [ OK ] Found device /dev/hvc0. + [ OK ] Reached target System Initialization. + [ OK ] Reached target Basic System. + [ OK ] Started Regular background program processing daemon. + [ OK ] Started Daily Cleanup of Temporary Directories. + Starting Permit User Sessions... + [ OK ] Started Daily apt download activities. + [ OK ] Started Daily apt upgrade and clean activities. + [ OK ] Reached target Timers. + [ OK ] Started Permit User Sessions. + [ OK ] Started Serial Getty on hvc0. + [ OK ] Reached target Login Prompts. + [ OK ] Reached target Multi-User System. + [ OK ] Reached target Graphical Interface. + + Debian GNU/Linux buster/sid openpiton hvc0 + + openpiton login: diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h new file mode 100644 index 0000000000..42c64f3ca5 --- /dev/null +++ b/include/configs/openpiton-riscv64.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2021 Tianrui Wei + * + * Authors: + * Anup Patel <anup.patel(a)wdc.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#ifndef __OPENPITON_RISCV64_CONFIG_H +#define __OPENPITON_RISCV64_CONFIG_H + +#include <linux/sizes.h> + +/* Environment options */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) +#define CONFIG_SYS_LOAD_ADDR 0x87000000 +#define CONFIG_SYS_MALLOC_LEN SZ_256M +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +#ifdef CONFIG_SPL +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x82000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000 +#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin" +#define CONFIG_SPL_GD_ADDR 0x85000000 +#endif + +/* ------------------------------------------------- + * Environment + */ +//Disable persistent environment variable storage +#define CONFIG_ENV_IS_NOWHERE 1 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x86000000\0" \ + "kernel_addr_r=0x80200000\0" \ + "image=boot/Image\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" + +#define CONFIG_USE_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "fdt addr ${fdtcontroladdr}; " \ + "fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \ + "load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \ + "booti ${kernel_addr_r} - ${fdt_addr_r}; " + +#endif/* __CONFIG_H */ -- 2.32.0

1 0

[PATCH v7 0/2] Add OpenPiton-riscv64 board support
by Tianrui Wei 14 Jun '21

14 Jun '21

This patch set is to add OpenPiton board support. Patches are split into several parts: - [PATCH 1/2] add OpenPiton support to mmc driver - [PATCH 2/2] add support for OpenPiton board Description - for mmc driver, it's settings are automatically configured at hardware level. We only need to expose the memory mapped interface through U-Boot driver model - For OpenPiton, as we need to embed the device tree blob into the bitstream, there is currently no itb support Tests checks - Able to boot Debian Linux from SD card on Digilent Genesys 2 - Checkpatch is performed, with some warnings ignored Changelogs - V2 . fix styles and typos in [1/2] and [2/2] . add board documentation in [2/2] - V3 . fix styles in [1/2] - V4 . fix checkpatch warnings in [1/2] except MAINTAINERS - V5 . major changes in device tree . changed to OF_SEPARATE . formatting update for mmc - V6 . eliminate debug outputs altogether . separate defconfigs between SPL and u-boot proper . style updates thanks to Sean - V7 . mmc dm fixes . mmc style updates, improving readibility . mmc add write support . OpenPiton RISC-V 64 board Kconfig fixes Acknowledgements We'd like to thank all maintainers who have reviewed our code. But we'd like to thank Sean and Jaehoon in particular for taking much time and energy to help us write better code. Tianrui Wei (2): board: riscv: add openpiton-riscv64 SoC support mmc: openpiton: add piton_mmc driver arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/openpiton-riscv64.dts | 153 ++++++++ board/openpiton/riscv64/Kconfig | 40 +++ board/openpiton/riscv64/MAINTAINERS | 8 + board/openpiton/riscv64/Makefile | 5 + board/openpiton/riscv64/openpiton-riscv64.c | 33 ++ configs/openpiton_riscv64_defconfig | 76 ++++ configs/openpiton_riscv64_spl_defconfig | 87 +++++ doc/board/index.rst | 1 + doc/board/openpiton/index.rst | 9 + doc/board/openpiton/riscv64.rst | 376 ++++++++++++++++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/piton_mmc.c | 181 ++++++++++ include/configs/openpiton-riscv64.h | 61 ++++ 16 files changed, 1045 insertions(+) create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 board/openpiton/riscv64/Kconfig create mode 100644 board/openpiton/riscv64/MAINTAINERS create mode 100644 board/openpiton/riscv64/Makefile create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 configs/openpiton_riscv64_spl_defconfig create mode 100644 doc/board/openpiton/index.rst create mode 100644 doc/board/openpiton/riscv64.rst create mode 100644 drivers/mmc/piton_mmc.c create mode 100644 include/configs/openpiton-riscv64.h -- 2.32.0

1 0

[PATCH v2] cmd: net: add a 'net list' command to list network devs
by Tim Harvey 14 Jun '21

14 Jun '21

In a system with multiple network controllers it can be difficult to know the names of the various devices available. This is especially true for USB ether devices as they do not display device names upon detection. This is being added as a net sub-system in case other commands may want to be added or moved here. Example: U-Boot > net net - NET sub-system Usage: net list - list available devices U-Boot > net list eth0 : ethernet@2188000 00:d0:12:98:f5:47 active eth1 : e1000#0 00:d0:12:98:f5:48 eth2 : asix_eth 8c:ae:4c:f5:84:9d eth3 : asix_eth 8c:ae:4c:f9:41:e3 Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> Reviewed-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Ramon Fried <rfried.dev(a)gmail.com> --- v2: added Reviewed-by tags --- cmd/net.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/cmd/net.c b/cmd/net.c index beb2877dfd..e51bc443f7 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -10,6 +10,7 @@ #include <common.h> #include <bootstage.h> #include <command.h> +#include <dm.h> #include <env.h> #include <image.h> #include <net.h> @@ -480,3 +481,46 @@ U_BOOT_CMD( ); #endif /* CONFIG_CMD_LINK_LOCAL */ + +static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const struct udevice *current = eth_get_dev(); + unsigned char env_enetaddr[ARP_HLEN]; + const struct udevice *dev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_ETH, dev, uc) { + eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr); + printf("eth%d : %s %pM %s\n", dev_seq(dev), dev->name, env_enetaddr, + current == dev ? "active" : ""); + } + return CMD_RET_SUCCESS; +} + +static struct cmd_tbl cmd_net[] = { + U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""), +}; + +static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct cmd_tbl *cp; + + cp = find_cmd_tbl(argv[1], cmd_net, ARRAY_SIZE(cmd_net)); + + /* Drop the net command */ + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) + return CMD_RET_SUCCESS; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + net, 2, 1, do_net, + "NET sub-system", + "list - list available devices\n" +); -- 2.17.1

2 4

[PATCH] lib: remove superfluous #ifdefs from date.c
by Heinrich Schuchardt 14 Jun '21

14 Jun '21

We should avoid #ifdef in C modules. Unused functions are eliminated by the linker. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/date.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/lib/date.c b/lib/date.c index 0456de78ab..c589d9ed3a 100644 --- a/lib/date.c +++ b/lib/date.c @@ -10,8 +10,6 @@ #include <rtc.h> #include <linux/time.h> -#if defined(CONFIG_LIB_DATE) || defined(CONFIG_TIMESTAMP) - #define FEBRUARY 2 #define STARTOFTIME 1970 #define SECDAY 86400L @@ -97,9 +95,6 @@ unsigned long rtc_mktime(const struct rtc_time *tm) return (hours * 60 + tm->tm_min) * 60 + tm->tm_sec; } -#endif /* CONFIG_LIB_DATE || CONFIG_TIMESTAMP */ - -#ifdef CONFIG_LIB_DATE /* for compatibility with linux code */ time64_t mktime64(const unsigned int year, const unsigned int mon, const unsigned int day, const unsigned int hour, @@ -116,4 +111,3 @@ time64_t mktime64(const unsigned int year, const unsigned int mon, return (time64_t)rtc_mktime((const struct rtc_time *)&time); } -#endif -- 2.30.2

1 0

Announcing a tool for Armada 3720 firmware
by Marek Behun 14 Jun '21

14 Jun '21

Hello, this is announcement of mox-imager [1], a firmware uploader / manipulator for Marvell's Armada 3720 SOC. For most of you who use the SOC on boards other than Turris MOX, the most useful feature probably is that it can upload a firmware via UART at higher baudrates than Marvell's original WtpDownloader, which is useful when debugging or during board manufacture. Features that should be interesting for you: - ability to upload firmware over UART at baudrates up to 6 MBaud. This was tested on ESPRESSObin, but should also work on other boards (uDPU, ESPRESSObin Ultra) Uploading at 3 MBaud: $ ./mox-imager -b 3000000 -D /dev/ttyUSB0 flash-image.bin - ability to upload flash-image.bin firmware over UART When TF-A builds for A3720, it creates image for SPI/eMMC called flash-image.bin, and a directory uart-images containing 3 binaries that you have to use instead of flash-image.bin if you want to boot via UART. mox-imager can work with both methods. When given flash-image.bin, it updates BootFlashSign in the TIM header so that the BootROM will accept the image when given over UART. So both of these work: $ ./mox-imager -D /dev/ttyUSB0 flash-image.bin $ ./mox-imager -D /dev/ttyUSB0 TIM_ATF.bin wtmi_h.bin boot-image_h.bin (This of course does not work if the image needs to be signed cryptographically and the singing key is not present. But AFAIK only Turris MOX uses this feature of the SOC.) - mox-imager has an implementation of a mini-terminal (code from U-Boot's kwboot), which can be used instead of minicom/kermit, once the firmware is uploaded. Although this mini-terminal does not support uploading images over Y-MODEM or other protocols to U-Boot, it can still be useful. If not for anything else, then at least for the ability to not lose any output which the SOC might have sent over UART. (When using minicom/kermit, there is a small window when the /dev/ttyX device is closed and some output is lost.) Use the -t flag to invoke this mini-terminal. Other features that we use on Turris MOX and may be useful to you, but need implementation for your boards: - we use one firmware image for all versions of our board: DDR3 512 MiB, DDR3 1024 MiB, DDR4 This simplifies development of updates significantly. We achieve this by burning board version info into the SOC's OTP. The GPP code contained in the TIM header can read OTP and decide how to initialize clock and DDR registers depending on the values there. The GPP code also works when OTP is empty. In that case it first tries to initialize the registers for DDR3, tests if DDR works, and if not, switches to DDR4. Then it determines RAM size. Note that we do not use this method in production, this was only tested on a few boards that we use for development. (We do not know for example, whether it is safe for the DDR4 chip if we first try to communicate with it in DDR3 mode, since the protocols are different.) You can look at the GPP code at https://gitlab.nic.cz/turris/mox-imager/-/blob/master/gpp/ddr.gpp - mox-imager can create trusted firmware image signed with ECDSA signature and can write the SOC's OTP so that only images signed with a specific ECDSA key will boot. We use this on Turris MOX. Related software: - we have significantly modified Marvell's original WTMI firmware that runs on the Cortex-M3 secure coprocessor. You can look at this modified firmware at our mox-boot-builder repository [2] in directory wtmi. Perhaps the most interesting feature for you is that this firmware exposes the SOC's internal HW RNG via the mailbox to Linux, and that upstream Linux has a driver (turris-mox-rwtm) that registers this random number generator via Linux' crypto API. Another feature our firmware supports is that it can utilize the crypto engine in the secure processor for creating ECDSA signatures. Every Turris MOX has an ECDSA key generated and burned into OTP when manufactured. When done correctly, it is impossible to read this key. It is only possible to use it via the crypto engine for ECDSA signatures. (The firmware has to be in trusted mode for this. If the user has the ability to upload any firmware into their device, they can read the private key from OTP.) This firmware can be built as a standalone replacement of Marvell's WTMI firmware from A3700-utils-marvell repository, but also as an wtmi_app.bin payload application for Marvell's firmware (in this case DDR and clocks are initialized by Marvell's code and HW RNG is provided by wtmi_app.bin). There are instructions on how to use this firmware on ESPRESSObin in mox-boot-builder's README.md. - turris-mox-rwtm driver in Linux [3] communicates with our WTMI firmware (see the point above) and exposes to Linux: - the SOC's HWRNG - the SOC's ECDSA signing engine with singing key stored in OTP. This can be used for authorizing the device, for example via SSH - OTP rows containing Turris MOX' serial number, board version and MAC address I'm thinking about implementing code into this driver so that it will also work with Marvell's original firmware, which only exposes access to OTP memory. - mox-pkcs11 [4] is a plugin for ssh that can utilize the HW ECDSA signing mechanism mentioned above when connecting to an ssh server Let us know if you are interested in any of these or need help with something. Marek & Pali [1] https://gitlab.nic.cz/turris/mox-imager The name should probably be something like a3720-tool, but I called it mox-imager at the beginning because then it was meant to be used only for Turris MOX. [2] https://gitlab.nic.cz/turris/mox-boot-builder [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/dri… [4] https://gitlab.nic.cz/turris/mox-pkcs11

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