June 2021 - U-Boot

[PATCH] MAINTAINER, git-mailrc: Update the mmc maintainer
by Jaehoon Chung 14 Jun '21

14 Jun '21

Update to me as co-maintainer with Peng. Additionally, fix the alias in git-mailrc. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- MAINTAINERS | 1 + doc/git-mailrc | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 86ff5e04a62b..a9257cde4df2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -882,6 +882,7 @@ F: arch/mips/dts/mrvl,cn73xx.dtsi MMC M: Peng Fan <peng.fan(a)nxp.com> +M: Jaehoon Chung <jh80.chung(a)samsung.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git F: drivers/mmc/ diff --git a/doc/git-mailrc b/doc/git-mailrc index 34f936f4d83c..2627edb09ac0 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -25,7 +25,7 @@ alias dinh Dinh Nguyen <dinguyen(a)kernel.org> alias hs Heiko Schocher <hs(a)denx.de> alias freenix Peng Fan <peng.fan(a)nxp.com> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> -alias jaehoon Jaehoon Chung <jh80.chung(a)samsung.com> +alias Jaehoon Jaehoon Chung <jh80.chung(a)samsung.com> alias jagan Jagan Teki <jagan(a)amarulasolutions.com> alias jhersh Joe Hershberger <joe.hershberger(a)ni.com> alias kevery Kever Yang <kever.yang(a)rock-chips.com> @@ -119,7 +119,7 @@ alias kerneldoc uboot, marex alias fdt uboot, sjg alias i2c uboot, hs alias kconfig uboot, masahiro -alias mmc uboot, freenix +alias mmc uboot, freenix, Jaehoon alias nand uboot alias net uboot, jhersh alias phy uboot, jhersh @@ -131,4 +131,4 @@ alias xhci uboot, bmeng alias video uboot, ag alias patman uboot, sjg alias buildman uboot, sjg -alias pmic uboot, jaehoon +alias pmic uboot, Jaehoon -- 2.29.0

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[PATCH] configs: OrangePi PC2: Update defaults
by Jernej Skrabec 14 Jun '21

14 Jun '21

OrangePi PC2 board has DRAM with ODT, so enable it. ZQ value is also slightly different in vendor images, so update it as well. H5 SoC is also connected to voltage regulator. It's default value is pretty low, so in order to avoid instability, enable driver for it and set it to appropriate voltage. Signed-off-by: Jernej Skrabec <jernej.skrabec(a)gmail.com> --- configs/orangepi_pc2_defconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index f72ffe27b26c..5e4cca793f53 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -3,13 +3,15 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 -CONFIG_DRAM_ZQ=3881977 -# CONFIG_DRAM_ODT_EN is not set +CONFIG_DRAM_ZQ=4145117 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPL_I2C_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SUN8I_EMAC=y +CONFIG_SY8106A_POWER=y +CONFIG_SY8106A_VOUT1_VOLT=1100 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y -- 2.31.1

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[GIT PULL] xilinx patches for v2021.07-rc5
by Michal Simek 13 Jun '21

13 Jun '21

Hi Tom, please pull these 3 fixes to your tree. When are you plan to open next branch? Thanks, Michal The following changes since commit e3b64beda5dd1a6b6bedfd1fe0e50be1ddea7044: Prepare v2021.07-rc4 (2021-06-07 09:26:39 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2021.07-rc5 for you to fetch changes up to 6bb577dbb30f3fcf47679328a1b77edc3d0c0b79: arm64: zynqmp: Disable EFI_CAPSULE_ON_DISK_EARLY (2021-06-11 09:24:58 +0200) ---------------------------------------------------------------- Xilinx changes for v2021.07-rc5 zynqmp: - Fix ANALOG_BUS value after powerup - Disable EFI_CAPSULE_ON_DISK_EARLY zynqmp-gqspi: - Fix write issue ---------------------------------------------------------------- Adrian Fiergolski (1): arm64: zynqmp: Writing correct value to ANALOG_BUS Ashok Reddy Soma (1): spi: zynqmp_gqspi: Fix write issue Michal Simek (1): arm64: zynqmp: Disable EFI_CAPSULE_ON_DISK_EARLY arch/arm/mach-zynqmp/include/mach/hardware.h | 5 +++++ board/xilinx/zynqmp/zynqmp.c | 11 +++++++++++ configs/xilinx_zynqmp_virt_defconfig | 1 - drivers/spi/zynqmp_gqspi.c | 18 +++++++++++++++++- 4 files changed, 33 insertions(+), 2 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

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BISECTED f3866909e350 ("distro_bootcmd: call EFI bootmgr even without having /EFI/boot")
by Matwey V. Kornilov 13 Jun '21

13 Jun '21

Hi, I've found that f3866909e350 ("distro_bootcmd: call EFI bootmgr even without having /EFI/boot") breaks running EFI application from USB device on BeagleBone Black (am335x) device. With this patch I see the following: Booting /efi\boot\bootarm.efi Welcome to GRUB! data abort pc : [<9ce0b6d0>] lr : [<9ffab7c7>] reloc pc : [<7d69d6d0>] lr : [<8083d7c7>] sp : 9df44e28 ip : 9ffdfe90 fp : 00000003 r10: 9ffe3300 r9 : 00000000 r8 : 9df6fe88 r7 : 00000000 r6 : 9ce5da08 r5 : 9ce571f8 r4 : 9ce2c040 r3 : 00000000 r2 : 00000001 r1 : 9ce56598 r0 : 00000000 Flags: NzCv IRQs off FIQs on Mode SVC_32 Code: e3500000 0a000015 e590000c eb00f96e (e5d03000) UEFI image [0x9ce46000:0x9cf28fff] '/efi\boot\bootarm.efi' Resetting CPU ... while without the patch, GRUB works as usual. Could you please help me to figure out what is going wrong here? -- With best regards, Matwey V. Kornilov

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[PATCH 1/1] net: sun8i-emac: fix MDIO frequency
by Heinrich Schuchardt 12 Jun '21

12 Jun '21

Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to network failure on the OrangePi PC. => dhcp sun8i_emac_eth_start: Timeout According to the commit message the change of the MDIO frequency is only required for external PHYs. Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/net/sun8i_emac.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5a1b38bf80..d7553fe163 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) * The EMAC clock is either 200 or 300 MHz, so we need a divider * of 128 to get the MDIO frequency below the required 2.5 MHz. */ - mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT; + if (!priv->use_internal_phy) + mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << + MDIO_CMD_MII_CLK_CSR_SHIFT; mii_cmd |= MDIO_CMD_MII_BUSY; @@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, * The EMAC clock is either 200 or 300 MHz, so we need a divider * of 128 to get the MDIO frequency below the required 2.5 MHz. */ - mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT; + if (!priv->use_internal_phy) + mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << + MDIO_CMD_MII_CLK_CSR_SHIFT; mii_cmd |= MDIO_CMD_MII_WRITE; mii_cmd |= MDIO_CMD_MII_BUSY; -- 2.31.0

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[PATCH v3] net: tsec: add option to set device max-speed via dts
by Aleksandar Gerasimovski 12 Jun '21

12 Jun '21

Current tsec adapter sets adapter gigabit capabilities by default, and in reality this must not always be the case. It is possible that tsec adapter is used for 100Mbps connection, and in this case setting 1000Mbps capabilities can lead to some side effects such longer autoneg process. In our ls102x designs this problem leads to long autoneg times (> 4 sec) in case board rgmii link is 100Mbps capable only. Limiting the rgmii link capabilities provides faster and smoother link establishment. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski(a)hitachi-powergrids.com> Reviewed-by: Vladimir Oltean <vladimir.oltean(a)nxp.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes for v2: - keep the variable sort order in a decreasing order of line length - fix comment typo Changes for v3: - fix commit message typos --- drivers/net/tsec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index c68e4b7..ee820aa 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -828,6 +828,7 @@ int tsec_probe(struct udevice *dev) const char *phy_mode; ofnode parent, child; fdt_addr_t reg; + u32 max_speed; int ret; data = (struct tsec_data *)dev_get_driver_data(dev); @@ -893,8 +894,12 @@ int tsec_probe(struct udevice *dev) } priv->interface = pdata->phy_interface; + /* Check for speed limit, default is 1000Mbps */ + max_speed = dev_read_u32_default(dev, "max-speed", 1000); + /* Initialize flags */ - priv->flags = TSEC_GIGABIT; + if (max_speed == 1000) + priv->flags = TSEC_GIGABIT; if (priv->interface == PHY_INTERFACE_MODE_SGMII) priv->flags |= TSEC_SGMII; -- 1.8.3.1

2 1

[PATCH] net: dwc_eth_qos: Revert some changes of commit 3a97da12ee7b
by Daniil Stas 12 Jun '21

12 Jun '21

Revert some changes of commit 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support") that were probably added by mistake. One of these changes can lead to received data corruption (enabling FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings for some platforms. And another makes some writes at unknown memory location. Fixes: 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support") Signed-off-by: Daniil Stas <daniil.stas(a)posteo.net> Cc: Ye Li <ye.li(a)nxp.com> Cc: Fugang Duan <fugang.duan(a)nxp.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/net/dwc_eth_qos.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 2f088c758f..b012bed517 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -172,8 +172,6 @@ struct eqos_mtl_regs { #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) -#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4) -#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3) #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff @@ -1222,7 +1220,6 @@ static int eqos_start(struct udevice *dev) } /* Configure MTL */ - writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100); /* Enable Store and Forward mode for TX */ /* Program Tx operating mode */ @@ -1236,9 +1233,7 @@ static int eqos_start(struct udevice *dev) /* Enable Store and Forward mode for RX, since no jumbo frame */ setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, - EQOS_MTL_RXQ0_OPERATION_MODE_RSF | - EQOS_MTL_RXQ0_OPERATION_MODE_FEP | - EQOS_MTL_RXQ0_OPERATION_MODE_FUP); + EQOS_MTL_RXQ0_OPERATION_MODE_RSF); /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ val = readl(&eqos->mac_regs->hw_feature1); @@ -1314,12 +1309,6 @@ static int eqos_start(struct udevice *dev) eqos->config->config_mac << EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); - clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, - EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << - EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, - 0x2 << - EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); - /* Multicast and Broadcast Queue Enable */ setbits_le32(&eqos->mac_regs->unused_0a4, 0x00100000); -- 2.31.1

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[PATCH] net: e1000: do not attempt to set hwaddr for i210 without FLASH
by Tim Harvey 12 Jun '21

12 Jun '21

commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM") adds support for storing hwaddr in EEPROM however i210 devices do not support this and thus results in errors such as: Warning: e1000#0 failed to set MAC address' Check if a flash device is present and if not return -ENOSYS indicating this is not supported. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/net/e1000.c | 4 ++++ drivers/net/e1000.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 694114eca7..60613b7df0 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5673,6 +5673,10 @@ static int e1000_write_hwaddr(struct eth_device *dev) DEBUGOUT("%s: mac=%pM\n", __func__, mac); + if ((hw->eeprom.type == e1000_eeprom_invm) && + !(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210)) + return -ENOSYS; + memset(current_mac, 0, 6); /* Read from EEPROM, not from registers, to make sure diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 072851ba31..082154a997 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1245,6 +1245,7 @@ struct e1000_hw { #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ +#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ #define E1000_FLUDONE_ATTEMPTS 20000 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ -- 2.17.1

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[PATCH] net: fm: Fix a memory leak issue
by Zhiqiang Hou 12 Jun '21

12 Jun '21

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Fix a memory leak issue in the RX port initialization. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- drivers/net/fm/eth.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 0e89e663f7..7c23ccc1f0 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* alloc Rx buffer from main memory */ rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); - if (!rx_buf_pool) + if (!rx_buf_pool) { + free(rx_bd_ring_base); return -ENOMEM; + } memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool); -- 2.17.1

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[RESEND PATCH v6 1/2] board: riscv: add openpiton-riscv64 SoC support
by Tianrui Wei 12 Jun '21

12 Jun '21

This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper - V6 . separate defconfigs for u-boot and SPL . eliminate debug console output . style updates Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com> Signed-off-by: Jonathan Balkind <jbalkind(a)ucsb.edu> --- arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/openpiton-riscv64.dts | 153 ++++++++ board/openpiton/riscv64/Kconfig | 42 +++ board/openpiton/riscv64/MAINTAINERS | 8 + board/openpiton/riscv64/Makefile | 5 + board/openpiton/riscv64/openpiton-riscv64.c | 33 ++ configs/openpiton_riscv64_defconfig | 76 ++++ configs/openpiton_riscv64_spl_defconfig | 87 +++++ doc/board/index.rst | 1 + doc/board/openpiton/index.rst | 9 + doc/board/openpiton/riscv64.rst | 376 ++++++++++++++++++++ include/configs/openpiton-riscv64.h | 62 ++++ 13 files changed, 857 insertions(+) create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 board/openpiton/riscv64/Kconfig create mode 100644 board/openpiton/riscv64/MAINTAINERS create mode 100644 board/openpiton/riscv64/Makefile create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 configs/openpiton_riscv64_spl_defconfig create mode 100644 doc/board/openpiton/index.rst create mode 100644 doc/board/openpiton/riscv64.rst create mode 100644 include/configs/openpiton-riscv64.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b3d7fd84ce..b30c50e8c7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" +config TARGET_OPENPITON_RISCV64 + bool "Support riscv cores on OpenPiton SoC" + endchoice config SYS_ICACHE_OFF @@ -60,6 +63,7 @@ source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" +source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 7778874831..b6e9166767 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb +dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts new file mode 100644 index 0000000000..45951e1236 --- /dev/null +++ b/arch/riscv/dts/openpiton-riscv64.dts @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 Tianrui Wei <tianrui-wei(a)outlook.com> */ + +/* + * This dts is for a dual core instance of OpenPiton+Ariane built + * to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files + * are automatically generated by the OpenPiton build system and + * this configuration may not be what you need if your configuration + * is different from the below. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "openpiton,riscv64"; + + chosen { + stdout-path = "uart0:115200"; + }; + + aliases { + console = &uart0; + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <520835>; + + CPU0: cpu@0 { + clocks = <&clk0>; + u-boot,dm-spl; + device_type = "cpu"; + reg = <0>; + compatible = "openhwgroup,cva6", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + clocks = <&clk0>; + device_type = "cpu"; + reg = <1>; + compatible = "openhwgroup,cva6", "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + tlb-split; + // HLIC - hart local interrupt controller + CPU1_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + }; + + clocks { + clk0: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <66667000>; + }; + }; + + memory@80000000 { + u-boot,dm-spl; + device_type = "memory"; + reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "openpiton,chipset", "simple-bus"; + ranges; + + uart0: uart@fff0c2c000 { + compatible = "ns16550", "openpiton,ns16550"; + reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >; + interrupt-parent = <&PLIC0>; + interrupts = <1>; + reg-shift = <0>; + // regs are spaced on 8 bit boundary + }; + + eth: ethernet@fff0d00000 { + compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet"; + device_type = "network"; + reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >; + interrupt-parent = <&PLIC0>; + interrupts = <2>; + phy-handle = <&phy0>; + xlnx,duplex = <0x1>; + xlnx,include-global-buffers = <0x1>; + xlnx,include-internal-loopback = <0x0>; + xlnx,include-mdio = <0x1>; + xlnx,rx-ping-pong = <0x1>; + xlnx,s-axi-id-width = <0x1>; + xlnx,tx-ping-pong = <0x1>; + xlnx,use-internal = <0x0>; + axi_ethernetlite_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: phy@1 { + compatible = "ethernet-phy-id001C.C915"; + device_type = "ethernet-phy"; + reg = <1>; + }; + }; + }; + + sdhci_0: sdhci@f000000000 { + u-boot,dm-spl; + compatible = "openpiton,piton-mmc", "openpiton,mmc"; + reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >; + }; + + clint@fff1020000 { + compatible = "sifive,clint0", "openpiton,clint"; + interrupts-extended = < &CPU0_intc 3 + &CPU0_intc 7 + &CPU1_intc 3 + &CPU1_intc 7 >; + reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >; + clocks = <&clk0>; + }; + + PLIC0: plic@fff1100000 { + u-boot,dm-spl; + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0", "openpiton,plic"; + interrupt-controller; + interrupts-extended = < &CPU0_intc 11 + &CPU0_intc 9 + &CPU1_intc 11 + &CPU1_intc 9 >; + reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >; + riscv,max-priority = <7>; + riscv,ndev = <2>; + }; + }; +}; diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig new file mode 100644 index 0000000000..4ee60098b9 --- /dev/null +++ b/board/openpiton/riscv64/Kconfig @@ -0,0 +1,42 @@ +if TARGET_OPENPITON_RISCV64 + +config SYS_BOARD + default "riscv64" + +config SYS_VENDOR + default "openpiton" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "openpiton-riscv64" + +config SYS_TEXT_BASE + default 0x81000000 if SPL + default 0x80000000 if !RISCV_SMODE + default 0x81000000 if RISCV_SMODE + +config SPL_TEXT_BASE + default 0x82000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x80000000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_EARLY_INIT_R + select SUPPORT_SPL + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply CMD_CPU + imply SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT + imply SPL_SMP + imply SPL_MMC + imply SMP + imply SPL_RISCV_MMODE + +endif diff --git a/board/openpiton/riscv64/MAINTAINERS b/board/openpiton/riscv64/MAINTAINERS new file mode 100644 index 0000000000..f91c000c83 --- /dev/null +++ b/board/openpiton/riscv64/MAINTAINERS @@ -0,0 +1,8 @@ +Openpiton BOARD +M: Tianrui Wei<tianrui-wei(a)outlook.com> +S: Maintained +F: board/openpiton/riscv64/ +F: include/configs/openpiton-riscv64.h +F: configs/openpiton_riscv64_defconfig +F: configs/openpiton_riscv64_spl_defconfig +F: drivers/mmc/piton_mmc.c diff --git a/board/openpiton/riscv64/Makefile b/board/openpiton/riscv64/Makefile new file mode 100644 index 0000000000..3bffa75a9a --- /dev/null +++ b/board/openpiton/riscv64/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 Tianrui Wei +# Tianrui Wei <tianrui-wei(a)outlook.com> +obj-y += openpiton-riscv64.o diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c new file mode 100644 index 0000000000..f2282d1548 --- /dev/null +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 SiFive, Inc + * Copyright (c) 2021 Tianrui Wei + * + * + * Authors: + * Pragnesh Patel <pragnesh.patel(a)sifive.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ +#include <common.h> +#include <init.h> +#include <configs/openpiton-riscv64.h> +#include <dm.h> +#include <spl.h> + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { + BOOT_DEVICE_MMC1, + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif + +int board_init(void) +{ + return 0; +} diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig new file mode 100644 index 0000000000..cd66db2fe5 --- /dev/null +++ b/configs/openpiton_riscv64_defconfig @@ -0,0 +1,76 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +CONFIG_TARGET_OPENPITON_RISCV64=y +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +CONFIG_OF_BOARD_FIXUP=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_ENV_VARS_UBOOT_CONFIG=y +# CONFIG_EXPERT is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_PROMPT="openpiton$ " +# CONFIG_CMD_CPU is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_DATE is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set +CONFIG_OF_EMBED=y +# CONFIG_NET is not set +CONFIG_CPU=y +CONFIG_MMC=y +# CONFIG_MMC_WRITE is not set +# CONFIG_MMC_HW_PARTITIONING is not set +# CONFIG_MMC_VERBOSE is not set +CONFIG_MMC_PITON=y +CONFIG_RAM=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_FS_SQUASHFS=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_MD5=y +CONFIG_GETOPT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SPL_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig new file mode 100644 index 0000000000..f681a50fd4 --- /dev/null +++ b/configs/openpiton_riscv64_spl_defconfig @@ -0,0 +1,87 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_PAYLOAD="" +CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64" +CONFIG_TARGET_OPENPITON_RISCV64=y +CONFIG_NR_CPUS=32 +CONFIG_ARCH_RV64I=y +CONFIG_CMODEL_MEDANY=y +CONFIG_RISCV_SMODE=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_ENV_VARS_UBOOT_CONFIG=y +# CONFIG_EXPERT is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_SPL_BANNER_PRINT is not set +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_RTC_SUPPORT=y +# CONFIG_SPL_OPENSBI is not set +CONFIG_SYS_PROMPT="openpiton$ " +# CONFIG_CMD_CPU is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_READ=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_DATE is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +# CONFIG_NET is not set +CONFIG_CPU=y +CONFIG_MMC=y +# CONFIG_MMC_WRITE is not set +# CONFIG_MMC_HW_PARTITIONING is not set +# CONFIG_MMC_VERBOSE is not set +CONFIG_MMC_PITON=y +CONFIG_RAM=y +# CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RTC=y +CONFIG_SYS_NS16550=y +CONFIG_FS_SQUASHFS=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_TPL_TINY_MEMSET=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_MD5=y +CONFIG_GETOPT=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set diff --git a/doc/board/index.rst b/doc/board/index.rst index a70d2de19d..6b1e246217 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -18,6 +18,7 @@ Board-specific doc intel/index kontron/index microchip/index + openpiton/index rockchip/index sifive/index sipeed/index diff --git a/doc/board/openpiton/index.rst b/doc/board/openpiton/index.rst new file mode 100644 index 0000000000..c469102c4b --- /dev/null +++ b/doc/board/openpiton/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +OpenPiton +========= + +.. toctree:: + :maxdepth: 2 + + riscv64 diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst new file mode 100644 index 0000000000..ed7d59db2c --- /dev/null +++ b/doc/board/openpiton/riscv64.rst @@ -0,0 +1,376 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Openpiton RISC-V SoC +==================== + +OpenPiton RISC-V SoC +-------------------- +OpenPiton is an open source, manycore processor and research platform. It is a +tiled manycore framework scalable from one to 1/2 billion cores. It supports a +number of ISAs including RISC-V with its P-Mesh cache coherence protocol and +networks on chip. It is highly configurable in both core and uncore components. +OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes +running full-stack Debian linux. + +RISCV-V Standard Bootflow +------------------------- +Currently, OpenPiton implements RISC-V standard bootflow in the following steps +mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux +This board supports S-mode u-boot as well as M-mode SPL + +Building OpenPition +--------------------- +If you'd like to build OpenPiton, please go to OpenPiton github repo +(at https://github.com/PrincetonUniversity/openpiton) to build from the latest +changes + +Building Images +--------------------------- + +SPL +--- + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + export ARCH=riscv + +3. make openpiton_riscv64_spl_defconfig +4. make + +U-Boot +------ + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + export ARCH=riscv + +3. make openpiton_riscv64_defconfig +4. make + + +opensbi +------- + +1. Add the RISC-V toolchain to your PATH. +2. Setup ARCH & cross compilation environment variable: + +.. code-block:: none + + export CROSS_COMPILE=<riscv64 toolchain prefix> + export ARCH=riscv + +3. Go to OpenSBI directory +4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin> + + +Using fw_payload.bin with linux +------------------------------- +Put the generated fw_payload.bin into the /boot directory on the root filesystem, +plug in the SD card, then flash the bitstream. Linux will boot automatically. + +Booting +------- +Once you plugin the sdcard and power up, you should see the U-Boot prompt. + +Sample Dual-core Debian boot log from OpenPiton +----------------------------------------------- + +.. code-block:: none + + Trying to boot from MMC1 + + OpenSBI v0.9-5-gd06cb61 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + + Platform Name : OPENPITON RISC-V + Platform Features : timer,mfdeleg + Platform HART Count : 3 + Firmware Base : 0x80000000 + Firmware Size : 104 KB + Runtime SBI Version : 0.2 + + Domain0 Name : root + Domain0 Boot HART : 0 + Domain0 HARTs : 0*,1*,2* + Domain0 Region00 : 0x0000000080000000-0x000000008001ffff () + Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X) + Domain0 Next Address : 0x0000000080200000 + Domain0 Next Arg1 : 0x0000000082200000 + Domain0 Next Mode : S-mode + Domain0 SysReset : yes + + Boot HART ID : 0 + Boot HART Domain : root + Boot HART ISA : rv64imafdcsu + Boot HART Features : scounteren,mcounteren + Boot HART PMP Count : 0 + Boot HART PMP Granularity : 0 + Boot HART PMP Address Bits: 0 + Boot HART MHPM Count : 0 + Boot HART MHPM Count : 0 + Boot HART MIDELEG : 0x0000000000000222 + Boot HART MEDELEG : 0x000000000000b109 + + + U-Boot 2021.01+ (Jun 12 2021 - 10:31:34 +0800) + + DRAM: 1 GiB + MMC: sdhci@f000000000: 0 (eMMC) + In: uart@fff0c2c000 + Out: uart@fff0c2c000 + Err: uart@fff0c2c000 + Hit any key to stop autoboot: 0 + 6492992 bytes read in 5310 ms (1.2 MiB/s) + ## Flattened Device Tree blob at 86000000 + Booting using the fdt blob at 0x86000000 + Loading Device Tree to 00000000bfffa000, end 00000000bffff007 ... OK + + Starting kernel ... + + [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 + [ 0.000000] Linux version 5.6.0-rc4-gb9d34f7e294d-dirty + [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') + [ 0.000000] printk: bootconsole [sbi0] enabled + [ 0.000000] Zone ranges: + [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Normal empty + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] + [ 0.000000] On node 0 totalpages: 261632 + [ 0.000000] DMA32 zone: 4088 pages used for memmap + [ 0.000000] DMA32 zone: 0 pages reserved + [ 0.000000] DMA32 zone: 261632 pages, LIFO batch:63 + [ 0.000000] software IO TLB: mapped [mem 0xbaffa000-0xbeffa000] (64MB) + [ 0.000000] SBI specification v0.2 detected + [ 0.000000] SBI implementation ID=0x1 Version=0x9 + [ 0.000000] SBI v0.2 TIME extension detected + [ 0.000000] SBI v0.2 IPI extension detected + [ 0.000000] SBI v0.2 RFENCE extension detected + [ 0.000000] SBI v0.2 HSM extension detected + [ 0.000000] elf_hwcap is 0x112d + [ 0.000000] percpu: Embedded 16 pages/cpu s25368 r8192 d31976 u65536 + [ 0.000000] pcpu-alloc: s25368 r8192 d31976 u65536 alloc=16*4096 + [ 0.000000] pcpu-alloc: [0] 0 + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 257544 + [ 0.000000] Kernel command line: earlycon=sbi root=/dev/piton_sd1 + [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) + [ 0.000000] Sorting __ex_table... + [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off + [ 0.000000] Memory: 956252K/1046528K available (4357K kernel code, 286K rwdata, 1200K rodata, 168K init, 311K bss, 90276K re) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 + [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 + [ 0.000000] plic: mapped 2 interrupts with 1 handlers for 2 contexts. + [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] + [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1ec037a6a, max_idle_ns: 7052723236599 ns + [ 0.000138] sched_clock: 64 bits at 520kHz, resolution 1919ns, wraps every 4398046510738ns + [ 0.009429] printk: console [hvc0] enabled + [ 0.009429] printk: console [hvc0] enabled + [ 0.017850] printk: bootconsole [sbi0] disabled + [ 0.017850] printk: bootconsole [sbi0] disabled + [ 0.028029] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.04 BogoMIPS (lpj=5208) + [ 0.038753] pid_max: default: 32768 minimum: 301 + [ 0.050248] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.058661] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) + [ 0.069359] *** VALIDATE tmpfs *** + [ 0.089093] *** VALIDATE proc *** + [ 0.101135] *** VALIDATE cgroup *** + [ 0.105019] *** VALIDATE cgroup2 *** + [ 0.144310] rcu: Hierarchical SRCU implementation. + [ 0.162836] smp: Bringing up secondary CPUs ... + [ 0.167736] smp: Brought up 1 node, 1 CPU + [ 0.185982] devtmpfs: initialized + [ 0.216237] random: get_random_u32 called from bucket_table_alloc.isra.25+0x4e/0x15c with crng_init=0 + [ 0.236026] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + [ 0.246916] futex hash table entries: 256 (order: 2, 16384 bytes, linear) + [ 0.266994] NET: Registered protocol family 16 + [ 0.763362] clocksource: Switched to clocksource riscv_clocksource + [ 0.770122] *** VALIDATE bpf *** + [ 0.782837] *** VALIDATE ramfs *** + [ 0.829997] NET: Registered protocol family 2 + [ 0.853577] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear) + [ 0.864085] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.875373] TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) + [ 0.887958] TCP: Hash tables configured (established 8192 bind 8192) + [ 0.902149] UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.909904] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + [ 0.924809] NET: Registered protocol family 1 + [ 0.948605] RPC: Registered named UNIX socket transport module. + [ 0.956003] RPC: Registered udp transport module. + [ 0.961565] RPC: Registered tcp transport module. + [ 0.966432] RPC: Registered tcp NFSv4.1 backchannel transport module. + [ 0.987180] Initialise system trusted keyrings + [ 0.998953] workingset: timestamp_bits=46 max_order=18 bucket_order=0 + [ 1.323977] *** VALIDATE nfs *** + [ 1.328520] *** VALIDATE nfs4 *** + [ 1.334422] NFS: Registering the id_resolver key type + [ 1.340148] Key type id_resolver registered + [ 1.345280] Key type id_legacy registered + [ 1.349820] nfs4filelayout_init: NFSv4 File Layout Driver Registering... + [ 1.357610] Installing knfsd (copyright (C) 1996 okir(a)monad.swb.de). + [ 1.866909] Key type asymmetric registered + [ 1.872460] Asymmetric key parser 'x509' registered + [ 1.878750] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) + [ 1.887480] io scheduler mq-deadline registered + [ 1.892864] io scheduler kyber registered + [ 3.905595] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 3.954332] fff0c2c000.uart: ttyS0 at MMIO 0xfff0c2c000 (irq = 1, base_baud = 4166687) is a 16550 + [ 4.254794] loop: module loaded + [ 4.258269] piton_sd:v1.0 Apr 26, 2019 + [ 4.258269] + [ 4.265170] gpt partition table header: + [ 4.265283] signature: 5452415020494645 + [ 4.269258] revision: 10000 + [ 4.273746] size: 5c + [ 4.276659] crc_header: 26b42404 + [ 4.278911] reserved: 0 + [ 4.282730] current lba: 1 + [ 4.285311] backup lda: 3b723ff + [ 4.288093] partition entries lba: 2 + [ 4.291835] number partition entries: 80 + [ 4.295529] size partition entries: 80 + [ 9.473253] piton_sd: piton_sd1 + [ 10.099676] libphy: Fixed MDIO Bus: probed + [ 10.148782] NET: Registered protocol family 10 + [ 10.183418] Segment Routing with IPv6 + [ 10.189384] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + [ 10.214449] NET: Registered protocol family 17 + [ 10.227413] Key type dns_resolver registered + [ 10.240561] Loading compiled-in X.509 certificates + [ 10.465264] EXT4-fs (piton_sd1): mounted filesystem with ordered data mode. Opts: (null) + [ 10.475922] VFS: Mounted root (ext4 filesystem) readonly on device 254:1. + [ 10.551865] devtmpfs: mounted + [ 10.562744] Freeing unused kernel memory: 168K + [ 10.567450] This architecture does not have kernel memory protection. + [ 10.574688] Run /sbin/init as init process + [ 10.578916] with arguments: + [ 10.582489] /sbin/init + [ 10.585312] with environment: + [ 10.588518] HOME=/ + [ 10.591459] TERM=linux + [ 18.154373] systemd[1]: System time before build time, advancing clock. + [ 18.565415] systemd[1]: systemd 238 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIB) + [ 18.596359] systemd[1]: Detected architecture riscv64. + + Welcome to Debian GNU/Linux buster/sid! + + [ 18.797150] systemd[1]: Set hostname to <openpiton>. + [ 31.609244] random: systemd: uninitialized urandom read (16 bytes read) + [ 31.630366] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe. + [ OK ] Listening on /dev/initctl Compatibility Named Pipe. + [ 31.674820] random: systemd: uninitialized urandom read (16 bytes read) + [ 31.806800] systemd[1]: Created slice system-serial\x2dgetty.slice. + [ OK ] Created slice system-serial\x2dgetty.slice. + [ 31.839855] random: systemd: uninitialized urandom read (16 bytes read) + [ 31.850670] systemd[1]: Reached target Slices. + [ OK ] Reached target Slices. + [ 32.128005] systemd[1]: Reached target Swap. + [ OK ] Reached target Swap. + [ 32.180337] systemd[1]: Listening on Journal Socket. + [ OK ] Listening on Journal Socket. + [ 32.416448] systemd[1]: Mounting Kernel Debug File System... + Mounting Kernel Debug File System... + [ 32.937934] systemd[1]: Starting Remount Root and Kernel File Systems... + Starting Remount Root and Kernel File Systems... + [ 33.117472] urandom_read: 4 callbacks suppressed + [ 33.117645] random: systemd: uninitialized urandom read (16 bytes read) + [ 33.214868] systemd[1]: Started Forward Password Requests to Wall Directory Watch. + [ OK ] Started Forward Password Requests to Wall Directory Watch. + [ 33.366745] random: systemd: uninitialized urandom read (16 bytes read) + [ 33.453262] systemd[1]: Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket (/dev/log). + [ 33.627020] random: systemd: uninitialized urandom read (16 bytes read) + [ 34.029973] systemd[1]: Starting Load Kernel Modules... + Starting Load Kernel Modules... + [ OK ] Created slice system-getty.slice. + [ OK ] Started Dispatch Password Requests to Console Directory Watch. + [ OK ] Reached target Local Encrypted Volumes. + [ OK ] Reached target Paths. + [ OK ] Reached target Remote File Systems. + [ OK ] Listening on udev Kernel Socket. + [ OK ] Listening on udev Control Socket. + [ OK ] Reached target Sockets. + Starting udev Coldplug all Devices... + Starting Journal Service... + [ 37.108761] systemd[1]: Starting Create Static Device Nodes in /dev... + Starting Create Static Device Nodes in /dev... + [ 37.941929] systemd[1]: Mounted Kernel Debug File System. + [ OK ] Mounted Kernel Debug File System. + [ 38.463855] systemd[1]: Started Remount Root and Kernel File Systems. + [ OK ] Started Remount Root and Kernel File Systems. + [ 39.614728] systemd[1]: Started Load Kernel Modules. + [ OK ] Started Load Kernel Modules. + [ 40.794332] systemd[1]: Starting Apply Kernel Variables... + Starting Apply Kernel Variables... + [ 41.928338] systemd[1]: Starting Load/Save Random Seed... + Starting Load/Save Random Seed... + [ 43.494757] systemd[1]: Started Create Static Device Nodes in /dev. + [ OK ] Started Create Static Device Nodes in /dev. + [ 44.795372] systemd[1]: Starting udev Kernel Device Manager... + Starting udev Kernel Device Manager... + [ 45.043065] systemd[1]: Reached target Local File Systems (Pre). + [ OK ] Reached target Local File Systems (Pre). + [ 45.224716] systemd[1]: Reached target Local File Systems. + [ OK ] Reached target Local File Systems. + [ 46.036491] systemd[1]: Started Apply Kernel Variables. + [ OK ] Started Apply Kernel Variables. + [ 46.947879] systemd[1]: Started Load/Save Random Seed. + [ OK ] Started Load/Save Random Seed. + [ 47.910242] systemd[1]: Starting Raise network interfaces... + Starting Raise network interfaces... + [ 48.119915] systemd[1]: Started Journal Service. + [ OK ] Started Journal Service. + Starting Flush Journal to Persistent Storage... + [ OK ] Started udev Kernel Device Manager. + [ 55.369915] systemd-journald[88]: Received request to flush runtime journal from PID 1 + [ OK ] Started Flush Journal to Persistent Storage. + Starting Create Volatile Files and Directories... + [ OK ] Started Raise network interfaces. + [ OK ] Reached target Network. + [FAILED] Failed to start Create Volatile Files and Directories. + See 'systemctl status systemd-tmpfiles-setup.service' for details. + Starting Update UTMP about System Boot/Shutdown... + [FAILED] Failed to start Network Time Synchronization. + See 'systemctl status systemd-timesyncd.service' for details. + [ OK ] Reached target System Time Synchronized. + [ OK ] Stopped Network Time Synchronization. + [ OK ] Started udev Coldplug all Devices. + [ OK ] Found device /dev/hvc0. + [ OK ] Reached target System Initialization. + [ OK ] Reached target Basic System. + [ OK ] Started Regular background program processing daemon. + [ OK ] Started Daily Cleanup of Temporary Directories. + Starting Permit User Sessions... + [ OK ] Started Daily apt download activities. + [ OK ] Started Daily apt upgrade and clean activities. + [ OK ] Reached target Timers. + [ OK ] Started Permit User Sessions. + [ OK ] Started Serial Getty on hvc0. + [ OK ] Reached target Login Prompts. + [ OK ] Reached target Multi-User System. + [ OK ] Reached target Graphical Interface. + + Debian GNU/Linux buster/sid openpiton hvc0 + + openpiton login: diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h new file mode 100644 index 0000000000..9ab7125552 --- /dev/null +++ b/include/configs/openpiton-riscv64.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2021 Tianrui Wei + * + * Authors: + * Anup Patel <anup.patel(a)wdc.com> + * Tianrui Wei <tianrui-wei(a)outlook.com> + */ + +#ifndef __OPENPITON_RISCV64_CONFIG_H +#define __OPENPITON_RISCV64_CONFIG_H + +#include <linux/sizes.h> + +/* Environment options */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) +#define CONFIG_SYS_LOAD_ADDR 0x87000000 +#define CONFIG_SYS_MALLOC_LEN SZ_256M +#define CONFIG_SYS_BOOTM_LEN SZ_256M + +#ifdef CONFIG_SPL +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_SDRAM_OFFSET 0x02000000 +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SPL_BSS_SDRAM_OFFSET) +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000 +#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin" +#define CONFIG_SPL_GD_ADDR 0x85000000 +#endif + +/* ------------------------------------------------- + * Environment + */ +//Disable persistent environment variable storage +#define CONFIG_ENV_IS_NOWHERE 1 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x86000000\0" \ + "kernel_addr_r=0x80200000\0" \ + "image=boot/Image\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" + +#define CONFIG_USE_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "fdt addr ${fdtcontroladdr}; " \ + "fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \ + "load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \ + "booti ${kernel_addr_r} - ${fdt_addr_r}; " + +#endif/* __CONFIG_H */ -- 2.32.0

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