May 2017 - U-Boot

[U-Boot] [PATCH v6 00/18] arm: rpi: Enable USB, Ethernet, MMC, Video driver model on Raspberry Pi
by Simon Glass 10 May '17

10 May '17

Raspberry Pi uses a DWC2 USB controller and a SMSC USB Ethernet adaptor. Driver model support for these is available. This series does the following: - Enable CONFIG_DM_ETH and CONFIG_DM_USB on Raspberry Pi - Convert the MMC driver to driver model - Convert the video driver to driver model - Fixes a driver model video bug which accessed beyond the frame buffer - Fixes start-up of MMC with driver model (e.g. at present it does not support env_fat) - Clean up a few loose ends With Ethernet active the device list looks something like this: U-Boot> dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ + ] |-- soc gpio [ + ] | |-- gpio@7e200000 serial [ + ] | |-- serial@7e215040 mmc [ + ] | |-- sdhci@7e300000 blk [ + ] | | `-- sdhci(a)7e300000.blk video [ + ] | |-- hdmi@7e902000 vidconsole0 [ + ] | | `-- hdmi(a)7e902000.vidconsole0 usb [ + ] | `-- usb@7e980000 usb_hub [ + ] | `-- usb_hub usb_hub [ + ] | `-- usb_hub eth [ + ] | `-- smsc95xx_eth simple_bus [ ] `-- clocks With version 4 a problem was discovered where tftpboot does not correctly read a file on rpi_2 and rpi_3. The cause is unknown but for now this series includes a work-around in the dwc2 driver. See here for details: https://lists.denx.de/pipermail/u-boot/2017-April/285451.html Changes in v6: - Drop changes to dwc2.c now we have http://patchwork.ozlabs.org/patch/746917/ - Rebase to master Changes in v5: - Add new patch for smsc95xx to correct free_pkt() implementation - Rebase to master Changes in v4: - Add patches to convert video and MMC to driver model also - Rebase to master Changes in v3: - Drop applied patches from series - Drop patch to introduce usbethaddr for driver model Simon Glass (18): net: smsc95xx: Correct free_pkt() implementation dm: mmc: Set up the MMC device when controller is probed dm: video: Correct line clearing code string: Use memcpy() within memmove() when we can arm: rpi: Drop the GPIO device addresses arm: rpi: Drop CONFIG_CONS_INDEX dm: arm: rpi: Move to driver model for USB dm: arm: rpi: Use driver model for Ethernet arm: rpi: Add a file to handle messages arm: rpi: Add a function to obtain the MMC clock dm: mmc: rpi: Convert Raspberry Pi to driver model for MMC dm: arm: rpi: Drop CONFIG_OF_EMBED video: arm: rpi: Move the video query out of the driver video: arm: rpi: Move the video settings out of the driver dm: video: Refactor lcd_simplefb to prepare for driver model dm: video: Add driver-model support to lcd_simplefb dm: video: arm: rpi: Convert to use driver model for video arm: rpi: Add a TODO to move all messages into the msg handler arch/arm/mach-bcm283x/Makefile | 2 +- arch/arm/mach-bcm283x/include/mach/gpio.h | 5 - arch/arm/mach-bcm283x/include/mach/msg.h | 51 ++++++++++ arch/arm/mach-bcm283x/msg.c | 154 ++++++++++++++++++++++++++++++ board/raspberrypi/rpi/rpi.c | 56 +---------- common/lcd_simplefb.c | 47 +++++++-- configs/rpi_2_defconfig | 6 +- configs/rpi_3_32b_defconfig | 6 +- configs/rpi_3_defconfig | 6 +- configs/rpi_defconfig | 6 +- drivers/mmc/bcm2835_sdhci.c | 81 ++++++++++++---- drivers/mmc/mmc-uclass.c | 12 +++ drivers/usb/eth/smsc95xx.c | 4 +- drivers/video/bcm2835.c | 140 +++++++-------------------- drivers/video/console_normal.c | 3 +- include/configs/rpi.h | 17 +--- lib/string.c | 11 +-- 17 files changed, 384 insertions(+), 223 deletions(-) create mode 100644 arch/arm/mach-bcm283x/include/mach/msg.h create mode 100644 arch/arm/mach-bcm283x/msg.c -- 2.12.2.715.g7642488e1d-goog

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[U-Boot] [PATCH] Allow boards to initialize the DT at runtime.
by Alex Deymo 10 May '17

10 May '17

In some boards like the Raspberry Pi the initial bootloader will pass a DT to the kernel. When using U-boot as such kernel, the board code in U-Boot should be able to provide U-boot with this, already assembled device tree blob. This patch introduces a new config option CONFIG_OF_BOARD to use instead of CONFIG_OF_EMBED or CONFIG_OF_SEPARATE which will initialize the DT from a board-specific funtion instead of bundling one with U-boot or as a separated file. This allows boards like the Raspberry Pi to reuse the device tree passed from the bootcode.bin and start.elf firmware files, included the run-time selected device tree overlays. Signed-off-by: Alex Deymo <deymo(a)google.com> --- README | 8 +++++++- board/raspberrypi/rpi/rpi.c | 10 ++++++++++ doc/README.fdt-control | 4 ++++ dts/Kconfig | 8 ++++++++ include/fdtdec.h | 6 ++++++ lib/fdtdec.c | 3 +++ 6 files changed, 38 insertions(+), 1 deletion(-) diff --git a/README b/README index aa907ced8a..e658f02a7e 100644 --- a/README +++ b/README @@ -975,7 +975,7 @@ The following options need to be configured: tree is available in the global data as gd->fdt_blob. U-Boot needs to get its device tree from somewhere. This can - be done using one of the two options below: + be done using one of the three options below: CONFIG_OF_EMBED If this variable is defined, U-Boot will embed a device tree @@ -996,6 +996,12 @@ The following options need to be configured: still use the individual files if you need something more exotic. + CONFIG_OF_BOARD + If this variable is defined, U-Boot will use the device tree + provided by the board at runtime instead of embedding one with + the image. Only boards defining board_fdt_blob_setup() support + this option (see include/fdtdec.h file). + - Watchdog: CONFIG_WATCHDOG If this variable is defined, it enables watchdog diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 2146534b36..ef04d397d6 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -516,6 +516,16 @@ int board_mmc_init(bd_t *bis) msg_clk->get_clock_rate.body.resp.rate_hz); } +/* + * If the firmware passed a device tree use it for U-Boot. + */ +void *board_fdt_blob_setup(void) +{ + if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) + return NULL; + return (void *)fw_dtb_pointer; +} + int ft_board_setup(void *blob, bd_t *bd) { /* diff --git a/doc/README.fdt-control b/doc/README.fdt-control index c965629905..378b06b108 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -130,6 +130,10 @@ u-boot-dtb.bin which does the above step for you also. If you are using CONFIG_SPL_FRAMEWORK, then u-boot.img will be built to include the device tree binary. +If CONFIG_OF_BOARD is defined, a board-specific routine will provide the +device tree at runtime, for example if an earlier bootloader stage creates +it and passes it to U-Boot. + If CONFIG_OF_HOSTFILE is defined, then it will be read from a file on startup. This is only useful for sandbox. Use the -d flag to U-Boot to specify the file to read. diff --git a/dts/Kconfig b/dts/Kconfig index 3f64eda619..978b2d7f3d 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -51,6 +51,14 @@ config OF_EMBED and development only and is not recommended for production devices. Boards in the mainline U-Boot tree should not use it. +config OF_BOARD + bool "Provided by the board at runtime" + depends on !SANDBOX + help + If this option is enabled, the device tree will be provided by + the board at runtime if the board supports it, instead of being + bundled with the image. + config OF_HOSTFILE bool "Host filed DTB for DT control" depends on SANDBOX diff --git a/include/fdtdec.h b/include/fdtdec.h index d074478f14..5c54f71458 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1015,4 +1015,10 @@ int fdtdec_setup_memory_banksize(void); */ int fdtdec_setup(void); +/** + * Board-specific FDT initialization. Returns the address to a device tree blob. + * Called when CONFIG_OF_BOARD is defined. + */ +void *board_fdt_blob_setup(void); + #endif diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 81f47ef2c7..2e1beb545b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1247,6 +1247,9 @@ int fdtdec_setup(void) /* FDT is at end of image */ gd->fdt_blob = (ulong *)&_end; # endif +# elif defined(CONFIG_OF_BOARD) + /* Allow the board to override the fdt address. */ + gd->fdt_blob = board_fdt_blob_setup(); # elif defined(CONFIG_OF_HOSTFILE) if (sandbox_read_fdt_from_file()) { puts("Failed to read control FDT\n"); -- 2.12.2.564.g063fe858b8-goog

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[U-Boot] [PATCH] [V2] bcm2835: wdt: support for the bcm2835/2836 wdt
by Paolo Pisati 10 May '17

10 May '17

The following patch add support for the watchdog built into the bcm2835/2836 chips, using the max timeout (~15s). Tested on my RaspberryPi2. Changelog: v2: fixed __eufi_runtime usage and moved to Kconfig Paolo Pisati (1): bcm2835_wdt: support for the BCM2835/2836 watchdog arch/arm/mach-bcm283x/reset.c | 21 ++++++++++++++++++--- board/raspberrypi/rpi/rpi.c | 4 ++++ drivers/watchdog/Kconfig | 15 +++++++++++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/bcm2835_wdt.c | 35 +++++++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+), 3 deletions(-) create mode 100644 drivers/watchdog/bcm2835_wdt.c -- 2.7.4

2 2

[U-Boot] [PATCH v4 00/12] STiH410-B2260: add reset, usb and fastboot support
by patrice.chotard＠st.com 10 May '17

10 May '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series adds : _ update existing sdhci driver to use reset framework _ add usb phy driver _ add ehci support _ add ohci support _ add xhci support _ add fastboot support With all this feature enable, it's now possible to _ boot on usb mass storage device _ boot from kernel image and dtb previously loaded using tftp _ update mmc partiton using fastboot v4: _ use PHY uclass currently available on dm-next branch, update sti ehci, ohci and xhci drivers to use new PHY uclass. v3: _ remove reset driver (already applied on u-boot-dm tree by Simon Glass) _ patch 4: add new USB PHY uclass requested by Simon Glass _ patch 5: convert STi usb phy driver to new USB PHY uclass _ patch 6/7: update echi/ohci drivers to use USB PHY uclass _ patch 8/9: rework xhci-sti.c and dwc3-sti.c. Previously, xhci-sti driver binded dwc3-sti (STi glue driver) which was not correct. Now we respect the device tree hierarchy, ie the STi dwc3 glue driver is first probed, then bind the xhci-sti driver. v2: _ add Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> in patches 2,3 and 4 _ fix remarks done by Marek Vasut : _ patch 5 : replace bitfield_replace() by clrsetbits_le32() _ patch 6 : update error messages and add remove callback _ patch 8 : put board specific defines in a separate patch _ patch 7: use setbits_le32() instead of read, modify, write sequence and add missing parenthesis _ squash previous patches 7,9,11,12,14,16,17,18,19,20 and 21 in patch 14 Patrice Chotard (12): mmc: sti_sdhci: Rework sti_mmc_core_config() ARM: dts: stih410-family: Add missing reset_names for mmc1 node mmc: sti_sdhci: Use reset framework usb: phy: Add STi USB2 PHY usb: ehci: Add STi ehci support usb: ohci: Add STi ohci support usb: xhci: Add STi xhci support usb: dwc3: Add dwc3 glue driver support for STi board: STiH410-B2260: add OHCI and XHCI related defines board: STiH410-B2260: add fastboot support STiH410-B2260: enable USB Host Networking STiH410-B2260: enable USB, fastboot, reset related flags arch/arm/dts/stih407-family.dtsi | 1 + arch/arm/include/asm/arch-stih410/sys_proto.h | 11 + board/st/stih410-b2260/board.c | 44 ++++ configs/stih410-b2260_defconfig | 37 ++- doc/device-tree-bindings/phy/phy-stih407-usb.txt | 24 ++ doc/device-tree-bindings/usb/dwc3-st.txt | 60 +++++ drivers/mmc/sti_sdhci.c | 60 +++-- drivers/phy/Kconfig | 8 + drivers/phy/Makefile | 1 + drivers/phy/sti_usb_phy.c | 181 +++++++++++++++ drivers/usb/host/Kconfig | 26 +++ drivers/usb/host/Makefile | 3 + drivers/usb/host/dwc3-sti-glue.c | 278 +++++++++++++++++++++++ drivers/usb/host/ehci-sti.c | 120 ++++++++++ drivers/usb/host/ohci-sti.c | 119 ++++++++++ drivers/usb/host/xhci-sti.c | 128 +++++++++++ include/configs/stih410-b2260.h | 16 ++ include/dwc3-sti-glue.h | 43 ++++ 18 files changed, 1134 insertions(+), 26 deletions(-) create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h create mode 100644 doc/device-tree-bindings/phy/phy-stih407-usb.txt create mode 100644 doc/device-tree-bindings/usb/dwc3-st.txt create mode 100644 drivers/phy/sti_usb_phy.c create mode 100644 drivers/usb/host/dwc3-sti-glue.c create mode 100644 drivers/usb/host/ehci-sti.c create mode 100644 drivers/usb/host/ohci-sti.c create mode 100644 drivers/usb/host/xhci-sti.c create mode 100644 include/dwc3-sti-glue.h -- 1.9.1

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[U-Boot] [PATCH 1/5] ARM64: poplar: add device tree bindings
by Jorge Ramirez-Ortiz 10 May '17

10 May '17

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz(a)linaro.org> --- arch/arm/dts/hi3798cv200-poplar.dts | 169 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 413 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 686 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts new file mode 100644 index 0000000..4e2b1d1 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -0,0 +1,169 @@ +/* + * DTS File for HiSilicon Poplar Development Board + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "hi3798cv200.dtsi" + +/ { + model = "HiSilicon Poplar Development Board"; + compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x000000000 0x00000000 0x00000000 0x80000000>; + }; + + soc { + leds { + compatible = "gpio-leds"; + + user-led0 { + label = "USER-LED0"; + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "USER-LED1"; + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "USER-LED2"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + user-led3 { + label = "USER-LED3"; + gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; + }; +}; + +&uart0 { + status = "ok"; +}; + +&uart2 { + status = "ok"; + label = "LS-UART0"; +}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ + +&i2c0 { + status = "ok"; + label = "LS-I2C0"; +}; + +&i2c2 { + status = "ok"; + label = "LS-I2C1"; +}; + +&spi0 { + status = "ok"; + label = "LS-SPI0"; +}; + +&gpio1 { + status = "ok"; + gpio-line-names = "LS-GPIO-E", "", + "", "", + "", "LS-GPIO-F", + "", "LS-GPIO-J"; +}; + +&gpio2 { + status = "ok"; + gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", + "LS-GPIO-L", "LS-GPIO-G", + "LS-GPIO-K", "", + "", ""; +}; + +&gpio3 { + status = "ok"; + gpio-line-names = "", "", + "", "", + "LS-GPIO-C", "", + "", "LS-GPIO-B"; +}; + +&gpio4 { + status = "ok"; + gpio-line-names = "", "", + "", "", + "", "LS-GPIO-D", + "", ""; +}; + +&gpio5 { + status = "ok"; + gpio-line-names = "", "USER-LED-1", + "USER-LED-2", "", + "", "LS-GPIO-A", + "", ""; +}; + +&gpio6 { + status = "ok"; + gpio-line-names = "", "", + "", "USER-LED-0", + "", "", + "", ""; +}; + +&gpio10 { + status = "ok"; + gpio-line-names = "", "", + "", "", + "", "", + "USER-LED-3", ""; +}; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&eth_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + status = "ok"; + + eth_phy1: phy@3{ + reg = <3>; + }; +}; diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi new file mode 100644 index 0000000..4757eb1 --- /dev/null +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -0,0 +1,413 @@ +/* + * DTS File for HiSilicon Hi3798cv200 SOC. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/reset/ti-syscon.h> + +/ { + compatible = "hisilicon,hi3798cv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /*GICD*/ + <0x0 0xf1002000 0x0 0x100>; /*GICC*/ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00000000 0x0 0xffffffff>; + + crg: clock-reset-controller@f8a22000 { + compatible = "hisilicon,hi3798cv200-crg", "simple-mfd"; + reg = <0xf8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + + gmacphyrst: reset-controller { + compatible = "ti,syscon-reset"; + reset-cells = <1>; + ti,reset-bits = < + 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR|DEASSERT_SET|STATUS_NONE) /* 0: gmac0-phy-rst */ + 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR|DEASSERT_SET|STATUS_NONE) /* 1: gmac1-phy-rst */ + >; + }; + }; + + sysctrl: system-controller@f8000000 { + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; + reg = <0xf8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + uart0: serial@f8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b00000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clock = <75000000>; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@f8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b02000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@f8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b10000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C0_CLK>; + status = "disabled"; + }; + + i2c1: i2c@f8b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b11000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C1_CLK>; + status = "disabled"; + }; + + i2c2: i2c@f8b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b12000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C2_CLK>; + status = "disabled"; + }; + + i2c3: i2c@f8b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C3_CLK>; + status = "disabled"; + }; + + i2c4: i2c@f8b14000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C4_CLK>; + status = "disabled"; + }; + + spi0: spi@f8b1a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xf8b1a000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + cs-gpios = <&gpio7 1 0>; + clocks = <&crg HISTB_SPI0_CLK>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emmc: mmc@f9830000 { + compatible = "snps,dw-mshc"; + reg = <0xf9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + gpio0: gpio@f8b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b20000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@f8b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b21000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio2: gpio@f8b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b22000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio3: gpio@f8b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b23000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio4: gpio@f8b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b24000 0x1000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio5: gpio@f8004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8004000 0x1000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio6: gpio@f8b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b26000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio7: gpio@f8b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b27000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio8: gpio@f8b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b28000 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio9: gpio@f8b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b29000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio10: gpio@f8b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b2a000 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio11: gpio@f8b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b2b000 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio12: gpio@f8b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b2c000 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gmac0: ethernet@f9840000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0xf9840000 0x1000>, + <0xf984300c 0x4>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, + <&crg 0xcc 10>, + <&gmacphyrst 0>; + reset-names = "mac_core", "mac_ifc", "phy"; + }; + + gmac1: ethernet@f9841000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0xf9841000 0x1000>, + <0xf9843010 0x4>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH1_MAC_CLK>, + <&crg HISTB_ETH1_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 9>, + <&crg 0xcc 11>, + <&gmacphyrst 1>; + reset-names = "mac_core", "mac_ifc", "phy"; + }; + + ir: ir@f8001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0xf8001000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_IR_CLK>; + }; + }; +}; diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 0000000..181c0f0 --- /dev/null +++ b/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 + + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 0000000..884fd91 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif -- 2.7.4

5 20

[U-Boot] [PATCH v5 00/16] GPT over MTD
by Patrick Delaunay 10 May '17

10 May '17

I have a request to support GPT over MTD to have the MTD informations without U-Boot environment(CONFIG_ENV_IS_NOWHERE is a other requirement of my project to manage several board configuration with the same defconfig; boot from NAND or NOR or SDCARD). The current idea is to use the GPT header format to save the partitioning information directly in flash device (NOR or NAND), then the U-Boot MTD variables are rebuild from these GPT partitions and can be used by DISTRO command to search bootable binary. This information are directly used by BootRom to locate and load the first bootstage. The added code is under a new CONFIG : CONFIG_EFI_PARTITION_MTD and in the new file "disk/part_efi_mtd.c" For implementation details, see doc/README.gpt.mtd TODO: full support for modified command (if needed) today I limit the support for the command expected used by DISTRO macro: + gpt write + part list PLANNED: DISTRO macro update for automatic boot on GPT bootable partition found in MTD devices => as it is needed for my project, I will propose an other patch when this on will be accepted the current level is tested manually on sandbox with : > make O=sandbox sandbox_defconfig > make O=sandbox > dd if=/dev/zero of=spi.bin bs=1M count=4 > sandbox/u-boot -d sandbox/arch/sandbox/dts/test.dtb => sf probe SF: Detected M25P16 with page size 256 Bytes, erase size 64 KiB, total 2 MiB => setenv nor_part "name=part1,size=64KiB;name=part2,size=128KiB;\ name=boot,type=linux,bootable,size=512KiB" => gpt write nor 0 $nor_part Writing GPT: success! => part list nor 0 Part Start LBA End LBA Name Attributes Type GUID Partition GUID 1 0x00000080 0x000000ff "part1" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 type: data guid: d117f98e-6f2c-0040-00b2-331a19f91cb2 2 0x00000100 0x000001ff "part2" attrs: 0x0000000000000000 type: ebd0a0a2-b9e5-4433-87c0-68b6b72699c7 type: data guid: 25718777-d0ad-0000-8060-02cb591c9737 3 0x00000200 0x000005ff "boot" attrs: 0x0000000000000004 type: 0fc63daf-8483-4772-8e79-3d69d8477de4 type: linux guid: 8a4bb8b4-e304-0040-0036-aff5c9c495b1 => setenv mtdids "nor0=nor0" => setenv mtdparts "mtdparts=" => mtdparts gpt nor0 => mtdparts device nor0 <nor0>, # parts = 3 #: name size offset mask_flags 0: part1 0x00010000 0x00010000 0 1: part2 0x00020000 0x00020000 0 2: boot 0x00080000 0x00040000 0 active partition: nor0,0 - (part1) 0x00010000 @ 0x00010000 defaults: mtdids : none mtdparts: none => part list nor 0 -bootable nor_boot_part => printenv nor_boot_part nor_boot_part=3 test filtering feature (can be used to mask some partitions to linux according the GUID) 1/ only add MTD for some guid = linux 2/ then add MTD for some guid = data => mtdparts delall => setenv mtdparts "mtdparts=" => setenv mtdids "nor0=nor0" => mtdparts gpt nor0 linux => mtdparts device nor0 <nor0>, # parts = 1 #: name size offset mask_flags 0: boot 0x00080000 0x00040000 0 active partition: nor0,0 - (boot) 0x00080000 @ 0x00040000 defaults: mtdids : none mtdparts: none => mtdparts gpt nor0 data => mtdparts device nor0 <nor0>, # parts = 3 #: name size offset mask_flags 0: part1 0x00010000 0x00010000 0 1: part2 0x00020000 0x00020000 0 2: boot 0x00080000 0x00040000 0 active partition: nor0,2 - (boot) 0x00080000 @ 0x00040000 defaults: mtdids : none mtdparts: none Changes in v5: - rebase of the top of latest u-boot master - solve warning and error (dont' include linux/mtd/mtd.h in part.h) Changes in v4: - change RFC to PATCH - update cover letter - rebase on v2017.03 Changes in v3: - solve issue in compute partition_entry_lba update : missing / lba_size - rework and split patches for unrelated change after review from Cristophe Kerello and Simon Glass - rebase on v2017.03-rc1 Changes in v2: - split serie to reduce patches size (separate disk part and cmd impact and add precursor patch) - split large function Patrick Delaunay (16): uuid: add a function for GUID string parsing disk: part: refactor part_print_efi to prepare GPT over MTD disk: part: refactor part_get_info_efi to prepare GPT over MTD disk: part: prepare_backup_gpt_header rework disk: part: compute partition_entry_lba disk: part: efi: export internal function disk: part: add support of GPT partitioning over MTD cmd: gpt: remove blk_desc parameter in static function cmd: gpt: use error number in set_gpt_info cmd: gpt: add print_gpt_info_err cmd: gpt: update write command to support GPT over MTD cmd: part: update command to support GPT over MTD cmd: mtdparts: move PART_ADD_DESC_MAXLEN cmd: mtdparts: update command to support GPT over MTD uuid: remove dependency with io.h sandbox: GPT over MTD test cmd/gpt.c | 128 +++++++++---- cmd/mtdparts.c | 144 ++++++++++++++- cmd/part.c | 49 ++++- configs/sandbox_defconfig | 3 + disk/Kconfig | 17 ++ disk/Makefile | 1 + disk/part_efi.c | 140 +++++++------- disk/part_efi_int.h | 36 ++++ disk/part_efi_mtd.c | 457 ++++++++++++++++++++++++++++++++++++++++++++++ doc/README.gpt.mtd | 189 +++++++++++++++++++ include/configs/sandbox.h | 6 + include/part.h | 15 +- include/uuid.h | 1 + lib/uuid.c | 48 ++++- 14 files changed, 1111 insertions(+), 123 deletions(-) create mode 100644 disk/part_efi_int.h create mode 100644 disk/part_efi_mtd.c create mode 100644 doc/README.gpt.mtd -- 1.9.1

3 28

[U-Boot] [PATCH] sunxi: setup simplefb for Allwinner DE2
by Icenowy Zheng 10 May '17

10 May '17

As the support of EFI boot on Allwinner H3 is broken, we still need to use simplefb to pass the framebuffer to Linux. Add code to setup simplefb for Allwinner DE2 driver. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- drivers/video/sunxi/sunxi_de2.c | 81 +++++++++++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 4 ++ 2 files changed, 85 insertions(+) diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 9a32c3a020..97e0513f04 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -10,6 +10,8 @@ #include <display.h> #include <dm.h> #include <edid.h> +#include <fdtdec.h> +#include <fdt_support.h> #include <video.h> #include <asm/global_data.h> #include <asm/io.h> @@ -256,3 +258,82 @@ U_BOOT_DRIVER(sunxi_de2) = { U_BOOT_DEVICE(sunxi_de2) = { .name = "sunxi_de2" }; + +/* + * Simplefb support. + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB) +int sunxi_simplefb_setup(void *blob) +{ + struct udevice *de2, *hdmi; + struct video_priv *de2_priv; + struct video_uc_platdata *de2_plat; + int mux; + int offset, ret; + u64 start, size; + const char *pipeline = NULL; + + debug("Setting up simplefb\n"); + + if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) + mux = 0; + else + mux = 1; + + /* Skip simplefb setting if DE2 / HDMI is not present */ + ret = uclass_find_device_by_name(UCLASS_VIDEO, + "sunxi_de2", &de2); + if (ret) { + debug("DE2 not present\n"); + return 0; + } + + ret = uclass_find_device_by_name(UCLASS_DISPLAY, + "sunxi_dw_hdmi", &hdmi); + if (ret) { + debug("HDMI not present\n"); + return 0; + } + + if (mux == 0) + pipeline = "mixer0-lcd0-hdmi"; + else + pipeline = "mixer1-lcd1-hdmi"; + + de2_priv = dev_get_uclass_priv(de2); + de2_plat = dev_get_uclass_platdata(de2); + + /* Find a prefilled simpefb node, matching out pipeline config */ + offset = fdt_node_offset_by_compatible(blob, -1, + "allwinner,simple-framebuffer"); + while (offset >= 0) { + ret = fdt_stringlist_search(blob, offset, "allwinner,pipeline", + pipeline); + if (ret == 0) + break; + offset = fdt_node_offset_by_compatible(blob, offset, + "allwinner,simple-framebuffer"); + } + if (offset < 0) { + eprintf("Cannot setup simplefb: node not found\n"); + return 0; /* Keep older kernels working */ + } + + start = gd->bd->bi_dram[0].start; + size = de2_plat->base - start; + ret = fdt_fixup_memory_banks(blob, &start, &size, 1); + if (ret) { + eprintf("Cannot setup simplefb: Error reserving memory\n"); + return ret; + } + + ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base, + de2_priv->xsize, de2_priv->ysize, + (1 << de2_priv->bpix) / 8 * de2_priv->xsize, + "x8r8g8b8"); + if (ret) + eprintf("Cannot setup simplefb: Error setting properties\n"); + + return ret; +} +#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 997a92c8be..8078ffe82a 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -286,6 +286,10 @@ extern int soft_i2c_gpio_scl; #endif /* CONFIG_VIDEO */ +#ifdef CONFIG_VIDEO_DE2 +#define CONFIG_VIDEO_DT_SIMPLEFB +#endif + /* Ethernet support */ #ifdef CONFIG_SUNXI_EMAC #define CONFIG_PHY_ADDR 1 -- 2.12.2

3 2

[U-Boot] [PATCH 0/4] dm: power: domain: add BCM6328 power domain driver
by Álvaro Fernández Rojas 10 May '17

10 May '17

BCM6328 SoCs have power domain controllers which supports enabling and disabling power for the different peripherals. Álvaro Fernández Rojas (4): dm: power: domain: add BCM6328 power domain driver mips: bmips: add bcm6328-power-domain driver support for BCM6328 mips: bmips: add bcm6328-power-domain driver support for BCM63268 mips: bmips: enable bcm6328-power-domain driver for BCM6328 and BCM63268 boards arch/mips/dts/brcm,bcm63268.dtsi | 7 ++ arch/mips/dts/brcm,bcm6328.dtsi | 7 ++ configs/comtrend_ar5387un_ram_defconfig | 2 + configs/comtrend_vr3032u_ram_defconfig | 2 + drivers/power/domain/Kconfig | 7 ++ drivers/power/domain/Makefile | 1 + drivers/power/domain/bcm6328-power-domain.c | 83 ++++++++++++++++++++++ .../power-domain/bcm63268-power-domain.h | 25 +++++++ .../power-domain/bcm6328-power-domain.h | 21 ++++++ 9 files changed, 155 insertions(+) create mode 100644 drivers/power/domain/bcm6328-power-domain.c create mode 100644 include/dt-bindings/power-domain/bcm63268-power-domain.h create mode 100644 include/dt-bindings/power-domain/bcm6328-power-domain.h -- 2.1.4

2 5

[U-Boot] [PATCH 0/5] dm: clk: add BCM6345 gated clock controller support
by Álvaro Fernández Rojas 10 May '17

10 May '17

Broadcom MIPS SoCs have gated clock controllers which only allow enabling and disabling each peripheral clock. Changing clock rates is not possible on these SoCs. Álvaro Fernández Rojas (5): dm: clk: add BCM6345 clock driver mips: bmips: add bcm6345-clk driver support for BCM6358 mips: bmips: add bcm6345-clk driver support for BCM6328 mips: bmips: add bcm6345-clk driver support for BCM63268 mips: bmips: enable bcm6345-clk driver for all BMIPS boards arch/mips/dts/brcm,bcm63268.dtsi | 13 +++++ arch/mips/dts/brcm,bcm6328.dtsi | 7 +++ arch/mips/dts/brcm,bcm6358.dtsi | 7 +++ configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + drivers/clk/Kconfig | 8 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_bcm6345.c | 78 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/bcm63268-clock.h | 52 ++++++++++++++++++++ include/dt-bindings/clock/bcm6328-clock.h | 25 ++++++++++ include/dt-bindings/clock/bcm6358-clock.h | 24 +++++++++ 13 files changed, 219 insertions(+) create mode 100644 drivers/clk/clk_bcm6345.c create mode 100644 include/dt-bindings/clock/bcm63268-clock.h create mode 100644 include/dt-bindings/clock/bcm6328-clock.h create mode 100644 include/dt-bindings/clock/bcm6358-clock.h -- 2.1.4

3 17

[U-Boot] [PATCH 0/3] dm: led: add BCM6358 serial leds support
by Álvaro Fernández Rojas 10 May '17

10 May '17

BCM6358 supports controlling serial LEDs (74x164) both by using spi-gpio or its LEDs controller. Álvaro Fernández Rojas (3): dm: led: add BCM6358 led driver mips: bmips: add bcm6358-led driver support for BCM6358 mips: bmips: add NeufBox 4 (Sercomm) board arch/mips/dts/brcm,bcm6358.dtsi | 9 ++ arch/mips/dts/sfr,nb4-ser.dts | 93 ++++++++++++++++ board/sfr/nb4_ser/Kconfig | 12 ++ board/sfr/nb4_ser/MAINTAINERS | 6 + board/sfr/nb4_ser/Makefile | 5 + board/sfr/nb4_ser/nb4-ser.c | 7 ++ configs/sfr_nb4-ser_ram_defconfig | 52 +++++++++ drivers/led/Kconfig | 7 ++ drivers/led/Makefile | 1 + drivers/led/led_bcm6358.c | 227 ++++++++++++++++++++++++++++++++++++++ include/configs/sfr_nb4_ser.h | 20 ++++ 11 files changed, 439 insertions(+) create mode 100644 arch/mips/dts/sfr,nb4-ser.dts create mode 100644 board/sfr/nb4_ser/Kconfig create mode 100644 board/sfr/nb4_ser/MAINTAINERS create mode 100644 board/sfr/nb4_ser/Makefile create mode 100644 board/sfr/nb4_ser/nb4-ser.c create mode 100644 configs/sfr_nb4-ser_ram_defconfig create mode 100644 drivers/led/led_bcm6358.c create mode 100644 include/configs/sfr_nb4_ser.h -- 2.1.4

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