May 2017 - U-Boot

[U-Boot] [PATCH 00/16] i.MX6: Engicam: Move common board code
by Jagan Teki 11 May '17

11 May '17

From: Jagan Teki <jagan(a)amarulasolutions.com> Engicam boards have some common code, so move them as (1) SPL board_init_f and UART MUX init to common/spl.c (2) board_init, dram_init, board_late_init and mmc_late_init to common/board.c This series also add board_fit_config_name_match to make SPL to pick suitable fdt, so reduced few defconifg files. thanks! Jagan. Jagan Teki (16): icorem6: Add modeboot env via board_late_init icorem6: Add mmc_late_init geam6ul: Add modeboot env via board_late_init geam6ul: Add mmc_late_init engicam: Set fdt_file env during run-time icorem6: Make SPL to pick suitable fdt engicam: Move uart mux init to SPL icorem6: Use proper iomux_ddr_regs drive strength values icorem6: Use drive strength macros i.MX6UL: geam6ul: Add SETUP_IOMUX_PADS isiot: Fix to use usdhc2_pads for mmc2 i.MX6UL: isiot: Add SETUP_IOMUX_PADS icorem6[_rqs]: Move the spl code common geam6/isiot: Move the spl code common engicam: common: Move common board code engicam: common: Move board_late_init arch/arm/cpu/armv7/mx6/Kconfig | 6 + arch/arm/include/asm/imx-common/iomux-v3.h | 6 + board/engicam/common/Makefile | 7 + board/engicam/common/board.c | 82 +++++ board/engicam/common/board.h | 12 + board/engicam/common/spl.c | 393 +++++++++++++++++++++ board/engicam/geam6ul/geam6ul.c | 206 ++--------- board/engicam/icorem6/MAINTAINERS | 6 +- board/engicam/icorem6/icorem6.c | 330 +---------------- board/engicam/icorem6_rqs/MAINTAINERS | 3 +- board/engicam/icorem6_rqs/icorem6_rqs.c | 352 +----------------- board/engicam/isiotmx6ul/isiotmx6ul.c | 261 +++----------- configs/imx6dl_icore_mmc_defconfig | 44 --- configs/imx6dl_icore_nand_defconfig | 45 --- configs/imx6dl_icore_rqs_mmc_defconfig | 41 --- configs/imx6q_icore_nand_defconfig | 45 --- ...e_mmc_defconfig => imx6qdl_icore_mmc_defconfig} | 2 +- ...c_defconfig => imx6qdl_icore_rqs_mmc_defconfig} | 2 +- configs/imx6ul_geam_mmc_defconfig | 1 - configs/imx6ul_geam_nand_defconfig | 1 - configs/imx6ul_isiot_emmc_defconfig | 1 - configs/imx6ul_isiot_mmc_defconfig | 1 - configs/imx6ul_isiot_nand_defconfig | 1 - include/configs/imx6qdl_icore.h | 39 +- include/configs/imx6qdl_icore_rqs.h | 1 - include/configs/imx6ul_geam.h | 38 +- include/configs/imx6ul_isiot.h | 1 - 27 files changed, 655 insertions(+), 1272 deletions(-) create mode 100644 board/engicam/common/Makefile create mode 100644 board/engicam/common/board.c create mode 100644 board/engicam/common/board.h create mode 100644 board/engicam/common/spl.c delete mode 100644 configs/imx6dl_icore_mmc_defconfig delete mode 100644 configs/imx6dl_icore_nand_defconfig delete mode 100644 configs/imx6dl_icore_rqs_mmc_defconfig delete mode 100644 configs/imx6q_icore_nand_defconfig rename configs/{imx6q_icore_mmc_defconfig => imx6qdl_icore_mmc_defconfig} (96%) rename configs/{imx6q_icore_rqs_mmc_defconfig => imx6qdl_icore_rqs_mmc_defconfig} (95%) -- 1.9.1

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[U-Boot] [PATCH] imx-common: rdc-sema: correct return value
by Peng Fan 11 May '17

11 May '17

When unlock, if caller is not the sema owner, return -EACCES, not 1. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/imx-common/rdc-sema.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/imx-common/rdc-sema.c b/arch/arm/imx-common/rdc-sema.c index 5df4e02..1d97ac8 100644 --- a/arch/arm/imx-common/rdc-sema.c +++ b/arch/arm/imx-common/rdc-sema.c @@ -94,7 +94,7 @@ int imx_rdc_sema_unlock(int per_id) reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); if ((reg & RDC_SEMA_GATE_GTFSM_MASK) != RDC_SEMA_PROC_ID) - return 1; /*Not the semaphore owner */ + return -EACCES; /*Not the semaphore owner */ writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); -- 2.6.2

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[U-Boot] [PATCH] imx-common: timer: clean up
by Peng Fan 11 May '17

11 May '17

Drop the unneeded code. lib/time.c use timebase_l/h. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/imx-common/timer.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index ee6eff2..9b01114 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -105,9 +105,6 @@ int timer_init(void) #endif __raw_writel(i, &cur_gpt->control); - gd->arch.tbl = __raw_readl(&cur_gpt->counter); - gd->arch.tbu = 0; - return 0; } -- 2.6.2

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[U-Boot] [PATCH] mx25pdk: Add fuse API support
by Fabio Estevam 11 May '17

11 May '17

From: Fabio Estevam <fabio.estevam(a)nxp.com> Select CONFIG_FSL_IIM and CONFIG_CMD_FUSE so that the fuse API can be used. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- include/configs/mx25pdk.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 4cee64d..eb64eda 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -103,6 +103,10 @@ #define CONFIG_RTC_IMXDI #define CONFIG_CMD_DATE +/* Fuse API support */ +#define CONFIG_FSL_IIM +#define CONFIG_CMD_FUSE + /* Ethernet Configs */ -- 2.7.4

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Re: [U-Boot] [PATCH] pinctrl: imx: fix memory leak
by Peng Fan 11 May '17

11 May '17

> -----Original Message----- > From: Lothar Waßmann [mailto:LW@KARO-electronics.de] > Sent: Thursday, May 11, 2017 5:13 PM > To: Peng Fan <peng.fan(a)nxp.com> > Cc: sjg(a)chromium.org; u-boot(a)lists.denx.de; Stefan Agner > <stefan.agner(a)toradex.com> > Subject: Re: [U-Boot] [PATCH] pinctrl: imx: fix memory leak > > Hi, > > On Thu, 11 May 2017 10:43:02 +0800 Peng Fan wrote: > > Each time set_state is called, a new piece memory will be allocated > > for pin_data, but not freed, this will incur memory leak. > > > > When error, the devm API could not free memory automatically. > > So need call devm_kfree when error. > > > > Issue reported by Coverity > > > > Signed-off-by: Peng Fan <peng.fan(a)nxp.com> > > Cc: Simon Glass <sjg(a)chromium.org> > > Cc: Stefan Agner <stefan.agner(a)toradex.com> > > Cc: Stefano Babic <sbabic(a)denx.de> > > --- > > drivers/pinctrl/nxp/pinctrl-imx.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c > > b/drivers/pinctrl/nxp/pinctrl-imx.c > > index f0321c4..31a28e1 100644 > > --- a/drivers/pinctrl/nxp/pinctrl-imx.c > > +++ b/drivers/pinctrl/nxp/pinctrl-imx.c > > @@ -53,6 +53,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, > struct udevice *config) > > if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins", > > pin_data, size >> 2)) { > > dev_err(dev, "Error reading pin data.\n"); > > + devm_kfree(pin_data); > > return -EINVAL; > > } > > > > @@ -78,6 +79,7 @@ static int imx_pinctrl_set_state(struct udevice > > *dev, struct udevice *config) > > > > if ((mux_reg == -1) || (conf_reg == -1)) { > > dev_err(dev, "Error mux_reg or conf_reg\n"); > > + devm_kfree(pin_data); > > return -EINVAL; > > } > > > > @@ -166,6 +168,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, > struct udevice *config) > > } > > } > > > > + devm_kfree(pin_data); > > + > > return 0; > > } > > > IMO 'devm'_kzalloc() doesn't make any sense here. > It would make sense for allocations that have the same lifetime as the 'struct > udevice', but not for a temporary buffer that is used within on function. Size is different for different fsl,pins group. So need to use devm_kzalloc. Thanks, Peng. > > > Lothar Waßmann

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[U-Boot] [PATCH] pinctrl: imx: fix memory leak
by Peng Fan 11 May '17

11 May '17

Each time set_state is called, a new piece memory will be allocated for pin_data, but not freed, this will incur memory leak. When error, the devm API could not free memory automatically. So need call devm_kfree when error. Issue reported by Coverity Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefan Agner <stefan.agner(a)toradex.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/pinctrl/nxp/pinctrl-imx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index f0321c4..31a28e1 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -53,6 +53,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins", pin_data, size >> 2)) { dev_err(dev, "Error reading pin data.\n"); + devm_kfree(pin_data); return -EINVAL; } @@ -78,6 +79,7 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) if ((mux_reg == -1) || (conf_reg == -1)) { dev_err(dev, "Error mux_reg or conf_reg\n"); + devm_kfree(pin_data); return -EINVAL; } @@ -166,6 +168,8 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) } } + devm_kfree(pin_data); + return 0; } -- 2.6.2

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[U-Boot] Cortex-A72 hangs after jumping from ARM Trusted Firmware to U-Boot?
by Masahiro Yamada 11 May '17

11 May '17

Hi. When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot) My UniPhier LD20 SoC (primary CPU = CA72) hangs in U-Boot. The same boot sequence works fine on a similar SoC, LD11 (primary CPU = CA53). I do not know why. Do you have a clue? A CA72-specific problem (errata)? After a while, I found a solution to make it work for CA72. Insert the following two lines in early boot stage of U-Boot. mrs x0, sctlr_el1 msr sctlr_el1, x0 The code above seems no effect because it just reads sctlr_el1 register, then writes back the value immediately. Surprisingly enough, it fixes the problem. I do not know why. I sent the following patch for my SoC: http://patchwork.ozlabs.org/patch/760988/ I am not sure if this is good. Anybody who has a clue? Thanks! -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH] ARM: uniphier: add weird workaround code for LD20
by Masahiro Yamada 11 May '17

11 May '17

When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS. The boot flow is as follows: BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot) This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20 SoC (Cortex-A72) hangs in U-Boot. The solution I found is to read sctlr_el1 and write back the value as-is. This should be no effect, but surprisingly fixes the problem and LD20 SoC boots. I do not know why. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/arm64/Makefile | 2 ++ arch/arm/mach-uniphier/arm64/lowlevel_init.S | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm/mach-uniphier/arm64/lowlevel_init.S diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile index eb34c20..3fde6b1 100644 --- a/arch/arm/mach-uniphier/arm64/Makefile +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -9,5 +9,7 @@ obj-y += mem_map.o ifdef CONFIG_ARMV8_MULTIENTRY obj-y += smp.o smp_kick_cpus.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o +else +obj-y += lowlevel_init.o endif endif diff --git a/arch/arm/mach-uniphier/arm64/lowlevel_init.S b/arch/arm/mach-uniphier/arm64/lowlevel_init.S new file mode 100644 index 0000000..a4255bf --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/lowlevel_init.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + /* + * I do not know why, but LD20 SoC (Cortex-A72) does not work + * without the following code. + */ + mrs x0, sctlr_el1 + msr sctlr_el1, x0 + ret +ENDPROC(lowlevel_init) -- 2.7.4

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[U-Boot] [PATCH v4 00/11] sunxi: sun5/7i: add the psci suspend function
by Antoine Tenart 11 May '17

11 May '17

Hi all, Respin this series that was sent in October 2016, with comments and new psci aware SoC taken into account. This series adds an implementation of the psci suspend function for both sun5i and sun7i. This was tested on Nextthing's CHIP, using cpuidle in Linux. As the sun5i does not have a GIC, I needed to remove some code from the generic psci code. To do this I added an ARM_GIC Kconfig option which needs to be selected by each SoC having a GIC. I already added the relevant lines for SoCs selecting ARCH_SUPPORT_PSCI. As this Kconfig option is currently only used in the psci code, it should be safe to add it even if all the SoCs having a GIC do not select it, as long as they don't have psci functions. On multi-core systems, we need to ensure all CPU are in psci suspend function to switch the cpu clk source. Likewise, the first CPU to exit the psci suspend function should restore the cpu clk source; and only the first one. This series adds a few atomic operation (with return support) in order to solve this problem. I used the Linux implementation. This series is based on sunxi/master (6e39de1b337e) and can be found on: https://github.com/atenart/u-boot sunxi/psci-suspend Thanks! Antoine Since v3: - Reworked the atomic functions with return support, based on the Linux implementation. - Do not disable LDO anymore. - Added some comments. - Poll the pll1 lock bit before switching to it. - Select CONFIG_ARM_GIC directly in CONFIG_TEGRA_COMMON. - Select ARM_GIC for mx7 and uniphier as well. Since v2: - Stopped putting the dram into self-refresh. - Removed pll2-7 disabling. - Added an atomic variable to only change the cpuclk source when all CPUs are in idle. - Did a similar implementation to be sure the first CPU to leave the idle mode switches back the cpuclk source to pll1. - Rebased on the latest master and updated the patches. Since v1: - Rebased on the latest master and updated the patches. - Fixed a compile warning I introduced in virt-v7.c - Added the missing ARM_GIC Kconfig options. - Fixed a commit message (removed 'HYP'). Antoine Tenart (11): arm: add atomic functions with return support arm: add the ARM_GIC configuration option sunxi: select ARM_GIC for sun[6789]i arm: select ARM_GIC for SoCs having a psci implementation tegra: select ARM_GIC for Tegra SoCs mx7: select ARM_GIC uniphier: select ARM_GIC arm: psci: protect GIC specific code with ARM_GIC sun5/7i: add an implementation of the psci suspend function sun5i: add defines used by the PSCI code sun5i: boot in non-secure mode by default arch/arm/Kconfig | 13 ++++ arch/arm/cpu/armv7/mx7/Kconfig | 1 + arch/arm/cpu/armv7/nonsec_virt.S | 6 ++ arch/arm/cpu/armv7/sunxi/Makefile | 9 ++- arch/arm/cpu/armv7/sunxi/psci.c | 40 +--------- arch/arm/cpu/armv7/sunxi/psci.h | 58 ++++++++++++++ arch/arm/cpu/armv7/sunxi/psci_suspend.c | 108 ++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-v7.c | 42 ++++++---- arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 + arch/arm/include/asm/atomic.h | 36 +++++++++ arch/arm/mach-tegra/Kconfig | 1 + arch/arm/mach-uniphier/Kconfig | 1 + board/sunxi/Kconfig | 12 +++ include/configs/sun5i.h | 2 + 14 files changed, 278 insertions(+), 53 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/psci.h create mode 100644 arch/arm/cpu/armv7/sunxi/psci_suspend.c -- 2.11.0

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[U-Boot] vitesse vsc8502 phy in uboot
by Sameer Arvikar 11 May '17

11 May '17

Hello, 1 . I am using vitesse vsc8502 phy and imx6 procesor , but i found that there is no driver for vsc8502 in uboot 2. Generic phy driver is detected ,but i want to change the driver to vitesse ,how to change phy driver (which files to change ) and is there any patch available for it Regards *Disclaimer* ------------------------------------------------------------ Notice: This e-mail and / or attachments (communication) may contain information that is confidential and proprietary to The Tata Power Company Limited, Strategic Engineering Division (Tata Power SED). If you are not the intended recipient of this communication, please do not use or disseminate the information contained therein, notify the sender by e-mail or telephone and delete the communication (permanently) from your system. Any information in this communication that does not relate to the official business of Tata Power SED shall be understood as neither given nor endorsed by it. Please note that e-mails are susceptible to change and Tata Power SED shall not be liable for the improper or incomplete transmission of the information contained in this communication nor for any delay in its receipt. This communication is not guaranteed to be free from computer viruses and it is recommended that you check for all viruses before download. Print this communication only if absolutely essential. Thank you for your co-operation. ------------------------------------------------------------

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