May 2017 - U-Boot

[U-Boot] [PATCH v2 0/5] Add Intel Arria 10 SoC FPGA driver
by tien.fong.chee＠intel.com 12 May '17

12 May '17

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This is the 2nd version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v1].This series is working on top of u-boot-socfpga-next branch http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/next. [1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg247788.html v1 -> v2 changes: ----------------- - Pulled the convert FPGA to kconfig patch out of this patchset, will submit as separate patch after this patchset. - Resolved duplicate fpgamgr_program_write() in both gen5 and arria10. Patchset history ---------------- [v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg247788.html Tien Fong Chee (5): arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset arm: socfpga: Restructure FPGA driver in the preparation to support A10. arm: socfpga: Move FPGA manager driver to FPGA driver arm: socfpga: Move the FPGA driver header from arch/arm to include/ arm: socfpga: Add FPGA driver support for Arria 10 arch/arm/mach-socfpga/Makefile | 1 - arch/arm/mach-socfpga/fpga_manager.c | 78 ---- arch/arm/mach-socfpga/include/mach/fpga_manager.h | 70 +-- .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 ++- .../include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/reset_manager_arria10.c | 6 +- arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +- arch/arm/mach-socfpga/system_manager_gen5.c | 2 +- drivers/Makefile | 1 + drivers/ddr/altera/sdram.c | 5 +- drivers/fpga/Makefile | 2 + drivers/fpga/socfpga.c | 242 +---------- drivers/fpga/socfpga_arria10.c | 482 +++++++++++++++++++++ drivers/fpga/{socfpga.c => socfpga_gen5.c} | 103 +++-- include/intel_socfpga/fpga_manager.h | 39 ++ include/intel_socfpga/fpga_manager_arria10.h | 105 +++++ .../intel_socfpga/fpga_manager_gen5.h | 69 ++- 17 files changed, 769 insertions(+), 512 deletions(-) delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%) create mode 100644 drivers/fpga/socfpga_arria10.c copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%) create mode 100644 include/intel_socfpga/fpga_manager.h create mode 100644 include/intel_socfpga/fpga_manager_arria10.h copy arch/arm/mach-socfpga/include/mach/fpga_manager.h => include/intel_socfpga/fpga_manager_gen5.h (57%) -- 2.2.0

3 17

[U-Boot] [PATCH] ARM64: zynqmp: Decrease MALLOC size for SPL
by Michal Simek 12 May '17

12 May '17

Decrease malloc size to 1MB from 256MB. Huge malloc space is adding huge delay in mem_malloc_init() because we are enabling CONFIG_SYS_MALLOC_CLEAR_ON_INIT which clear the whole malloc space. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 35ce0157b92b..7a3ccad74e81 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -299,7 +299,7 @@ # define CONFIG_ENV_MAX_ENTRIES 10 # define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000 +# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" -- 1.9.1

1 0

[U-Boot] [PATCH 1/5] arm64: zynqmp: Add support for QSPI boot
by Michal Simek 12 May '17

12 May '17

This patch is enabling support for SPL QSPI boot. First of all it is necessary to generate atf-spi.ub which is different format than atf-uboot.ub (this can be made as legacy image too) ADDR=`arm-xilinx-linux-gnueabi-readelf -a bl31.elf | grep "Entry point address" | cut -d ':' -f 2 | sed -e 's/^[ \t]*//'` aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin ./tools/mkimage -f auto -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR -n "atf1" -E -b arch/arm/dts/zynqmp-zcu102.dtb -d bl31.bin atf-uboot.ub ./tools/mkimage -A arm64 -T firmware -C none -O u-boot -a $ADDR -e $ADDR -n "atf-for-qspi" -E -d bl31.bin atf-spi.ub This patch is using this QSPI layout with offsets: 0 boot.bin 512k atf-ub 640k u-boot.bin 1280k u-boot.img Which corresponding by writing these images(read from MMC) mmcinfo sf probe load mmc 0 10000000 boot.bin sf erase 0 +$filesize sf write 10000000 0 $filesize load mmc 0 10000000 atf-spi.ub sf erase 0x80000 +$filesize sf write 10000000 0x80000 $filesize load mmc 0 10000000 u-boot.bin sf erase 0xa0000 +$filesize sf write 10000000 0xa0000 $filesize load mmc 0 10000000 u-boot.img sf erase 0x140000 +$filesize sf write 10000000 0x140000 $filesize For testing u-boot running in EL3 you can break atf-spi.ub like this: sf probe sf erase 0x80000 +4 Then u-boot.img is executed. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/spl.c | 5 +++++ arch/arm/dts/zynqmp.dtsi | 1 + include/configs/xilinx_zynqmp.h | 7 +++++++ 3 files changed, 13 insertions(+) diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 0a5f4306e822..c9fe260c8da6 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -96,6 +96,11 @@ u32 spl_boot_device(void) case SW_SATA_MODE: return BOOT_DEVICE_SATA; #endif +#ifdef CONFIG_SPL_SPI_SUPPORT + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + return BOOT_DEVICE_SPI; +#endif default: printf("Invalid Boot Mode:0x%x\n", bootmode); break; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 96118e31521a..6786fd44092d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -701,6 +701,7 @@ }; qspi: spi@ff0f0000 { + u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index c2e2a51f0faf..35ce0157b92b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -266,6 +266,13 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 + +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 + /* u-boot is like dtb */ #define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" #define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 -- 1.9.1

1 4

[U-Boot] [PATCH] powerpc, mpc8260: init bootflag before calling board_init_f()
by Heiko Schocher 12 May '17

12 May '17

in start.S we call board_init_f... board_init_f has a function parameter bootflag, which is not initialized when we call it, so we have random behaviour... set bootflag to value 0 before calling board_init_f. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- arch/powerpc/cpu/mpc8260/start.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index d255bde..bb23be6 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -194,6 +194,7 @@ in_flash: bl init_debug /* set up debugging stuff */ #endif + li r3, 0 /* parameter 1: bootflag */ bl board_init_f /* run 1st part of board init code (in Flash)*/ /* NOTREACHED - board_init_f() does not return */ -- 2.7.4

1 0

[U-Boot] [PATCH] microblaze: Build only DTBs for selected target
by Michal Simek 12 May '17

12 May '17

Adding more targets to repository requires some additional changes not simply just adding config file, defconfig and dts. This patch makes this process easier by building only particular DTB which is selected via defconfig that Makefile doesn't need to contain all dts files in the repository. Reported-by: Nathan Rossi <nathan(a)nathanrossi.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/microblaze/dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 5e70d9e1109e..f80d8fd8506d 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-y += microblaze-generic.dtb +dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb targets += $(dtb-y) -- 1.9.1

1 0

[U-Boot] [PATCH v3 00/31] ARM: i.MX6: SabreSD: Add dts support
by Jagan Teki 12 May '17

12 May '17

From: Jagan Teki <jagan(a)amarulasolutions.com> This series has full possible dts support for SabreSD DualLite, Quad and Quad Plus and DCD code for DualLite has added in SPL code. The main intention of this series is to add the dts node step by step and remove the legacy code at the end and to make the full functional dts. Changes for v3: - rebase on master - Added patch 'ARM: i.MX6: sabresd: Cleanup board code' - Added patch 'ARM: i.MX6DL: sabresd: Move DCD reginit on SPL' Changes for v2: - rebase on master - Added new-patches. U-Boot SPL 2017.03-33716-gcadc609 (Apr 06 2017 - 00:41:19) Trying to boot from MMC1 U-Boot 2017.03-33716-gcadc609 (Apr 06 2017 - 00:41:19 +0530) CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 28C Reset cause: POR Model: Freescale i.MX6 Quad Plus SABRE Smart Device Board DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 PCI: pcie phy link never came up No panel detected: default to Hannstar-XGA Display: Hannstar-XGA (1024x768) In: serial Out: serial Err: serial Net: eth0: ethernet@02188000 Hit any key to stop autoboot: 0 => => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver thermal [ ] |-- imx_thermal simple_bus [ + ] `-- soc simple_bus [ + ] |-- aips-bus@02000000 simple_bus [ ] | |-- spba-bus@02000000 gpio [ + ] | |-- gpio@0209c000 gpio [ + ] | |-- gpio@020a0000 gpio [ + ] | |-- gpio@020a4000 gpio [ + ] | |-- gpio@020a8000 gpio [ + ] | |-- gpio@020ac000 gpio [ + ] | |-- gpio@020b0000 gpio [ + ] | |-- gpio@020b4000 simple_bus [ ] | |-- anatop@020c8000 simple_bus [ ] | |-- snvs@020cc000 pinctrl [ + ] | `-- iomuxc@020e0000 pinconfig [ + ] | `-- imx6qdl-sabresd pinconfig [ + ] | |-- enetgrp pinconfig [ ] | |-- i2c1grp pinconfig [ ] | |-- i2c2grp pinconfig [ ] | |-- i2c3grp pinconfig [ ] | |-- uart1grp pinconfig [ ] | |-- usbotggrp pinconfig [ + ] | |-- usdhc2grp pinconfig [ + ] | |-- usdhc3grp pinconfig [ + ] | `-- usdhc4grp simple_bus [ + ] `-- aips-bus@02100000 usb [ ] |-- usb@02184000 usb [ ] |-- usb@02184200 eth [ + ] |-- ethernet@02188000 mmc [ + ] |-- usdhc@02194000 mmc [ + ] |-- usdhc@02198000 mmc [ + ] |-- usdhc@0219c000 i2c [ ] |-- i2c@021a0000 i2c [ ] |-- i2c@021a4000 pmic [ ] | `-- pfuze100@08 i2c [ ] `-- i2c@021a8000 Tested: UART, MMC, I2C, FEC(with basic ping) thanks! Jagan. Jagan Teki (31): ARM: i.MX6: sabresd: Fix README - s/of=/dev/sdbbs=1K/of=/dev/sdb bs=1K/ ARM: dts: i.MX6: Add imx6qdl-sabresd.dtsi ARM: dts: imx6qdl-sabresd: Add imx6q-sabresd.dts ARM: i.MX6: sabresd: Remove SPL_I2C_SUPPORT ARM: i.MX6Q: sabresd: Add initial devicetree support ARM: dts: imx6qdl-sabresd: Add imx6qp-sabresd.dts ARM: i.MX6QP: sabresd: Add initial devicetree support ARM: i.MX6: sabresd: Move CONFIG_SYS_I2C_MXC to defconfigs ARM: dts: imx6qdl-sabresd: Add I2C node's ARM: dts: imx6qdl-sabresd: Add PMIC pfuze100 node ARM: i.MX6: sabresd: Enable DM_I2C and DM_PMIC ARM: i.MX6: sabresd: defconfig move - CONFIG_USB_EHCI(_MX6) ARM: dts: imx6qdl-sabresd: Add usb host node ARM: dts: imx6qdl-sabresd: Add usb otg node ARM: i.MX6: sabresd: Enable CONFIG_DM_REGULATOR ARM: i.MX6: sabresd: Enable DM_USB ARM: dts: imx6qdl-sabresd: Add FEC node ARM: i.MX6: sabresd: Move CONFIG_FEC_MXC to defconfigs ARM: i.MX6: sabresd: Enable DM_ETH ARM: i.MX6: sabresd: Add dm_gpio_* for backlight ARM: i.MX6: sabresd: Add imx6_pcie_toggle_power ARM: i.MX6: sabresd: Add imx6_pcie_toggle_reset ARM: i.MX6DL: sabresd: Move DCD reginit on SPL ARM: dts: imx6qdl-sabresd: Add imx6dl-sabresd.dts ARM: i.MX6DL: sabresd: Add initial devicetree support ARM: i.MX6: sabresd: Drop legacy non-fdt code ARM: i.MX6: %s/mx6sabresd/imx6sabresd ARM: i.MX6: sabresd: Move DM_* and OF_CONTROL to arch Kconfig ARM: i.MX6: sabresd: Update README ARM: i.MX6: sabresd: Drop checkboard ARM: i.MX6: sabresd: Cleanup board code arch/arm/cpu/armv7/mx6/Kconfig | 10 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx6dl-sabresd.dts | 17 + arch/arm/dts/imx6q-sabresd.dts | 21 + arch/arm/dts/imx6qdl-sabresd.dtsi | 235 ++++++ arch/arm/dts/imx6qp-sabresd.dts | 85 +++ .../freescale/{mx6sabresd => imx6sabresd}/Kconfig | 4 +- board/freescale/imx6sabresd/MAINTAINERS | 8 + .../freescale/{mx6sabresd => imx6sabresd}/Makefile | 2 +- board/freescale/imx6sabresd/README | 84 +++ .../mx6sabresd.c => imx6sabresd/imx6sabresd.c} | 785 ++++++++++----------- board/freescale/mx6sabresd/MAINTAINERS | 8 - board/freescale/mx6sabresd/README | 103 --- board/freescale/mx6sabresd/mx6dlsabresd.cfg | 131 ---- board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg | 169 ----- ...lsabresd_defconfig => imx6dl_sabresd_defconfig} | 26 +- ...bresd_spl_defconfig => imx6q_sabresd_defconfig} | 13 +- ...qsabresd_defconfig => imx6qp_sabresd_defconfig} | 27 +- include/configs/{mx6sabresd.h => imx6sabresd.h} | 25 +- include/configs/mx6sabre_common.h | 3 +- 20 files changed, 882 insertions(+), 877 deletions(-) create mode 100644 arch/arm/dts/imx6dl-sabresd.dts create mode 100644 arch/arm/dts/imx6q-sabresd.dts create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi create mode 100644 arch/arm/dts/imx6qp-sabresd.dts rename board/freescale/{mx6sabresd => imx6sabresd}/Kconfig (70%) create mode 100644 board/freescale/imx6sabresd/MAINTAINERS rename board/freescale/{mx6sabresd => imx6sabresd}/Makefile (86%) create mode 100644 board/freescale/imx6sabresd/README rename board/freescale/{mx6sabresd/mx6sabresd.c => imx6sabresd/imx6sabresd.c} (69%) delete mode 100644 board/freescale/mx6sabresd/MAINTAINERS delete mode 100644 board/freescale/mx6sabresd/README delete mode 100644 board/freescale/mx6sabresd/mx6dlsabresd.cfg delete mode 100644 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg rename configs/{mx6dlsabresd_defconfig => imx6dl_sabresd_defconfig} (59%) rename configs/{mx6sabresd_spl_defconfig => imx6q_sabresd_defconfig} (82%) rename configs/{mx6qsabresd_defconfig => imx6qp_sabresd_defconfig} (57%) rename include/configs/{mx6sabresd.h => imx6sabresd.h} (71%) -- 1.9.1

3 36

[U-Boot] [PATCH 1/2] imx: mx6sxsabresd: drop SPL support
by Peng Fan 11 May '17

11 May '17

We never use it, so drop the support. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 167 ---------------------------- configs/mx6sxsabresd_spl_defconfig | 44 -------- 2 files changed, 211 deletions(-) delete mode 100644 configs/mx6sxsabresd_spl_defconfig diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 0460cd9..8468f1d 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -343,7 +343,6 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_SPL_BUILD int i, ret; /* @@ -387,47 +386,6 @@ int board_mmc_init(bd_t *bis) } return 0; -#else - struct src *src_regs = (struct src *)SRC_BASE_ADDR; - u32 val; - u32 port; - - val = readl(&src_regs->sbmr1); - - if ((val & 0xc0) != 0x40) { - printf("Not boot from USDHC!\n"); - return -EINVAL; - } - - port = (val >> 11) & 0x3; - printf("port %d\n", port); - switch (port) { - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - break; - case 2: - imx_iomux_v3_setup_multiple_pads( - usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - gpio_direction_input(USDHC3_CD_GPIO); - gpio_direction_output(USDHC3_PWR_GPIO, 1); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; - break; - case 3: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - gpio_direction_input(USDHC4_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; - break; - } - - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif } #ifdef CONFIG_FSL_QSPI @@ -546,128 +504,3 @@ int checkboard(void) return 0; } - -#ifdef CONFIG_SPL_BUILD -#include <libfdt.h> -#include <spl.h> -#include <asm/arch/mx6-ddr.h> - -const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_dqm2 = 0x00000028, - .dram_dqm3 = 0x00000028, - .dram_ras = 0x00000020, - .dram_cas = 0x00000020, - .dram_odt0 = 0x00000020, - .dram_odt1 = 0x00000020, - .dram_sdba2 = 0x00000000, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdclk_0 = 0x00000030, - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_sdqs2 = 0x00000028, - .dram_sdqs3 = 0x00000028, - .dram_reset = 0x00000020, -}; - -const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000020, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_ctlds = 0x00000020, - .grp_ddr_type = 0x000c0000, - .grp_b2ds = 0x00000028, - .grp_b3ds = 0x00000028, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00290025, - .p0_mpwldectrl1 = 0x00220022, - .p0_mpdgctrl0 = 0x41480144, - .p0_mpdgctrl1 = 0x01340130, - .p0_mprddlctl = 0x3C3E4244, - .p0_mpwrdlctl = 0x34363638, -}; - -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1600, - .density = 4, - .width = 32, - .banks = 8, - .rowaddr = 15, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - -static void ccgr_init(void) -{ - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - writel(0xFFFFFFFF, &ccm->CCGR0); - writel(0xFFFFFFFF, &ccm->CCGR1); - writel(0xFFFFFFFF, &ccm->CCGR2); - writel(0xFFFFFFFF, &ccm->CCGR3); - writel(0xFFFFFFFF, &ccm->CCGR4); - writel(0xFFFFFFFF, &ccm->CCGR5); - writel(0xFFFFFFFF, &ccm->CCGR6); - writel(0xFFFFFFFF, &ccm->CCGR7); -} - -static void spl_dram_init(void) -{ - struct mx6_ddr_sysinfo sysinfo = { - .dsize = mem_ddr.width/32, - .cs_density = 24, - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 2, - .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; - - mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - -void board_init_f(ulong dummy) -{ - /* setup AIPS and disable watchdog */ - arch_cpu_init(); - - ccgr_init(); - - /* iomux and setup of i2c */ - board_early_init_f(); - - /* setup GP timer */ - timer_init(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - /* load/boot image from boot device */ - board_init_r(NULL, 0); -} -#endif diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig deleted file mode 100644 index c08cada..0000000 --- a/configs/mx6sxsabresd_spl_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_TARGET_MX6SXSABRESD=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -# CONFIG_CMD_BMODE is not set -CONFIG_VIDEO=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SPL=y -CONFIG_SPL_EXT_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -CONFIG_CMD_GPIO=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_SPI_FLASH=y -CONFIG_PCI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -- 2.6.2

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Re: [U-Boot] [PATCH] pinctrl: imx: fix memory leak
by Peng Fan 11 May '17

11 May '17

> -----Original Message----- > From: Lothar Waßmann [mailto:LW@KARO-electronics.de] > Sent: Thursday, May 11, 2017 6:10 PM > To: Peng Fan <peng.fan(a)nxp.com> > Cc: sjg(a)chromium.org; u-boot(a)lists.denx.de; Stefan Agner > <stefan.agner(a)toradex.com> > Subject: Re: [U-Boot] [PATCH] pinctrl: imx: fix memory leak > > Hi, > > On Thu, 11 May 2017 09:22:22 +0000 Peng Fan wrote: > > > > > > > -----Original Message----- > > > From: Lothar Waßmann [mailto:LW@KARO-electronics.de] > > > Sent: Thursday, May 11, 2017 5:13 PM > > > To: Peng Fan <peng.fan(a)nxp.com> > > > Cc: sjg(a)chromium.org; u-boot(a)lists.denx.de; Stefan Agner > > > <stefan.agner(a)toradex.com> > > > Subject: Re: [U-Boot] [PATCH] pinctrl: imx: fix memory leak > > > > > > Hi, > > > > > > On Thu, 11 May 2017 10:43:02 +0800 Peng Fan wrote: > > > > Each time set_state is called, a new piece memory will be > > > > allocated for pin_data, but not freed, this will incur memory leak. > > > > > > > > When error, the devm API could not free memory automatically. > > > > So need call devm_kfree when error. > > > > > > > > Issue reported by Coverity > > > > > > > > Signed-off-by: Peng Fan <peng.fan(a)nxp.com> > > > > Cc: Simon Glass <sjg(a)chromium.org> > > > > Cc: Stefan Agner <stefan.agner(a)toradex.com> > > > > Cc: Stefano Babic <sbabic(a)denx.de> > > > > --- > > > > drivers/pinctrl/nxp/pinctrl-imx.c | 4 ++++ > > > > 1 file changed, 4 insertions(+) > > > > > > > > diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c > > > > b/drivers/pinctrl/nxp/pinctrl-imx.c > > > > index f0321c4..31a28e1 100644 > > > > --- a/drivers/pinctrl/nxp/pinctrl-imx.c > > > > +++ b/drivers/pinctrl/nxp/pinctrl-imx.c > > > > @@ -53,6 +53,7 @@ static int imx_pinctrl_set_state(struct udevice > > > > *dev, > > > struct udevice *config) > > > > if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins", > > > > pin_data, size >> 2)) { > > > > dev_err(dev, "Error reading pin data.\n"); > > > > + devm_kfree(pin_data); > > > > return -EINVAL; > > > > } > > > > > > > > @@ -78,6 +79,7 @@ static int imx_pinctrl_set_state(struct udevice > > > > *dev, struct udevice *config) > > > > > > > > if ((mux_reg == -1) || (conf_reg == -1)) { > > > > dev_err(dev, "Error mux_reg or conf_reg\n"); > > > > + devm_kfree(pin_data); > > > > return -EINVAL; > > > > } > > > > > > > > @@ -166,6 +168,8 @@ static int imx_pinctrl_set_state(struct > > > > udevice *dev, > > > struct udevice *config) > > > > } > > > > } > > > > > > > > + devm_kfree(pin_data); > > > > + > > > > return 0; > > > > } > > > > > > > IMO 'devm'_kzalloc() doesn't make any sense here. > > > It would make sense for allocations that have the same lifetime as > > > the 'struct udevice', but not for a temporary buffer that is used within on > function. > > > > Size is different for different fsl,pins group. So need to use devm_kzalloc. > > > You obviously did not understand what I meant! > Sure you need dynamic allocation, but it's complete nonsense to use the dev_- > variant here, since the memory is only used for this one function call and > deallocated immediately after use. > > There is no need to have it automatically released when the underlying udevice > is destroyed. Yeah. I thought when error, we could let devm_ to free the memory. But missed the point that each time set_state, need to free the memory. Regards, Peng. > > > Lothar Waßmann

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[U-Boot] [PATCH 0/7] Add Intel Arria 10 SoC FPGA driver
by tien.fong.chee＠intel.com 11 May '17

11 May '17

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This patchset adds FPGA driver to Intel Arria 10 SoC. This series is working on top of u-boot-socfpga-next branch http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/next. Tien Fong Chee (7): arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset arm: socfpga: Convert FPGA configuration to Kconfig method. arm: socfpga: Restructure FPGA driver in the preparation to support A10. arm: socfpga: Move FPGA manager driver to FPGA driver arm: socfpga: Move the FPGA driver header from arch to include directory arm: socfpga: Add Arria10 FPGA manager program assembly driver arm: socfpga: Add FPGA driver support for Arria 10 arch/arm/mach-socfpga/Makefile | 2 +- arch/arm/mach-socfpga/fpga_manager.c | 78 --- arch/arm/mach-socfpga/include/mach/fpga_manager.h | 65 +--- .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 69 ++-- .../include/mach/reset_manager_arria10.h | 2 +- arch/arm/mach-socfpga/lowlevel_init.S | 48 ++ arch/arm/mach-socfpga/reset_manager_arria10.c | 6 +- arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +- arch/arm/mach-socfpga/system_manager_gen5.c | 2 +- drivers/Makefile | 1 + drivers/ddr/altera/sdram.c | 7 +- drivers/fpga/Kconfig | 5 +- drivers/fpga/Makefile | 5 +- drivers/fpga/socfpga.c | 269 +----------- drivers/fpga/socfpga_arria10.c | 490 ++++++++++++++++++++ drivers/fpga/{socfpga.c => socfpga_gen5.c} | 75 ++- include/altera.h | 2 +- include/configs/socfpga_common.h | 3 - include/intel_socfpga/fpga_manager.h | 38 ++ include/intel_socfpga/fpga_manager_arria10.h | 107 +++++ .../intel_socfpga/fpga_manager_gen5.h | 69 ++-- 21 files changed, 831 insertions(+), 517 deletions(-) delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%) create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S create mode 100644 drivers/fpga/socfpga_arria10.c copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (86%) create mode 100644 include/intel_socfpga/fpga_manager.h create mode 100644 include/intel_socfpga/fpga_manager_arria10.h copy arch/arm/mach-socfpga/include/mach/fpga_manager.h => include/intel_socfpga/fpga_manager_gen5.h (57%) -- 1.7.7.4

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[U-Boot] [PATCH 1/2] imx: thermal: update imx6 thermal driver according new equation
by Peng Fan 11 May '17

11 May '17

>From IC guys: " After a thorough accuracy study of the Temp sense circuit, we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. " New equation: Tmeas = (Nmeas - n1) / slope + t1 + offset n1= fused room count t1= 25 offset=3.580661 slope= 0.4148468 – 0.0015423*n1 According the new equation, update the thermal driver. c1 and c2 changed to u64 type and update comments. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/thermal/imx_thermal.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 0509094..b159464 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -22,8 +22,9 @@ /* board will busyloop until this many degrees C below CPU max temperature */ #define TEMPERATURE_HOT_DELTA 5 /* CPU maxT - 5C */ #define FACTOR0 10000000 -#define FACTOR1 15976 -#define FACTOR2 4297157 +#define FACTOR1 15423 +#define FACTOR2 4148468 +#define OFFSET 3580661 #define MEASURE_FREQ 327 #define TEMPERATURE_MIN -40 #define TEMPERATURE_HOT 85 @@ -54,39 +55,42 @@ static int read_cpu_temperature(struct udevice *dev) struct thermal_data *priv = dev_get_priv(dev); u32 fuse = priv->fuse; int t1, n1; - u32 c1, c2; + u64 c1, c2; u64 temp64; /* * Sensor data layout: * [31:20] - sensor value @ 25C * We use universal formula now and only need sensor value @ 25C - * slope = 0.4297157 - (0.0015976 * 25C fuse) + * slope = 0.4445388 - (0.0016549 * 25C fuse) */ n1 = fuse >> 20; t1 = 25; /* t1 always 25C */ /* * Derived from linear interpolation: - * slope = 0.4297157 - (0.0015976 * 25C fuse) + * slope = 0.4445388 - (0.0016549 * 25C fuse) * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0 - * (Nmeas - n1) / (Tmeas - t1) = slope + * offset = 3.580661 + * offset = OFFSET / 1000000 + * (Nmeas - n1) / (Tmeas - t1 - offset) = slope * We want to reduce this down to the minimum computation necessary * for each temperature read. Also, we want Tmeas in millicelsius * and we don't want to lose precision from integer division. So... - * Tmeas = (Nmeas - n1) / slope + t1 - * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1 - * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1 - * Let constant c1 = (-1000 / slope) - * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1 - * Let constant c2 = n1 *c1 + 1000 * t1 - * milli_Tmeas = c2 - Nmeas * c1 + * Tmeas = (Nmeas - n1) / slope + t1 + offset + * milli_Tmeas = 1000000 * (Nmeas - n1) / slope + 1000000 * t1 + OFFSET + * milli_Tmeas = -1000000 * (n1 - Nmeas) / slope + 1000000 * t1 + OFFSET + * Let constant c1 = (-1000000 / slope) + * milli_Tmeas = (n1 - Nmeas) * c1 + 1000000 * t1 + OFFSET + * Let constant c2 = n1 *c1 + 1000000 * t1 + * milli_Tmeas = (c2 - Nmeas * c1) + OFFSET + * Tmeas = ((c2 - Nmeas * c1) + OFFSET) / 1000000 */ temp64 = FACTOR0; - temp64 *= 1000; + temp64 *= 1000000; do_div(temp64, FACTOR1 * n1 - FACTOR2); c1 = temp64; - c2 = n1 * c1 + 1000 * t1; + c2 = n1 * c1 + 1000000 * t1; /* * now we only use single measure, every time we read @@ -118,8 +122,8 @@ static int read_cpu_temperature(struct udevice *dev) >> TEMPSENSE0_TEMP_CNT_SHIFT; writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); - /* milli_Tmeas = c2 - Nmeas * c1 */ - temperature = (long)(c2 - n_meas * c1)/1000; + /* Tmeas = (c2 - Nmeas * c1 + OFFSET) / 1000000 */ + temperature = lldiv(c2 - n_meas * c1 + OFFSET, 1000000); /* power down anatop thermal sensor */ writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); -- 2.6.2

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