August 2014 - U-Boot

[U-Boot] [PATCH] Fman/mEMAC: mEMAC fix for 10G MAC and PHY
by shh.xie＠gmail.com 14 Nov '14

14 Nov '14

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> 1. use Payload length check disable when enable MAC; 2. add XGMII support for setting MAC interface mode; 3. only enable auto negotiation for Non-XGMII mode; 4. return 0xffff if clause 22 is used to read 10G phy_id; Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- arch/powerpc/include/asm/fsl_memac.h | 1 + drivers/net/fm/memac.c | 12 +++++++++--- drivers/net/fm/memac_phy.c | 2 ++ 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h index 4640e33..f84c1a9 100644 --- a/arch/powerpc/include/asm/fsl_memac.h +++ b/arch/powerpc/include/asm/fsl_memac.h @@ -159,6 +159,7 @@ struct memac { #define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ #define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ #define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN) +#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */ /* HASHTABLE_CTRL - Hashtable control register */ #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 592a67f..ceed261 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -38,7 +38,8 @@ static void memac_enable_mac(struct fsl_enet_mac *mac) { struct memac *regs = mac->base; - setbits_be32(&regs->command_config, MEMAC_CMD_CFG_RXTX_EN); + setbits_be32(&regs->command_config, + MEMAC_CMD_CFG_RXTX_EN | MEMAC_CMD_CFG_NO_LEN_CHK); } static void memac_disable_mac(struct fsl_enet_mac *mac) @@ -94,11 +95,16 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; + case PHY_INTERFACE_MODE_XGMII: + if_mode &= ~IF_MODE_MASK; + if_mode |= IF_MODE_XGMII; + break; default: break; } - /* Enable automatic speed selection */ - if_mode |= IF_MODE_EN_AUTO; + /* Enable automatic speed selection for Non-XGMII */ + if (type != PHY_INTERFACE_MODE_XGMII) + if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII) { if_mode &= ~IF_MODE_EN_AUTO; diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index de9c0e9..3fa91b3 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -71,6 +71,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, u32 c45 = 1; if (dev_addr == MDIO_DEVAD_NONE) { + if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) + return 0xffff; c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC); -- 1.8.0

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[U-Boot] [PATCH 0/9] net: rtl8169: Fix cache maintenance issues
by Thierry Reding 13 Nov '14

13 Nov '14

From: Thierry Reding <treding(a)nvidia.com> This series attempts to fix a long-standing problem in the rtl8169 driver (though the same problem may exist in other drivers as well). Let me first explain what exactly the issue is: The rtl8169 driver provides a set of RX and TX descriptors for the device to use. Once they're set up, the device is told about their location so that it can fetch the descriptors using DMA. The device will also write packet state back into these descriptors using DMA. For this to work properly, whenever a driver needs to access these descriptors it needs to invalidate the D-cache line(s) associated with them. Similarly when changes to the descriptor have been made by the driver, the cache lines need to be flushed to make sure the changes are visible to the device. The descriptors are 16 bytes in size. This causes problems when used on CPUs that have a cache-line size that is larger than 16 bytes. One example is the NVIDIA Tegra124 which has 64-byte cache-lines. That means that 4 descriptors fit into a single cache-line. So whenever the driver flushes a cache-line it has the potential to discard changes made to another descriptor by the DMA device. One typical symptom is that large transfers over TFTP will often not complete and hang somewhere midway because a device marked a packet received but the driver flushing the cache and causing the packet to be lost. Since the descriptors need to be consecutive in memory, I don't see a way to fix this other than to use uncached memory. Therefore the solution proposed in this patch series is to introduce a mechanism in U-Boot to allow a driver to allocate from a pool of uncached memory. Currently an implementation is provided only for ARM v7. The idea is that a region (of user-definable size) immediately below (taking into account architecture-specific alignment restrictions) the malloc() area is mapped uncacheable in the MMU. A driver can use the new noncached_alloc() function to allocate a chunk of memory from this pool dynamically for buffers that it can't or doesn't want to do any explicit cache-maintainance on, yet needs to be shared with DMA devices. Patches 1-3 are minor preparatory work. Patch 1 cleans up some coding style issues in the ARM v7 cache code and patch 2 uses more future-proof types for the mmu_set_region_dcache_behaviour() function arguments. Patch 3 is purely for debugging purposes. It will print out the region used by malloc() when DEBUG is enabled. This can be useful to see where the malloc() region is in the memory map (compared to the noncached region introduced in a later patch for example). Patch 4 implements the noncached API for ARM v7. It obtains the start of the malloc() area and places the noncached region immediately below it so that noncached_alloc() can allocate from it. During boot, the noncached area will be set up immediately after malloc(). Patch 5 enables noncached memory for all Tegra boards. It uses a 1 MiB chunk which should be plenty (it's also the minimum on ARM v7 because it matches the MMU section size and therefore the granularity at which U-Boot can set the cacheable attributes). Patch 6 is not really related but just something I stumbled across when going through the code. According to the top-level README file, network drivers are supposed to respect the CONFIG_SYS_RX_ETH_BUFFER. rtl8169 doesn't currently do that, so this patch fixes it. Patch 7 is the result of earlier rework that still aimed at solving the problem using explicit cache maintenance. rtl8169 hardware requires buffers to be aligned to 256 byte boundaries. The rtl8169 driver used to employ some trickery to make that work, but nowadays there are macros that can be used to the same effect, so this patch uses them and gets rid of the custom trickery. This patch also prints out a warning if it detects a potential caching issue (i.e. ARCH_DMA_MINALIGN > sizeof(struct RxDesc)). Patch 8 finally adds optional support for non-cached memory. When available the driver will now use the noncached API to obtain uncached buffers for the RX and TX descriptor rings. At the same time the cache-maintenance functions for the RX and TX descriptors become no-ops so that the code can work with or without the noncached API available. With all of the above in place, patch 9 adds support for RTL-8168/8111g as found on the NVIDIA Jetson TK1 board (which has a Tegra124 SoC). Note that this series also fixes the sporadic hangs of large TFTP transfers for earlier SoC generations of Tegra (Tegra20 and Tegra30), though they were less frequent there, probably caused by the cache-lines being 32 bytes rather than 64. Thierry Thierry Reding (9): ARM: cache_v7: Various minor cleanups ARM: cache-cp15: Use unsigned long for address and size malloc: Output region when debugging ARM: Implement non-cached memory support ARM: tegra: Enable non-cached memory net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER net: rtl8169: Properly align buffers net: rtl8169: Use non-cached memory if available net: rtl8169: Add support for RTL-8168/8111g README | 16 ++++++ arch/arm/cpu/armv7/cache_v7.c | 14 +++--- arch/arm/include/asm/system.h | 7 ++- arch/arm/lib/cache-cp15.c | 6 +-- arch/arm/lib/cache.c | 41 +++++++++++++++ common/board_r.c | 11 +++++ common/dlmalloc.c | 3 ++ drivers/net/rtl8169.c | 110 ++++++++++++++++++++++++++++++----------- include/configs/tegra-common.h | 1 + 9 files changed, 168 insertions(+), 41 deletions(-) -- 2.0.4

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[U-Boot] socfpga: initialize MMC
by Pavel Machek 10 Nov '14

10 Nov '14

Hi! Once ethernet changes I merged, I can rediff mmc changes for application. It will look something like this: Albert, can you apply the ethernet patch? I'd like to continue on top of it... Pavel diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 2f1c716..7af384e 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -14,3 +16,27 @@ int dram_init(void) + +#ifdef CONFIG_DWMMC +/* + * Initializes MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ + return altera_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 4, 0); +} +#endif diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h index f564046..9b488d9 100644 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -14,5 +14,8 @@ #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 #endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 34febf5..5902105 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_ALTERA_DWMMC) += altera_dw_mmc.o obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o diff --git a/drivers/mmc/altera_dw_mmc.c b/drivers/mmc/altera_dw_mmc.c new file mode 100644 index 0000000..b22dc45 --- /dev/null +++ b/drivers/mmc/altera_dw_mmc.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <dwmmc.h> +#include <asm/arch/dwmmc.h> +#include <errno.h> + +#define CLKMGR_PERPLLGRP_EN_REG (SOCFPGA_CLKMGR_ADDRESS + 0xA0) +#define CLKMGR_SDMMC_CLK_ENABLE (1 << 8) +#define SYSMGR_SDMMCGRP_CTRL_REG (SOCFPGA_SYSMGR_ADDRESS + 0x108) + +static char *ALTERA_NAME = "ALTERA DWMMC"; + +static void altera_dwmci_clksel(struct dwmci_host *host) +{ + unsigned int drvsel; + unsigned int smplsel; + + /* Disable SDMMC clock. */ + clrbits_le32(CLKMGR_PERPLLGRP_EN_REG, CLKMGR_SDMMC_CLK_ENABLE); + + /* Configures drv_sel and smpl_sel */ + drvsel = 3; + smplsel = 0; + + debug("%s: drvsel %d smplsel %d\n", __FUNCTION__, drvsel, smplsel); + writel((smplsel << 3) | drvsel, SYSMGR_SDMMCGRP_CTRL_REG); + + /* Enable SDMMC clock */ + setbits_le32(CLKMGR_PERPLLGRP_EN_REG, CLKMGR_SDMMC_CLK_ENABLE); +} + +int altera_dwmmc_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc failed!\n"); + return -ENOMEM; + } + + host->name = ALTERA_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = altera_dwmci_clksel; + host->dev_index = index; + host->bus_hz = 400000; + host->fifoth_val = MSIZE(0x2) | + RX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2 - 1) | + TX_WMARK(CONFIG_DWMMC_FIFO_DEPTH / 2); + + add_dwmci(host, host->bus_hz, host->bus_hz); + + return 0; +} + diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 0254249..189dcde 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -180,13 +183,30 @@ /* * FLASH */ #define CONFIG_SYS_NO_FLASH + +/* + * MMC support + */ +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_DWMMC 1 +#define CONFIG_ALTERA_DWMMC 1 +#define CONFIG_DWMMC_FIFO_DEPTH 1024 +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif /* CONFIG_MMC */ + /* * L4 OSC1 Timer 0 */ -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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[U-Boot] [PATCH] Added support for comments in input to mkenvimage.
by Dominik Muth 10 Nov '14

10 Nov '14

>From 4877c78a6b11ebf90fe25376f1362b12d233797a Mon Sep 17 00:00:00 2001 From: Dominik Muth <dominik.muth(a)bkvibro.com> Date: Thu, 28 Aug 2014 12:25:27 +0200 Subject: [PATCH] Added support for comments in input to mkenvimage. This patch adds support for comments in the input to mkenvimage, i.e. in the environment source: All lines starting with a # in the firs column will be ignored. Additionally empty lines will also be ignored. Signed-off-by: Dominik Muth <dominik.muth(a)bkvibro.com> --- tools/mkenvimage.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index bbd3041..4f75338 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -37,6 +37,8 @@ static void usage(const char *exec_name) "\t\tkey1=value1\n" "\t\tkey2=value2\n" "\t\t...\n" + "\tEmpty lines are skipped, and lines with a # in the first\n" + "\tcolumn are treated as comments (also skipped).\n" "\t-r : the environment has multiple copies in flash\n" "\t-b : the target is big endian (default is little endian)\n" "\t-p <byte> : fill the image with <byte> bytes instead of 0xff bytes\n" @@ -221,10 +223,9 @@ int main(int argc, char **argv) /* Replace newlines separating variables with \0 */ for (fp = 0, ep = 0 ; fp < filesize ; fp++) { if (filebuf[fp] == '\n') { - if (ep == 0) { + if (fp == 0 || filebuf[fp-1] == '\n') { /* - * Newlines at the beginning of the file ? - * Ignore them. + * Skip empty lines. */ continue; } else if (filebuf[fp-1] == '\\') { @@ -240,6 +241,10 @@ int main(int argc, char **argv) /* End of a variable */ envptr[ep++] = '\0'; } + } else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') { + /* Comment, skip the line. */ + while (++fp < filesize && filebuf[fp] != '\n') + continue; } else { envptr[ep++] = filebuf[fp]; } -- 1.7.9.5 ________________________________ Sitz der Gesellschaft / Registered Office: Darmstadt Handelsregister Darmstadt / Darmstadt Commercial Register No.: HRB 6803 Geschaeftsfuehrung / Managing Director: Torben Ekvall The Royal Bank of Scotland N.V., Frankfurt a.M., 1654012009 (BLZ 502 304 00) SWIFT-BIC: ABNADEFF FRA IBAN: DE21 5023 0400 1654 0120 09 UST-ID Nr. / UST-ID No.: DE 812 272 970 WEEE-Reg.-Nr. / WEEE-Reg.-No.: DE 69572330 Registered Office: Naerum Naerum Commercial Register No.: 15 38 05 94 Managing Director: Torben Ekvall Danske Bank, Account no.: 3001 3345212949 SWIFT Address: DABADKKK IBAN No.: DK94 3000 3345 2129 49 Der Inhalt dieser E-Mail ist ausschliesslich fuer den/die bezeichneten Empfaenger bestimmt. Wenn Sie nicht der vorgesehene Adressat dieser E-Mail oder dessen Vertreter sein sollen, so beachten Sie bitte, dass jede Form der Kenntnisnahme, Veroeffentlichung, Vervielfaeltigung oder Weitergabe des Inhalts dieser E-Mail unzulaessig ist. Wir bitten Sie, sich in diesem Fall mit dem Absender der E-Mail oder telefonisch unter +49 (0) 6151 428-1100 in Verbindung zu setzen. This e-mail is confidential and may be read, copied and used only by the intended recipient. If you have received it in error, please contact the sender immediately by return e-mail or by telephoning +49 (0) 6151 428-1100. Please then delete the e-mail and do not disclose its contents to any person.

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[U-Boot] [PATCH] Disable FLASH_AMLV256U support for TOP860 target
by Vasili Galka 28 Oct '14

28 Oct '14

TOP860 configuration assumes at most 128 flash sectors. Thus, the AMLV256U flash can't be supported. The existing code could result in memory corruption when writing to the flash_info->start[] array. Signed-off-by: Vasili Galka <vvv444(a)gmail.com> Cc: Wolfgang Denk <wd(a)denx.de> --- board/emk/common/flash.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c index ae5777c..4119b3b 100644 --- a/board/emk/common/flash.c +++ b/board/emk/common/flash.c @@ -324,6 +324,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info) } break; } +#ifndef CONFIG_TOP860 if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 && (FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3) { @@ -337,7 +338,8 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info) } break; } - +#endif + /* fall thru to here ! */ default: printf ("unknown AMD device=%x %x %x", -- 1.7.9

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[U-Boot] [PATCH 1/2] ARM: mxs: Enable DCDC converter for battery boot
by Marek Vasut 26 Oct '14

26 Oct '14

In case the board detected sufficient voltage for battery boot, make sure the DCDC converter is ON and the board is not running only from linregs, otherwise an instability will be observed. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 8ea45be..d25019a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -654,6 +654,8 @@ static void mxs_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + + mxs_power_enable_4p2(); } /** -- 1.8.4.rc3

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[U-Boot] [PATCH] usb/xhci: remove XHCI init code from other usb controllers
by Zhao Qiang 22 Oct '14

22 Oct '14

The patch with commit id "020bbcb76b5be0d5406d2ae7c26dbdb013ead812" adds some init codes for XHCI but not for other usb controllers. And it will causes a bug for EHCI. so use macro "#ifdef CONFIG_USB_XHCI" to run it just for XHCI. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- common/usb_hub.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/common/usb_hub.c b/common/usb_hub.c index ffac0e7..7f791f1 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -90,12 +90,16 @@ static void usb_hub_power_on(struct usb_hub_device *hub) int i; struct usb_device *dev; unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2; + +#ifdef CONFIG_USB_XHCI ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); unsigned short portstatus; int ret; +#endif dev = hub->pusb_dev; +#ifdef CONFIG_USB_XHCI /* * Enable power to the ports: * Here we Power-cycle the ports: aka, @@ -132,6 +136,7 @@ static void usb_hub_power_on(struct usb_hub_device *hub) continue; } } +#endif for (i = 0; i < dev->maxchild; i++) { usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); -- 1.8.5

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[U-Boot] [PATCH] arm: tegra: use architecture specific memcpy
by Marcel Ziswiler 20 Oct '14

20 Oct '14

Use architecture specific memcpy to speed up things. Signed-off-by: Marcel Ziswiler <marcel(a)ziswiler.com> --- include/configs/tegra-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 16f45f5..be1c7f5 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -109,6 +109,8 @@ #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#define CONFIG_USE_ARCH_MEMCPY + /*----------------------------------------------------------------------- * Physical Memory Map */ -- 1.9.3

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[U-Boot] tools-only build broken
by Ian Campbell 17 Oct '14

17 Oct '14

The tools-only target is currently broken: $ make CROSS_COMPILE=arm-linux-gnueabihf- tools-only CHK include/config/uboot.release /bin/sh: 1: cannot open include/config/auto.conf: No such file Makefile:1052: recipe for target 'include/config/uboot.release' failed make: *** [include/config/uboot.release] Error 2 This is because tools-only depends on $(version_h), depends on include/config/uboot.release, depends include/config/auto.conf. I think this is all due to the support for LOCALVERSION(_AUTO). I'm not sure how to reconcile this, since the version stuff fundamentally needs the .config. Perhaps sandbox could be used? Ian.

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[U-Boot] [PATCH] ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables
by Stephen Warren 15 Oct '14

15 Oct '14

From: Stephen Warren <swarren(a)nvidia.com> This pinmux tables currently omit any configuration for PCIe clk_req, wake, and rst pins, which in turn causes intermittent failures in U-Boot's PCIe support. Import an updated version of the pinmux tables which rectifies this. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index d338818a64eb..de4eb355982c 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -283,6 +283,11 @@ static const struct pmux_pingrp_config jetson_tk1_pingrps[] = { PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), + PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), -- 1.9.1

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