October 2013 - U-Boot

[U-Boot] TI xHCI updates
by Dan Murphy 10 Oct '13

10 Oct '13

This patch series contains the following changes - Moves the xhci-omap.h to a common location - Fixes a compilation issue on OMAP5 when xHCI is defined when patch "usb: new board-specific USB init interface" is applied - Moves the TI USB PHY code out of the xhci-omap.c file and into a new file called drivers/usb/phy/omap_usb_phy.c - Enables the dra7xx xHCI controller - Enables the AM437x xHCI controller - Move OMAP5 MAC creation out of USB and into misc_init so that usbethaddr is set on each boot or else the kernel sets a random MAC.

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[U-Boot] [PATCH] ARM: omap4-panda: Add MAC address creation for panda
by Dan Murphy 09 Oct '13

09 Oct '13

Add a MAC address create based on the OMAP die ID registers. Then poplulate the ethaddr enviroment variable so that the device tree alias can be updated prior to boot. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- arch/arm/include/asm/arch-omap4/omap.h | 4 ++++ board/ti/panda/panda.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 9129c0d..e35f51c 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -33,6 +33,10 @@ /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 +#define STD_FUSE_DIE_ID_0 0x4A002200 +#define STD_FUSE_DIE_ID_1 0x4A002208 +#define STD_FUSE_DIE_ID_2 0x4A00220c +#define STD_FUSE_DIE_ID_3 0x4A002210 #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index e838ffd..53f4c24 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -133,6 +133,7 @@ int misc_init_r(void) { int phy_type; u32 auxclk, altclksrc; + uint8_t device_mac[6]; /* EHCI is not supported on ES1.0 */ if (omap_revision() == OMAP4430_ES1_0) @@ -186,6 +187,21 @@ int misc_init_r(void) writel(altclksrc, &scrm->altclksrc); + if (!getenv("ethaddr")) { + /* + * create a fake MAC address from the processor ID code. + * first byte is 0x02 to signify locally administered. + */ + device_mac[0] = 0x02; + device_mac[1] = readl(STD_FUSE_DIE_ID_3) & 0xff; + device_mac[2] = readl(STD_FUSE_DIE_ID_2) & 0xff; + device_mac[3] = readl(STD_FUSE_DIE_ID_1) & 0xff; + device_mac[4] = readl(STD_FUSE_DIE_ID_0) & 0xff; + device_mac[5] = (readl(STD_FUSE_DIE_ID_0) >> 8) & 0xff; + + eth_setenv_enetaddr("ethaddr", device_mac); + } + return 0; } -- 1.7.9.5

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[U-Boot] [ANN] v2013.10-rc4
by Tom Rini 09 Oct '13

09 Oct '13

Hey all, I've put v2013.10-rc4 out, only a little later than I had hoped, but I wanted to get those PRs in for this. uploaded soon. At this point, we're just about ready to release so: 1) If you have a bugfix outstand please let me know (I know about the igep and pcm cpsw fixes, those are on my list) 2) If something is broken, please shout! Thanks all! -- Tom

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[U-Boot] [PATCH] Tegra: T1x4: SPI: Use a common name (t1x4) for SPI driver
by Tom Warren 09 Oct '13

09 Oct '13

Tegra124 is compatible w/T114 SPI, so try to commonize as much as possible. TEST=built all T1x4 boards, tested on Venice1 & 2 OK. There's no real binary change here, just names/includes. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- .../tegra114_spi.h => arch-tegra/tegra1x4_spi.h} | 6 +++--- drivers/spi/Makefile | 2 +- drivers/spi/fdt_spi.c | 22 ++++------------------ drivers/spi/{tegra114_spi.c => tegra1x4_spi.c} | 22 ++++------------------ 4 files changed, 12 insertions(+), 40 deletions(-) rename arch/arm/include/asm/{arch-tegra114/tegra114_spi.h => arch-tegra/tegra1x4_spi.h} (94%) rename drivers/spi/{tegra114_spi.c => tegra1x4_spi.c} (92%) diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra/tegra1x4_spi.h similarity index 94% rename from arch/arm/include/asm/arch-tegra114/tegra114_spi.h rename to arch/arm/include/asm/arch-tegra/tegra1x4_spi.h index 48197bc..93aa9ac 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h +++ b/arch/arm/include/asm/arch-tegra/tegra1x4_spi.h @@ -22,8 +22,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA114_SPI_H_ -#define _TEGRA114_SPI_H_ +#ifndef _TEGRA1x4_SPI_H_ +#define _TEGRA1x4_SPI_H_ #include <asm/types.h> @@ -38,4 +38,4 @@ void tegra114_spi_cs_deactivate(struct spi_slave *slave); int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags); -#endif /* _TEGRA114_SPI_H_ */ +#endif /* _TEGRA1x4_SPI_H_ */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 91d24ce..8b72cf9 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -37,7 +37,7 @@ COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o -COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o +COBJS-$(CONFIG_TEGRA114_SPI) += tegra1x4_spi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c index 58f139a..ee1b9f7 100644 --- a/drivers/spi/fdt_spi.c +++ b/drivers/spi/fdt_spi.c @@ -1,24 +1,10 @@ /* * Common fdt based SPI driver front end * - * Copyright (c) 2013 NVIDIA Corporation + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> * - * See file CREDITS for list of people who contributed to this - * project. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> @@ -29,7 +15,7 @@ #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra20/tegra20_sflash.h> #include <asm/arch-tegra20/tegra20_slink.h> -#include <asm/arch-tegra114/tegra114_spi.h> +#include <asm/arch-tegra/tegra1x4_spi.h> #include <spi.h> #include <fdtdec.h> diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra1x4_spi.c similarity index 92% rename from drivers/spi/tegra114_spi.c rename to drivers/spi/tegra1x4_spi.c index 4d2af48..2742443 100644 --- a/drivers/spi/tegra114_spi.c +++ b/drivers/spi/tegra1x4_spi.c @@ -1,24 +1,10 @@ /* * NVIDIA Tegra SPI controller (T114 and later) * - * Copyright (c) 2010-2013 NVIDIA Corporation + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * See file CREDITS for list of people who contributed to this - * project. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> @@ -27,7 +13,7 @@ #include <asm/gpio.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra114/tegra114_spi.h> +#include <asm/arch-tegra/tegra1x4_spi.h> #include <spi.h> #include <fdtdec.h> -- 1.8.1.5

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[U-Boot] [PATCH 0/4] arm64: rela relocation
by Scott Wood 09 Oct '13

09 Oct '13

This lets us remove the manual relocation stuff from the arm64 patchset (the symbol itself is removed by this patchset, but not all the new manual relocations added by the arm64 patchset). I'm not terribly happy with the way relocate-rela is now, versus something cleaner that operates on the ELF file, but it's good enough for now and waiting longer to get rid of the manual relocations would be worse. This patchset is based on David's arm64 patchset v13. David, the first two patches should be applied before your arm64 patches. Maybe the fourth as well (except for the removal of the arm64 ifdef you added, which would then need to be squashed with your patch). The third patch should be squashed with your patches (plus you should remove the manual relocs). Scott Wood (4): arm64: Add tool to statically apply RELA relocations arm64: Turn u-boot.bin back into an ELF file after relocate-rela arm64: Non-manual relocation arm64: Make checkarmreloc accept arm64 relocations Makefile | 39 ++++++-- arch/arm/config.mk | 4 - arch/arm/cpu/armv8/config.mk | 1 - arch/arm/cpu/armv8/u-boot.lds | 32 +++++-- arch/arm/include/asm/config.h | 5 -- arch/arm/lib/crt0_64.S | 7 +- arch/arm/lib/relocate_64.S | 41 ++++----- include/configs/vexpress_aemv8a.h | 3 + tools/Makefile | 6 ++ tools/relocate-rela.c | 185 ++++++++++++++++++++++++++++++++++++++ 10 files changed, 276 insertions(+), 47 deletions(-) create mode 100644 tools/relocate-rela.c -- 1.8.1.2

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[U-Boot] [PATCH V2 0/6] SMDK5420: Add S2MPS11 pmic support to SMDK5420
by Leela Krishna Amudala 09 Oct '13

09 Oct '13

This patchset adds support for S2MPS11 pmic on SMDK5420 This patchset has dependency on Rajeshwari's base patchset: [V4] EXYNOS5420: Add SMDK5420 board support http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/170582 Also, for testing we need Naveen's i2c patchset as well: i2c: improve s3c24x0 with High-speed and new SYS_I2C framework support http://www.mail-archive.com/u-boot@lists.denx.de/msg122679.html Changes since V1: - In patch "exynos: Use common pmic_reg_update() definition" moved pmic_reg_update() from drivers/power/power_i2c.c to power_core.c suggested by Lukasz Majewski <l.majewski(a)samsung.com> - Changed the License details to GPL 2.0+ license for below pathces SMDK5420: S2MPS11: Adds the register settings for S2MPS11 exynos: Add a common DT based PMIC driver initialization - corrected the typo error in "config: SMDK5420: Enable S2MPS11 pmic" patch header Leela Krishna Amudala (6): exynos: Use common pmic_reg_update() definition power: Explicitly select pmic device's bus FDT: Exynos5420: Add compatible srings for PMIC SMDK5420: S2MPS11: Adds the register settings for S2MPS11 exynos: Add a common DT based PMIC driver initialization config: SMDK5420: Enable S2MPS11 pmic board/samsung/common/board.c | 39 ++++++----- drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pmic_common.c | 97 ++++++++++++++++++++++++++ drivers/power/power_core.c | 33 +++++++++ drivers/power/power_i2c.c | 62 +++++++++++++++-- include/configs/smdk5420.h | 4 ++ include/fdtdec.h | 1 + include/power/pmic.h | 35 ++++++++++ include/power/s2mps11_pmic.h | 141 ++++++++++++++++++++++++++++++++++++++ lib/fdtdec.c | 1 + 10 files changed, 391 insertions(+), 23 deletions(-) create mode 100644 drivers/power/pmic/pmic_common.c create mode 100644 include/power/s2mps11_pmic.h -- 1.7.10.4

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[U-Boot] [PATCH v4] spi: Add support SH Quad SPI driver
by Jagannadha Sutradharudu Teki 09 Oct '13

09 Oct '13

From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp(a)renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> --- Changes for v4: - Added tabs - Added comments - Added sh_qspi_init() Changes for v3: - Change Queued to Quad. - Remove path of file from file header. - Use read* and write* directly instead of sh_qspi_write* sh_qspi_read*. - Change driver format. Changes for v2: - "SH QSPI" to "SH QSPI (Queued SPI)". - Remove magic number. drivers/spi/Makefile | 1 + drivers/spi/sh_qspi.c | 248 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 249 insertions(+) create mode 100644 drivers/spi/sh_qspi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 91d24ce..c44f851 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o +COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c new file mode 100644 index 0000000..6872142 --- /dev/null +++ b/drivers/spi/sh_qspi.c @@ -0,0 +1,248 @@ +/* + * SH QSPI (Quad SPI) driver + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> + +/* SH QSPI register bit masks <REG>_<BIT> */ +#define SPCR_MSTR 0x08 +#define SPCR_SPE 0x40 +#define SPSR_SPRFF 0x80 +#define SPSR_SPTEF 0x20 +#define SPPCR_IO3FV 0x04 +#define SPPCR_IO2FV 0x02 +#define SPPCR_IO1FV 0x01 +#define SPBDCR_RXBC0 (1 << 0) +#define SPCMD_SCKDEN (1 << 15) +#define SPCMD_SLNDEN (1 << 14) +#define SPCMD_SPNDEN (1 << 13) +#define SPCMD_SSLKP (1 << 7) +#define SPCMD_BRDV0 (1 << 2) +#define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \ + SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \ + SPCMD_BRDV0 +#define SPBFCR_TXRST (1 << 7) +#define SPBFCR_RXRST (1 << 6) + +/* SH QSPI register set */ +struct sh_qspi_regs { + unsigned char spcr; + unsigned char sslp; + unsigned char sppcr; + unsigned char spsr; + unsigned long spdr; + unsigned char spscr; + unsigned char spssr; + unsigned char spbr; + unsigned char spdcr; + unsigned char spckd; + unsigned char sslnd; + unsigned char spnd; + unsigned char dummy0; + unsigned short spcmd0; + unsigned short spcmd1; + unsigned short spcmd2; + unsigned short spcmd3; + unsigned char spbfcr; + unsigned char dummy1; + unsigned short spbdcr; + unsigned long spbmul0; + unsigned long spbmul1; + unsigned long spbmul2; + unsigned long spbmul3; +}; + +struct sh_qspi_slave { + struct spi_slave slave; + struct sh_qspi_regs *regs; +}; + +static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave) +{ + return container_of(slave, struct sh_qspi_slave, slave); +} + +static void sh_qspi_init(struct sh_qspi_slave *ss) +{ + /* QSPI initialize */ + writeb(SPCR_MSTR, &ss->regs->spcr); + writeb(0x00, &ss->regs->sslp); + writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr); + + /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */ + writeb(0x01, &ss->regs->spbr); + + writeb(0x00, &ss->regs->spdcr); + writeb(0x00, &ss->regs->spckd); + writeb(0x00, &ss->regs->sslnd); + writeb(0x00, &ss->regs->spnd); + writew(SPCMD_INIT1, &ss->regs->spcmd0); + writew(SPCMD_INIT2, &ss->regs->spcmd0); + writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spscr); + writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr); +} + +static int sh_qspi_xfer(struct sh_qspi_slave *ss, unsigned char *tdata, + unsigned char *rdata, unsigned long flags) +{ + while (!(readb(&ss->regs->spsr) & SPSR_SPTEF)) { + if (ctrlc()) + return 1; + udelay(10); + } + + writeb(*tdata, (unsigned char *)(&ss->regs->spdr)); + + while ((readw(&ss->regs->spbdcr) != SPBDCR_RXBC0)) { + int i = 100; + + if (ctrlc()) + return 1; + while (i--) + ; + } + + while (!(readb(&ss->regs->spsr) & SPSR_SPRFF)) { + if (ctrlc()) + return 1; + udelay(10); + } + + *rdata = readb((unsigned char *)(&ss->regs->spdr)); + + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct sh_qspi_slave *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs); + if (!ss) { + printf("SPI_error: Fail to allocate sh_qspi_slave\n"); + return NULL; + } + + ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE; + + /* Init SH QSPI */ + sh_qspi_init(ss); + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct sh_qspi_slave *spi = to_sh_qspi(slave); + + free(spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct sh_qspi_slave *ss = to_sh_qspi(slave); + unsigned long nbyte; + int ret = 0; + unsigned char *tdata, *rdata, dtdata = 0, drdata; + + if (dout == NULL && din == NULL) { + if (flags & SPI_XFER_END) + writeb(SPCR_MSTR, &ss->regs->spcr); + return 0; + } + + if (bitlen % 8) { + printf("%s: bitlen is not 8bit alined %d", __func__, bitlen); + return 1; + } + + nbyte = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + unsigned long *spbmul0 = &ss->regs->spbmul0; + writeb(SPCR_MSTR, &ss->regs->spcr); + + writew(SPCMD_INIT1, &ss->regs->spcmd0); + + if (flags & SPI_XFER_END) + writel(nbyte, spbmul0); + else + /* Set 1048576 byte */ + writel(0x100000, spbmul0); + + writeb(SPBFCR_TXRST|SPBFCR_RXRST, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spbfcr); + writeb(0x00, &ss->regs->spscr); + writeb(SPCR_SPE|SPCR_MSTR, &ss->regs->spcr); + } + + if (dout != NULL) + tdata = (unsigned char *)dout; + else + tdata = &dtdata; + + if (din != NULL) + rdata = din; + else + rdata = &drdata; + + while (nbyte > 0) { + ret = sh_qspi_xfer(ss, tdata, rdata, flags); + if (ret) + break; + if (dout != NULL) + tdata++; + if (din != NULL) + rdata++; + nbyte--; + } + + if (flags & SPI_XFER_END) + writeb(SPCR_MSTR, &ss->regs->spcr); + + return ret; +} -- 1.8.3

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[U-Boot] [PATCH] mpc85xx: Fix the offset of register address error
by Tang Yuantian 09 Oct '13

09 Oct '13

From: Tang Yuantian <yuantian.tang(a)freescale.com> The offset of register address within GPIO module is just CONFIG_SYS_MPC85xx_GPIO_ADDR, no reason to add 0xc00. Signed-off-by: Tang Yuantian <Yuantian.Tang(a)freescale.com> --- arch/powerpc/include/asm/mpc85xx_gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 3d11884..87bb4a0 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -20,7 +20,7 @@ static inline void mpc85xx_gpio_set(unsigned int mask, unsigned int dir, unsigned int val) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* First mask off the unwanted parts of "dir" and "val" */ dir &= mask; @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios) static inline unsigned int mpc85xx_gpio_get(unsigned int mask) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* Read the requested values */ return in_be32(&gpio->gpdat) & mask; -- 1.8.0

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[U-Boot] Difference between CONFIG_SYS_TEXT_BASE and _start
by Djoker 09 Oct '13

09 Oct '13

Hi Everyone, I have a armv7 board and am seeing a discrepancy. In my board file I have defined: #define CONFIG_SYS_TEXT_BASE 0x67000004 After I build the ub-boot binary, I ran "nm u-boot | grep -w _start". It returned the following: 67000020 T _start Would anyone know why there is a difference in the values of _start and CONFIG_SYS_TEXT_BASE ? I thought they were the same, please correct me if wrong ? Thanks, ~vj

1 0

[U-Boot] [PATCH] arm: Tegra: T114: Use common tegra1x4- includes in arch-tegra
by Tom Warren 09 Oct '13

09 Oct '13

A previous commit created common arch-tegra/tegra1x4-xxx header files for T124, based on the existing T114 headers (HW is nearly 100% compatible for most blocks). Now that T124 support is in, move T114 over to use those common headers (which are actually copies of the T114 headers). Some headers aren't shared, such as clk_rst.h, gpio.h, pmc.h, etc. as they have extra regs/bits for T124. Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- arch/arm/include/asm/arch-tegra114/ahb.h | 13 + arch/arm/include/asm/arch-tegra114/clock-tables.h | 15 +- arch/arm/include/asm/arch-tegra114/clock.h | 21 +- arch/arm/include/asm/arch-tegra114/emc.h | 13 + arch/arm/include/asm/arch-tegra114/flow.h | 30 +- arch/arm/include/asm/arch-tegra114/funcmux.h | 15 +- arch/arm/include/asm/arch-tegra114/fuse.h | 13 + arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 78 +---- arch/arm/include/asm/arch-tegra114/gpio.h | 15 +- arch/arm/include/asm/arch-tegra114/hardware.h | 15 +- arch/arm/include/asm/arch-tegra114/pinmux.h | 15 +- arch/arm/include/asm/arch-tegra114/pmc.h | 343 ++++++++++++++++++++++ arch/arm/include/asm/arch-tegra114/pmu.h | 18 +- arch/arm/include/asm/arch-tegra114/spl.h | 15 +- arch/arm/include/asm/arch-tegra114/sysctr.h | 30 +- arch/arm/include/asm/arch-tegra114/tegra.h | 15 +- arch/arm/include/asm/arch-tegra114/usb.h | 153 +--------- 17 files changed, 428 insertions(+), 389 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra114/ahb.h create mode 100644 arch/arm/include/asm/arch-tegra114/emc.h create mode 100644 arch/arm/include/asm/arch-tegra114/fuse.h create mode 100644 arch/arm/include/asm/arch-tegra114/pmc.h diff --git a/arch/arm/include/asm/arch-tegra114/ahb.h b/arch/arm/include/asm/arch-tegra114/ahb.h new file mode 100644 index 0000000..a65943b --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/ahb.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_AHB_H_ +#define _TEGRA114_AHB_H_ + +#include <asm/arch-tegra/tegra1x4_ahb.h> + +#endif /* _TEGRA114_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index 19b8acf..2df960b 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ /* Tegra114 clock PLL tables */ diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h index abbefcd..b64d803 100644 --- a/arch/arm/include/asm/arch-tegra114/clock.h +++ b/arch/arm/include/asm/arch-tegra114/clock.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ /* Tegra114 clock control functions */ @@ -19,10 +10,6 @@ #ifndef _TEGRA114_CLOCK_H_ #define _TEGRA114_CLOCK_H_ -#include <asm/arch-tegra/clock.h> - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 28 -#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +#include <asm/arch-tegra/tegra1x4_clock.h> #endif /* _TEGRA114_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/emc.h b/arch/arm/include/asm/arch-tegra114/emc.h new file mode 100644 index 0000000..82db639 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/emc.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_EMC_H_ +#define _TEGRA114_EMC_H_ + +#include <asm/arch-tegra/tegra1x4_emc.h> + +#endif /* _TEGRA114_EMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h index c7eb051..d8f36e7 100644 --- a/arch/arm/include/asm/arch-tegra114/flow.h +++ b/arch/arm/include/asm/arch-tegra114/flow.h @@ -1,35 +1,13 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_FLOW_H_ #define _TEGRA114_FLOW_H_ -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 xrq_events; - u32 halt_cpu1_events; - u32 cpu1_csr; - u32 halt_cpu2_events; - u32 cpu2_csr; - u32 halt_cpu3_events; - u32 cpu3_csr; - u32 cluster_control; -}; +#include <asm/arch-tegra/tegra1x4_flow.h> #endif /* _TEGRA114_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h index 7f48f25..b9dd62d 100644 --- a/arch/arm/include/asm/arch-tegra114/funcmux.h +++ b/arch/arm/include/asm/arch-tegra114/funcmux.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ /* Tegra114 high-level function multiplexing */ diff --git a/arch/arm/include/asm/arch-tegra114/fuse.h b/arch/arm/include/asm/arch-tegra114/fuse.h new file mode 100644 index 0000000..a21a9a2 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/fuse.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_FUSE_H_ +#define _TEGRA114_FUSE_H_ + +#include <asm/arch-tegra/tegra1x4_fuse.h> + +#endif /* _TEGRA114_FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index 41ce677..d7f1ef2 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -1,83 +1,13 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_GP_PADCTRL_H_ #define _TEGRA114_GP_PADCTRL_H_ -#include <asm/arch-tegra/gp_padctrl.h> - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ - u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ - u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ - u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 reserved1; /* 0x8C: */ - u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ - u32 reserved2[3]; /* 0xA4 - 0xAC: */ - u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ - u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ - u32 reserved3[9]; /* 0xC8-0xE8: */ - u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ - u32 reserved4[3]; /* 0xF0-0xF8: */ - u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ - u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ - u32 reserved5[3]; /* 0x104-0x10C: */ - u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ - u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ - u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ - u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ - u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ - u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ - u32 reserved6; /* 0x128: */ - u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ - u32 reserved7[2]; /* 0x130 - 0x134: */ - u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ - u32 reserved8[22]; /* 0x13C - 0x190: */ - u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ - u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ - u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ - u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ - u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ - u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ - u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ -}; - -/* SDMMC1/3 settings from section 27.5 of T114 TRM */ -#define SDIOCFG_DRVUP_SLWF 0 -#define SDIOCFG_DRVDN_SLWR 0 -#define SDIOCFG_DRVUP 0x24 -#define SDIOCFG_DRVDN 0x14 +#include <asm/arch-tegra/tegra1x4_gp_padctrl.h> #endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h index 21853b6..1c92362 100644 --- a/arch/arm/include/asm/arch-tegra114/gpio.h +++ b/arch/arm/include/asm/arch-tegra114/gpio.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_GPIO_H_ diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h index c21fbb6..db629e3 100644 --- a/arch/arm/include/asm/arch-tegra114/hardware.h +++ b/arch/arm/include/asm/arch-tegra114/hardware.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_HARDWARE_H_ diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 9c22c08..3f0196e 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_PINMUX_H_ diff --git a/arch/arm/include/asm/arch-tegra114/pmc.h b/arch/arm/include/asm/arch-tegra114/pmc.h new file mode 100644 index 0000000..96476b0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/pmc.h @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_PMC_H_ +#define _TEGRA114_PMC_H_ + +/* Power Management Controller (APBDEV_PMC_) registers */ +struct pmc_ctlr { + uint pmc_cntrl; /* _CNTRL_0, offset 00 */ + uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ + uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ + uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ + uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ + uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ + uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ + uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ + uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ + uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ + uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ + uint pmc_clamp_status; /* _PMC_CLAMP_STATUS_0, offset 2C */ + uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ + uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ + uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ + uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ + uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ + uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ + uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ + uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ + + uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ + uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ + uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ + uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ + uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ + uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ + uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ + uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ + uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ + uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ + uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ + uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ + uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ + uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ + uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ + uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ + uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ + uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ + uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ + uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ + uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ + uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ + uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ + uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ + + uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ + uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ + uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ + uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ + uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ + uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ + + uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ + uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ + uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ + uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ + uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ + uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ + uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ + uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ + uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ + uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ + uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ + uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ + uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ + + uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ + uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ + uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ + uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ + uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ + uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ + uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ + uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ + uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ + uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ + uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ + uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ + uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ + uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ + uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ + uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ + uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ + uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ + uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ + + uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ + uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ + uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ + uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ + uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ + uint pmc_gate; /* _GATE_0, offset 15C */ + uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ + uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ + uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ + uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ + uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ + uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ + uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ + uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ + uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ + uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ + uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ + uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ + uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ + uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ + uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ + uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ + uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ + uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ + uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ + uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ + uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ + uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ + uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ + uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ + uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ + uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ + uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ + uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ + + uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ + uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ + uint pmc_reserved0; /* _RESERVED, offset 1D8 */ + uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ + uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ + uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ + uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ + uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ + uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ + uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ + uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ + uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ + + uint pmc_todo_0[9]; /* offset 200-220 */ + uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ + uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ + uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */ + uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */ + uint pmc_scratch45; + uint pmc_scratch46; + uint pmc_scratch47; + uint pmc_scratch48; + uint pmc_scratch49; + uint pmc_scratch50; + uint pmc_scratch51; + uint pmc_scratch52; + uint pmc_scratch53; + uint pmc_scratch54; + uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */ + uint pmc_scratch0_eco; /* _SCRATCH0_ECO, offset 260 */ + uint pmc_scratch1_eco; /* _SCRATCH1_ECO, offset 264 */ + uint pmc_scratch2_eco; /* _SCRATCH2_ECO, offset 268 */ + uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ + uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ + uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ + uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ + uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ + uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ + uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ + uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ + uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ + uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ + uint pmc_secure_scratch9; + uint pmc_secure_scratch10; + uint pmc_secure_scratch11; + uint pmc_secure_scratch12; + uint pmc_secure_scratch13; + uint pmc_secure_scratch14; + uint pmc_secure_scratch15; + uint pmc_secure_scratch16; + uint pmc_secure_scratch17; + uint pmc_secure_scratch18; + uint pmc_secure_scratch19; + uint pmc_secure_scratch20; + uint pmc_secure_scratch21; + uint pmc_secure_scratch22; + uint pmc_secure_scratch23; /* _SECURE_SCRATCH23_0, offset 33C */ + uint pmc_scratch56; /* _SCRATCH56_0, offset 340 */ + uint pmc_scratch57; + uint pmc_scratch58; + uint pmc_scratch59; + uint pmc_scratch60; + uint pmc_scratch61; + uint pmc_scratch62; + uint pmc_scratch63; + uint pmc_scratch64; + uint pmc_scratch65; + uint pmc_scratch66; + uint pmc_scratch67; + uint pmc_scratch68; + uint pmc_scratch69; + uint pmc_scratch70; + uint pmc_scratch71; + uint pmc_scratch72; + uint pmc_scratch73; + uint pmc_scratch74; + uint pmc_scratch75; + uint pmc_scratch76; + uint pmc_scratch77; + uint pmc_scratch78; + uint pmc_scratch79; + uint pmc_scratch80; + uint pmc_scratch81; + uint pmc_scratch82; + uint pmc_scratch83; + uint pmc_scratch84; + uint pmc_scratch85; + uint pmc_scratch86; + uint pmc_scratch87; + uint pmc_scratch88; + uint pmc_scratch89; + uint pmc_scratch90; + uint pmc_scratch91; + uint pmc_scratch92; + uint pmc_scratch93; + uint pmc_scratch94; + uint pmc_scratch95; + uint pmc_scratch96; + uint pmc_scratch97; + uint pmc_scratch98; + uint pmc_scratch99; + uint pmc_scratch100; + uint pmc_scratch101; + uint pmc_scratch102; + uint pmc_scratch103; + uint pmc_scratch104; + uint pmc_scratch105; + uint pmc_scratch106; + uint pmc_scratch107; + uint pmc_scratch108; + uint pmc_scratch109; + uint pmc_scratch110; + uint pmc_scratch111; + uint pmc_scratch112; + uint pmc_scratch113; + uint pmc_scratch114; + uint pmc_scratch115; + uint pmc_scratch116; + uint pmc_scratch117; + uint pmc_scratch118; + uint pmc_scratch119; +}; + +#define CPU_PWRED 1 +#define CPU_CLMP 1 + +#define PARTID_CP 0xFFFFFFF8 +#define START_CP (1 << 8) + +#define CPUPWRREQ_OE (1 << 16) +#define CPUPWRREQ_POL (1 << 15) + +#define CRAILID (0) +#define CE0ID (14) +#define C0NCID (15) +#define CRAIL (1 << CRAILID) +#define CE0 (1 << CE0ID) +#define C0NC (1 << C0NCID) + +#define PMC_XOFS_SHIFT 1 +#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) + +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 2 +#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) +#define MULT_1 0 +#define MULT_2 1 +#define MULT_4 2 +#define MULT_8 3 + +#define AMAP_WRITE_SHIFT 20 +#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) + +/* SEC_DISABLE_0, 0x04 */ +#define SEC_DISABLE_WRITE0_ON (1 << 4) +#define SEC_DISABLE_READ0_ON (1 << 5) +#define SEC_DISABLE_WRITE1_ON (1 << 6) +#define SEC_DISABLE_READ1_ON (1 << 7) +#define SEC_DISABLE_WRITE2_ON (1 << 8) +#define SEC_DISABLE_READ2_ON (1 << 9) +#define SEC_DISABLE_WRITE3_ON (1 << 10) +#define SEC_DISABLE_READ3_ON (1 << 11) +#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) + +/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ +#define PWRGATE_TOGGLE_PARTID_CRAIL 0 +#define PWRGATE_TOGGLE_PARTID_TD 1 +#define PWRGATE_TOGGLE_PARTID_VE 2 +#define PWRGATE_TOGGLE_PARTID_VDE 4 +#define PWRGATE_TOGGLE_PARTID_L2C 5 +#define PWRGATE_TOGGLE_PARTID_MPE 6 +#define PWRGATE_TOGGLE_PARTID_HEG 7 +#define PWRGATE_TOGGLE_PARTID_CE1 9 +#define PWRGATE_TOGGLE_PARTID_CE2 10 +#define PWRGATE_TOGGLE_PARTID_CE3 11 +#define PWRGATE_TOGGLE_PARTID_CELP 12 +#define PWRGATE_TOGGLE_PARTID_CE0 14 +#define PWRGATE_TOGGLE_PARTID_C0NC 15 +#define PWRGATE_TOGGLE_PARTID_C1NC 16 +#define PWRGATE_TOGGLE_PARTID_DIS 18 +#define PWRGATE_TOGGLE_PARTID_DISB 19 +#define PWRGATE_TOGGLE_PARTID_XUSBA 20 +#define PWRGATE_TOGGLE_PARTID_XUSBB 21 +#define PWRGATE_TOGGLE_PARTID_XUSBC 22 +#define PWRGATE_TOGGLE_START (1 << 8) + +/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ +#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) +#define PWRGATE_STATUS_TD_ENABLE (1 << 1) +#define PWRGATE_STATUS_VE_ENABLE (1 << 2) +#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) +#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) +#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) +#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) +#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) +#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) +#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) +#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) +#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) +#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) +#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) +#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) +#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) +#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) +#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) +#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) + +#endif /* _TEGRA114_PMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h index c6e2381..1766f18 100644 --- a/arch/arm/include/asm/arch-tegra114/pmu.h +++ b/arch/arm/include/asm/arch-tegra114/pmu.h @@ -1,23 +1,13 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_PMU_H_ #define _TEGRA114_PMU_H_ -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); +#include <asm/arch-tegra/tegra1x4_pmu.h> #endif /* _TEGRA114_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h index ebb16fe..9f789b5 100644 --- a/arch/arm/include/asm/arch-tegra114/spl.h +++ b/arch/arm/include/asm/arch-tegra114/spl.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h index c05e2c3..4f21c81 100644 --- a/arch/arm/include/asm/arch-tegra114/sysctr.h +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -1,35 +1,13 @@ /* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_SYSCTR_H_ #define _TEGRA114_SYSCTR_H_ -struct sysctr_ctlr { - u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ - u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ - u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ - u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ - u32 reserved1[4]; /* 0x10 - 0x1C */ - u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ - u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ - u32 reserved2[1002]; /* 0x28 - 0xFCC */ - u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ -}; - -#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ -#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ +#include <asm/arch-tegra/tegra1x4_sysctr.h> #endif /* _TEGRA114_SYSCTR_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index 5d426b5..89f57f3 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -1,17 +1,8 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_H_ diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h index d46048c..1c7d857 100644 --- a/arch/arm/include/asm/arch-tegra114/usb.h +++ b/arch/arm/include/asm/arch-tegra114/usb.h @@ -1,156 +1,13 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation - * See file CREDITS for list of people who contributed to this - * project. + * (C) Copyright 2013 + * NVIDIA Corporation <www.nvidia.com> * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _TEGRA114_USB_H_ #define _TEGRA114_USB_H_ -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[2]; - - /* 0x130 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x140 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint reserved5_1; - - /* 0x150 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; - uint icusb_ctrl; - - /* 0x160 */ - uint ulpi_viewport; - uint reserved7[3]; - - /* 0x170 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x190 */ - uint reserved9[8]; - - /* 0x1b0 */ - uint reserved10; - uint hostpc1_devlc; - uint reserved10_1[2]; - - /* 0x1c0 */ - uint reserved10_2[4]; - - /* 0x1d0 */ - uint reserved10_3[4]; - - /* 0x1e0 */ - uint reserved10_4[4]; - - /* 0x1f0 */ - uint reserved10_5; - uint otgsc; - uint usb_mode; - uint reserved10_6; - - /* 0x200 */ - uint endpt_nak; - uint endpt_nak_enable; - uint endpt_setup_stat; - uint reserved11_1[0x7D]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - -/* USB2D_HOSTPC1_DEVLC_0 */ -#define PTS_SHIFT 29 -#define PTS_MASK (0x7U << PTS_SHIFT) +#include <asm/arch-tegra/tegra1x4_usb.h> -#define STS (1 << 28) -#endif /* _TEGRA114_USB_H_ */ +#endif /* _TEGRA114_USB_H_ */ -- 1.8.1.5

2 1