October 2013 - U-Boot

[U-Boot] [PATCH V2]Powerpc/P1022DS: Enable the DIU for P1022DS board.
by Jason Jin 08 Oct '13

08 Oct '13

The DIU of P1022DS was disabled by commit: dfe64e2c89731a3f9950d7acd8681b68df2bae03 to verify the u-boot MTD subsystem. The local bus and DIU is multiplex on P1022, but the DIU will not be enabled if there is no video-mode environment. The NAND still can be used with DIU enabled in the configuration file with the video-mode environment disabled. Signed-off-by: Jason Jin <Jason.Jin(a)freescale.com> --- V2: Remove the ATI enablement when not enable the DIU. include/configs/P1022DS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index edece1f..9da9cdf 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -413,6 +413,7 @@ #define CONFIG_SYS_HUSH_PARSER /* Video */ +#define CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) -- 1.8.0

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[U-Boot] : SPI patches
by Jagan Teki 08 Oct '13

08 Oct '13

Hi Rajeswari, Below is a list of pending patches on my queue: http://patchwork.ozlabs.org/patch/247461/ http://patchwork.ozlabs.org/patch/247457/ http://patchwork.ozlabs.org/patch/247452/ http://patchwork.ozlabs.org/patch/247451/ http://patchwork.ozlabs.org/patch/247450/ Request you to fix my comments and re-base the same on to u-boot-spi.git repo with master-probe branch. Please test this new branch with your changes and let me know for any issues/concerns. -- Thanks, Jagan. -------- Jagannadha Sutradharudu Teki, E: jagannadh.teki(a)gmail.com, P: +91-9676773388 Engineer - System Software Hacker U-boot - SPI Custodian and Zynq APSOC Ln: http://www.linkedin.com/in/jaganteki

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[U-Boot] [PATCH] arm/km: fix i2c mux define for km_kirkwood_128m16 target
by Holger Brunck 08 Oct '13

08 Oct '13

Due to the i2c mux rework in u-boot we now have only to specify the busnumber and not the whole mux configuration. Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> --- include/configs/km_kirkwood.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 3806762..2bd89b1 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -43,7 +43,7 @@ #define CONFIG_SYS_KWD_CONFIG \ $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg #define CONFIG_KM_DISABLE_PCIE -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ /* KM_NUSA */ #elif defined(CONFIG_KM_NUSA) -- 1.8.0.1

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[U-Boot] [PATCH] Tegra114: Dalmore: Add voltage reg/PMIC init for various periphs
by Tom Warren 08 Oct '13

08 Oct '13

These powerrails are currently needed for kernel boot. This will be move to a pmic-specific driver (or even better moved to the kernel) at a later date. Signed-off-by: Tom Warren <twarren(a)nvidia.com> Change-Id: Id1654e6338b11cb22715fa3caba644cfe6e2410b --- arch/arm/include/asm/arch-tegra/board.h | 3 + board/nvidia/common/board.c | 4 + board/nvidia/dalmore/dalmore.c | 154 +++++++++++++++++++++++++++----- include/configs/dalmore.h | 3 + 4 files changed, 140 insertions(+), 24 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 0e69864..b148b25 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -29,4 +29,7 @@ void pin_mux_spi(void); /* overrideable SPI pinmux setup */ void pin_mux_nand(void); /* overrideable NAND pinmux setup */ void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */ +/* Enable needed power rails */ +void board_vreg_init(void); + #endif diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 126e56e..c479958 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -151,6 +151,10 @@ int board_init(void) # endif /* CONFIG_TEGRA_PMU */ #endif /* CONFIG_SYS_I2C_TEGRA */ +#ifdef CONFIG_TEGRA114 + /* Enable needed power rails. TBD: Move to kernel or driver init. */ + board_vreg_init(); +#endif #ifdef CONFIG_USB_EHCI_TEGRA pin_mux_usb(); board_usb_init(gd->fdt_blob); diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 2c23a29..27f9ab2 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -15,8 +15,10 @@ */ #include <common.h> -#include <asm/arch/pinmux.h> +#include <asm-generic/gpio.h> +#include <asm/arch/gpio.h> #include <asm/arch/gp_padctrl.h> +#include <asm/arch/pinmux.h> #include "pinmux-config-dalmore.h" #include <i2c.h> @@ -42,6 +44,20 @@ void pinmux_init(void) padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl)); } +/* Writes val to reg @ chip address pmu */ +void i2c_write_pmic(uchar pmu, uchar reg, uchar val) +{ + uchar data_buffer[1]; + int ret; + + data_buffer[0] = val; + + ret = i2c_write(pmu, reg, 1, data_buffer, 1); + if (ret) + printf("%s: PMU i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); +} + #if defined(CONFIG_TEGRA_MMC) /* * Do I2C/PMU writes to bring up SD card bus power @@ -49,39 +65,129 @@ void pinmux_init(void) */ void board_sdmmc_voltage_init(void) { - uchar reg, data_buffer[1]; - int ret; - - ret = i2c_set_bus_num(0);/* PMU is on bus 0 */ + int ret = i2c_set_bus_num(0); /* PMU is on bus 0 */ if (ret) printf("%s: i2c_set_bus_num returned %d\n", __func__, ret); /* TPS65913: LDO9_VOLTAGE = 3.3V */ - data_buffer[0] = 0x31; - reg = 0x61; - - ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); - if (ret) - printf("%s: PMU i2c_write %02X<-%02X returned %d\n", - __func__, reg, data_buffer[0], ret); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x61, 0x31); /* TPS65913: LDO9_CTRL = Active */ - data_buffer[0] = 0x01; - reg = 0x60; - - ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); - if (ret) - printf("%s: PMU i2c_write %02X<-%02X returned %d\n", - __func__, reg, data_buffer[0], ret); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x60, 0x01); /* TPS65090: FET6_CTRL = enable output auto discharge, enable FET6 */ - data_buffer[0] = 0x03; - reg = 0x14; + i2c_write_pmic(PMU_I2C_ADDRESS, 0x14, 0x03); +} - ret = i2c_write(BAT_I2C_ADDRESS, reg, 1, data_buffer, 1); +void board_vreg_init(void) +{ + int ret = i2c_set_bus_num(0); /* PMU is on bus 0 */ if (ret) - printf("%s: BAT i2c_write %02X<-%02X returned %d\n", - __func__, reg, data_buffer[0], ret); + printf("%s: i2c_set_bus_num returned %d\n", __func__, ret); + + /* + * Enable USB voltage: AVDD_USB_HDMI for AVDD_USB_AP + * and AVDD_HDMI_AP + * LDOUSB_VOLTAGE = 3.3v + * LDOUSB_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x65, 0x31); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x64, 0x01); + + /* + * Enable HVDD_USB3 voltage: HVDD_USB3_AP + * LDOLN_VOLTAGE = 3.3v + * LDOLN_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x63, 0x31); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x62, 0x01); + + /* + * Enable additional VDD_1V1_CORE + * + * SMPS7_CTRL: enable active: auto + * + * VDD_CORE is provided by SMPS4_SW, 5 and 7 where + * 4 and 5 are enabled after power on. + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x30, 0x05); + + /* + * Set and enable AVDD_2V8_CAM1 + * LDO1_VOLTAGE = 2.8v + * LDO1_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x51, 0x27); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x50, 0x01); + + /* + * Set and enable AVDD_2V8_CAM2 + * LDO2_VOLTAGE = 2.8v + * LDO2_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x53, 0x27); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x52, 0x01); + + /* + * Set and enable AVDD_1V2 for VDDIO_HSIC_AP and AVDD_DSI_CSI_AP + * LDO3_VOLTAGE = 1.2v + * LDO3_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x55, 0x07); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x54, 0x01); + + /* + * Set and enable VPP_FUSE_APP + * LDO4_VOLTAGE = 1.8v + * LDO4_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x57, 0x13); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x56, 0x01); + + /* + * Set and enable VDD_1V2_LCD + * LDO5_VOLTAGE = 1.2v (TPS65913) + * LDO5_CTRL = Active + * + * Enable VDD_LCD_BL + * VOUT1 (FET1) (TPS65090): auto discharge and enable + * + * Enable AVDD_LCD + * VOUT4 (FET4) (TPS65090): auto discharge and enable + * + * Enable VDD_LVDS + * VOUT5 (FET5) (TPS65090): auto discharge and enable + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x59, 0x07); /* LDO5_VOLTAGE */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x58, 0x01); /* LD05_CTRL */ + i2c_write_pmic(BAT_I2C_ADDRESS, 0x0F, 0x03); /* VOUT1 (FET1) */ + i2c_write_pmic(BAT_I2C_ADDRESS, 0x12, 0x03); /* VOUT4 (FET4) */ + i2c_write_pmic(BAT_I2C_ADDRESS, 0x13, 0x03); /* VOUT5 (FET5) */ + + /* + * Set and enable VDD_SENSOR + * LDO6_VOLTAGE = 2.85v + * LDO6_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x5B, 0x28); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x5A, 0x01); + + /* + * Set and enable AVDD_2V8_CAM_AF1 + * LDO7_VOLTAGE = 2.8v + * LDO7_CTRL = Active + */ + i2c_write_pmic(PMU_I2C_ADDRESS, 0x5D, 0x27); + i2c_write_pmic(PMU_I2C_ADDRESS, 0x5C, 0x01); + + /* + * Enable VDD_3V3_COM + * VOUT7 (FET7) (TPS65090): auto discharge and enable + */ + i2c_write_pmic(BAT_I2C_ADDRESS, 0x15, 0x03); + + /* Enable LCD backlight */ + gpio_direction_output(DSI_PANEL_BL_EN_GPIO, 1); } /* diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index bdf012b..ec285b0 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -87,6 +87,9 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP +/* Backlight enable GPIO. TBD - move to DT when LCD driver added */ +#define DSI_PANEL_BL_EN_GPIO GPIO_PH2 + #include "tegra-common-post.h" #endif /* __CONFIG_H */ -- 1.8.1.5

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[U-Boot] [PATCH v3 0/3] Trivial patches ready for merging
by Otavio Salvador 07 Oct '13

07 Oct '13

Hello, I am resending the patches I think are ready to be applied and are trivial. Please also add: http://patchwork.ozlabs.org/patch/279105/ as it fixes a watchdog to work. Changes in v3: - Fix code comment (dropped 'either') Changes in v2: - rework commit log (Eric Benard) - rework commitlog (Fabio) Otavio Salvador (3): mtd: Fix function description in part_validate comment include/linux/fb.h: Add a missing include for 'list.h' doc: Fix a typo in the description in doc/README.JFFS2_NAND common/cmd_mtdparts.c | 7 +++---- doc/README.JFFS2_NAND | 2 +- include/linux/fb.h | 1 + 3 files changed, 5 insertions(+), 5 deletions(-) -- 1.8.4.rc3

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[U-Boot] [PATCH] power:pmic: prevent data abort for pmic bat command
by Piotr Wilczek 07 Oct '13

07 Oct '13

This patch prevents data abort when pmic bat command is called on non-batery pmic device. Signed-off-by: Piotr Wilczek <p.wilczek(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> CC: Lukasz Majewski <l.majewski(a)samsung.com> CC: Minkyu Kang <mk7.kang(a)samsung.com> --- drivers/power/power_core.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index 583e56b..d9bc05f 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -188,18 +188,21 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 4) return CMD_RET_USAGE; + if (!p->pbat) { + printf("%s is not a battery\n", p->name); + return CMD_RET_FAILURE; + } + if (strcmp(argv[3], "state") == 0) p->fg->fg_battery_check(p->pbat->fg, p); if (strcmp(argv[3], "charge") == 0) { - if (p->pbat) { - printf("BAT: %s charging (ctrl+c to break)\n", - p->name); - if (p->low_power_mode) - p->low_power_mode(); - if (p->pbat->battery_charge) - p->pbat->battery_charge(p); - } + printf("BAT: %s charging (ctrl+c to break)\n", + p->name); + if (p->low_power_mode) + p->low_power_mode(); + if (p->pbat->battery_charge) + p->pbat->battery_charge(p); } return CMD_RET_SUCCESS; -- 1.7.9.5

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[U-Boot] [PATCH] pci: Properly configure prefetchable memory region
by Thierry Reding 07 Oct '13

07 Oct '13

Forcibly set hose->pci_prefetch to NULL to make sure it will be setup. This will help if for any reason callers didn't make sure themselves to NULL the field. Signed-off-by: Thierry Reding <treding(a)nvidia.com> --- drivers/pci/pci_auto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index c4ed8ba..86ba6b5 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -297,7 +297,7 @@ void pciauto_config_init(struct pci_controller *hose) { int i; - hose->pci_io = hose->pci_mem = NULL; + hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL; for (i = 0; i < hose->region_count; i++) { switch(hose->regions[i].flags) { -- 1.8.4

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[U-Boot] [PATCH] cmd_nvedit.c: setenv_hex must prefix hex with '0x'
by Tom Rini 07 Oct '13

07 Oct '13

setenv_hex is only called with hex values, but does not prefix the strings with '0x', as in general U-Boot assumes hex values not decimal values, and this saves space in the environment. However, some functions such as 'load' take some values that are most easily described in hex (load address) and decimal (size, offset within a file). This can lead to the situation where, for example, spl export is run, which leads to a call of setenv_hex of the fdtaddr, which will be re-set in the environment. Then 'saveenv' may be run (after updating other parts of the environment for falcon mode), causing an invalid for 'load' fdtaddr to be saved to the environment and leading to future boots to fail if using 'load' to read the fdt file. Cc: Wolfgang Denk <wd(a)denx.de> Signed-off-by: Tom Rini <trini(a)ti.com> --- common/cmd_nvedit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 778dca5..4cac794 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -321,7 +321,7 @@ int setenv_hex(const char *varname, ulong value) { char str[17]; - sprintf(str, "%lx", value); + sprintf(str, "0x%lx", value); return setenv(varname, str); } -- 1.7.9.5

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[U-Boot] [PATCH] ARM: virtualization: replace verbose license with SPDX identifier
by Andre Przywara 07 Oct '13

07 Oct '13

The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S} predates the SPDX conversion, so the original elaborate license statements sneaked in. Fix this by replacing them with the proper abbreviation. Signed-off-by: Andre Przywara <andre.przywara(a)linaro.org> --- arch/arm/cpu/armv7/nonsec_virt.S | 18 +----------------- arch/arm/cpu/armv7/virt-v7.c | 20 ++------------------ 2 files changed, 3 insertions(+), 35 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 358348f..24b4c18 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -3,23 +3,7 @@ * * Copyright (c) 2013 Andre Przywara <andre.przywara(a)linaro.org> * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include <config.h> diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 6de7fe7..2cd604f 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -1,28 +1,12 @@ /* * (C) Copyright 2013 - * Andre Przywara, Linaro + * Andre Przywara, Linaro <andre.przywara(a)linaro.org> * * Routines to transition ARMv7 processors from secure into non-secure state * and from non-secure SVC into HYP mode * needed to enable ARMv7 virtualization for current hypervisors * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -- 1.7.12.1

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[U-Boot] [RESEND PATCH v6 2/2] socfpga: Adding pin mux handoff files
by Chin Liang See 07 Oct '13

07 Oct '13

Adding the generated pin mux configuration by Preloader Generator tool Signed-off-by: Chin Liang See <clsee(a)altera.com> Reviewed-by: Pavel Machek <pavel(a)denx.de> Acked-by: Dinh Nguyen <dinguyen(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- Changes for v6: - Re-shuffle the change list Changes for v5: - Updated the subject Changes for v4: - Added change log for each revision change Changes for v3: - Fixed the long subject of the patch Changes for v2: - Fixed the word wrap issue within patch --- board/altera/socfpga/pinmux_config.c | 214 ++++++++++++++++++++++++++++++++++ board/altera/socfpga/pinmux_config.h | 54 +++++++++ 2 files changed, 268 insertions(+) create mode 100644 board/altera/socfpga/pinmux_config.c create mode 100644 board/altera/socfpga/pinmux_config.h diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c new file mode 100644 index 0000000..8b09005 --- /dev/null +++ b/board/altera/socfpga/pinmux_config.c @@ -0,0 +1,214 @@ +/* This file is generated by Preloader Generator */ + +#include "pinmux_config.h" + +/* pin mux configuration data */ +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { + 0, /* EMACIO0 - Unused */ + 2, /* EMACIO1 - USB */ + 2, /* EMACIO2 - USB */ + 2, /* EMACIO3 - USB */ + 2, /* EMACIO4 - USB */ + 2, /* EMACIO5 - USB */ + 2, /* EMACIO6 - USB */ + 2, /* EMACIO7 - USB */ + 2, /* EMACIO8 - USB */ + 0, /* EMACIO9 - Unused */ + 2, /* EMACIO10 - USB */ + 2, /* EMACIO11 - USB */ + 2, /* EMACIO12 - USB */ + 2, /* EMACIO13 - USB */ + 0, /* EMACIO14 - N/A */ + 0, /* EMACIO15 - N/A */ + 0, /* EMACIO16 - N/A */ + 0, /* EMACIO17 - N/A */ + 0, /* EMACIO18 - N/A */ + 0, /* EMACIO19 - N/A */ + 3, /* FLASHIO0 - SDMMC */ + 3, /* FLASHIO1 - SDMMC */ + 3, /* FLASHIO2 - SDMMC */ + 3, /* FLASHIO3 - SDMMC */ + 0, /* FLASHIO4 - SDMMC */ + 0, /* FLASHIO5 - SDMMC */ + 0, /* FLASHIO6 - SDMMC */ + 0, /* FLASHIO7 - SDMMC */ + 0, /* FLASHIO8 - SDMMC */ + 3, /* FLASHIO9 - SDMMC */ + 3, /* FLASHIO10 - SDMMC */ + 3, /* FLASHIO11 - SDMMC */ + 3, /* GENERALIO0 - TRACE */ + 3, /* GENERALIO1 - TRACE */ + 3, /* GENERALIO2 - TRACE */ + 3, /* GENERALIO3 - TRACE */ + 3, /* GENERALIO4 - TRACE */ + 3, /* GENERALIO5 - TRACE */ + 3, /* GENERALIO6 - TRACE */ + 3, /* GENERALIO7 - TRACE */ + 3, /* GENERALIO8 - TRACE */ + 3, /* GENERALIO9 - SPIM0 */ + 3, /* GENERALIO10 - SPIM0 */ + 3, /* GENERALIO11 - SPIM0 */ + 3, /* GENERALIO12 - SPIM0 */ + 2, /* GENERALIO13 - CAN0 */ + 2, /* GENERALIO14 - CAN0 */ + 3, /* GENERALIO15 - I2C0 */ + 3, /* GENERALIO16 - I2C0 */ + 2, /* GENERALIO17 - UART0 */ + 2, /* GENERALIO18 - UART0 */ + 0, /* GENERALIO19 - N/A */ + 0, /* GENERALIO20 - N/A */ + 0, /* GENERALIO21 - N/A */ + 0, /* GENERALIO22 - N/A */ + 0, /* GENERALIO23 - N/A */ + 0, /* GENERALIO24 - N/A */ + 0, /* GENERALIO25 - N/A */ + 0, /* GENERALIO26 - N/A */ + 0, /* GENERALIO27 - N/A */ + 0, /* GENERALIO28 - N/A */ + 0, /* GENERALIO29 - N/A */ + 0, /* GENERALIO30 - N/A */ + 0, /* GENERALIO31 - N/A */ + 2, /* MIXED1IO0 - EMAC */ + 2, /* MIXED1IO1 - EMAC */ + 2, /* MIXED1IO2 - EMAC */ + 2, /* MIXED1IO3 - EMAC */ + 2, /* MIXED1IO4 - EMAC */ + 2, /* MIXED1IO5 - EMAC */ + 2, /* MIXED1IO6 - EMAC */ + 2, /* MIXED1IO7 - EMAC */ + 2, /* MIXED1IO8 - EMAC */ + 2, /* MIXED1IO9 - EMAC */ + 2, /* MIXED1IO10 - EMAC */ + 2, /* MIXED1IO11 - EMAC */ + 2, /* MIXED1IO12 - EMAC */ + 2, /* MIXED1IO13 - EMAC */ + 0, /* MIXED1IO14 - Unused */ + 3, /* MIXED1IO15 - QSPI */ + 3, /* MIXED1IO16 - QSPI */ + 3, /* MIXED1IO17 - QSPI */ + 3, /* MIXED1IO18 - QSPI */ + 3, /* MIXED1IO19 - QSPI */ + 3, /* MIXED1IO20 - QSPI */ + 0, /* MIXED1IO21 - GPIO */ + 0, /* MIXED2IO0 - N/A */ + 0, /* MIXED2IO1 - N/A */ + 0, /* MIXED2IO2 - N/A */ + 0, /* MIXED2IO3 - N/A */ + 0, /* MIXED2IO4 - N/A */ + 0, /* MIXED2IO5 - N/A */ + 0, /* MIXED2IO6 - N/A */ + 0, /* MIXED2IO7 - N/A */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h new file mode 100644 index 0000000..f278f2b --- /dev/null +++ b/board/altera/socfpga/pinmux_config.h @@ -0,0 +1,54 @@ +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PINMUX_CONFIG_H_ +#define _PRELOADER_PINMUX_CONFIG_H_ + +/* + * State of enabling for which IP connected out through the muxing. + * Value 1 mean the IP connection is muxed out + */ +#define CONFIG_HPS_EMAC0 (0) +#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_USB0 (0) +#define CONFIG_HPS_USB1 (1) +#define CONFIG_HPS_NAND (0) +#define CONFIG_HPS_SDMMC (1) +#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_UART0 (1) +#define CONFIG_HPS_UART1 (0) +#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_I2C0 (1) +#define CONFIG_HPS_I2C1 (0) +#define CONFIG_HPS_I2C2 (0) +#define CONFIG_HPS_I2C3 (0) +#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM1 (0) +#define CONFIG_HPS_SPIS0 (0) +#define CONFIG_HPS_SPIS1 (0) +#define CONFIG_HPS_CAN0 (1) +#define CONFIG_HPS_CAN1 (0) + +/* IP attribute value (which affected by pin muxing configuration) */ +#define CONFIG_HPS_SDMMC_BUSWIDTH (4) + +/* 1 if the pins are connected out */ +#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS1 (0) +#define CONFIG_HPS_QSPI_CS2 (0) +#define CONFIG_HPS_QSPI_CS3 (0) + +/* UART */ +/* 1 means the pin is mux out or available */ +#define CONFIG_HPS_UART0_TX (1) +#define CONFIG_HPS_UART0_RX (1) +#define CONFIG_HPS_UART0_CTS (0) +#define CONFIG_HPS_UART0_RTS (0) +#define CONFIG_HPS_UART1_TX (0) +#define CONFIG_HPS_UART1_RX (0) +#define CONFIG_HPS_UART1_CTS (0) +#define CONFIG_HPS_UART1_RTS (0) + +/* Pin mux data */ +#define CONFIG_HPS_PINMUX_NUM (207) + +#endif /* _PRELOADER_PINMUX_CONFIG_H_ */ -- 1.7.9.5

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