October 2013 - U-Boot

[U-Boot] [PATCH 4/6] Makefile:Add u-boot-with-spl-pbl.bin target for SPL
by Prabhakar Kushwaha 01 Oct '13

01 Oct '13

This image combines the pbl format of SPL with and U-Boot. This is a convenient way of having a single image to program on indirect boot source. Corenet platforms like T4240, P4080 etc have PBL hardware which read data in PBL format and copy to internal SRAM for further execution. This image configures DDR, copy u-boot to DDR and transfer the control. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next Makefile | 7 +++++++ spl/Makefile | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/Makefile b/Makefile index 6f8f2f1..260bb65 100644 --- a/Makefile +++ b/Makefile @@ -496,6 +496,9 @@ endif $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD) $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) +$(obj)u-boot-with-spl-pbl.bin: $(obj)spl/u-boot-spl.pbl $(SPL_PAYLOAD) + $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) + $(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin $(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO)) @@ -623,6 +626,9 @@ $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all +$(obj)spl/u-boot-spl.pbl: $(SUBDIR_TOOLS) depend + $(MAKE) -C spl all + $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all CONFIG_TPL_BUILD=y @@ -917,6 +923,7 @@ clobber: tidy @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map} @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} + @rm -f $(obj)spl/u-boot-spl.pbl @rm -f $(obj)spl/u-boot-spl.lds @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map} @rm -f $(obj)tpl/u-boot-spl.lds diff --git a/spl/Makefile b/spl/Makefile index 174d0a7..919f97e 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -180,6 +180,10 @@ ifdef CONFIG_SAMSUNG ALL-y += $(obj)$(BOARD)-spl.bin endif +ifdef CONFIG_PBLPBI_CONFIG +ALL-y += $(obj)$(SPL_BIN).pbl +endif + all: $(ALL-y) ifdef CONFIG_SAMSUNG @@ -191,6 +195,11 @@ endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ +$(obj)$(SPL_BIN).pbl: $(obj)$(SPL_BIN).bin + $(obj)../tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ + -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ + -d $< $@ + GEN_UBOOT = \ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -- 1.7.9.5

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[U-Boot] [PATCH 2/6] powerpc/SPL:Allow Parsing of LAW table in both SPL & non SPL
by Prabhakar Kushwaha 01 Oct '13

01 Oct '13

SPL does not relocates the CCSRBAR hence it is using CCSRBAR at 0xfe00_0000. U-boot relocates CCSRBAR to 0xf_fe00_0000. So law talbe needs to be updated again. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next arch/powerpc/cpu/mpc8xxx/law.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index a401083..d76ba22 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -244,15 +244,6 @@ void init_laws(void) gd->arch.used_laws |= (1 << i); } -#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - /* - * in SPL boot we've already parsed the law_table and setup those LAWs - * so don't do it again. - */ - return; -#endif - for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, -- 1.7.9.5

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[U-Boot] [PATCH 1/6] powerpc:Add support of SPL non-relocation
by Prabhakar Kushwaha 01 Oct '13

01 Oct '13

Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation, move bss_section within SPL range. Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot-mpc85xx.git branch next arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index bc13267..ffc6ad3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,13 +57,34 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; +#ifdef CONFIG_SKIP_RELOCATE_SPL + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif /* FIXME for non-NAND SPL */ #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else @@ -80,6 +101,7 @@ SECTIONS } = 0xffff #endif +#ifndef CONFIG_SKIP_RELOCATE_SPL /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -94,4 +116,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif } -- 1.7.9.5

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[U-Boot] [PATCH 0/6] powerpc: Add support 2 stage boot loader for corenet platform
by Prabhakar Kushwaha 01 Oct '13

01 Oct '13

Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Add support of 2 stage NAND boot loader in cornet platforms using SPL framework. This will be helpful for those SoC which has less internal SRAM(256K) like T1040. here, PBL initialise the internal SRAM and copy SPL(192K) in SRAM. SPL further initialise DDR using SPD and environment variables and copy u-boot(512 KB) from NAND flash to DDR. Finally SPL transer control to u-boot for futher booting. SPL has following features: - Executes within 256K - SPL size 192K - No relocation required Run time view of SPL framework ============================== ----------------------------------------------- Area | Address | ----------------------------------------------- GD, BD | 0x0xFFFC0000 (4K) | ----------------------------------------------- HEAP | 0xFFFC1000 (40K) grow downwards | ----------------------------------------------- STACK | 0xFFFD0000 (20K) grow upwards | ----------------------------------------------- U-boot SPL | 0xfffD0000 - 0xfffffffc (192K) | ----------------------------------------------- --- This patch set contains:- [PATCH 1/6] powerpc:Add support of SPL non-relocation [PATCH 2/6] powerpc/SPL:Allow Parsing of LAW table in both SPL & non SPL [PATCH 3/6] common/env: Point default envirenoment for GD [PATCH 4/6] Makefile:Add u-boot-with-spl-pbl.bin target for SPL [PATCH 5/6] SPL:Defines function required to env read for IFC & env_nand [PATCH 6/6] T1040QDS: Add support of 2 stage NAND boot loader -- 1.7.9.5

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