October 2013 - U-Boot

[U-Boot] omap3 usb boot
by Michael Trimarchi 11 Oct '13

11 Oct '13

Hi Tom I have managed to boot dm3730 on usb (first stage), but looking at the code I have some comment in arch/arm/cpu/armv7/omap3/clock.c #ifdef CONFIG_SYS_NS16550 /* Enable UART1 clocks */ sr32(&prcm_base->fclken1_core, 13, 1, 0x1); sr32(&prcm_base->iclken1_core, 13, 1, 0x1); /* UART 3 Clocks */ sr32(&prcm_base->fclken_per, 11, 1, 0x1); sr32(&prcm_base->iclken_per, 11, 1, 0x1); You enable clock for two uarts without take in account the real console uart of the device. Then some lines after sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); That just reset all the clock using the PER_ON mask so what is done before doesn't make sense anymore. Michael

2 1

[U-Boot] [RFC] [PATCH] [NEXT] arm: keep all sections in ELF file
by Albert ARIBAUD 11 Oct '13

11 Oct '13

(foreword: this is an RFC, and in any case, not intended for the upcoming 2013.10 release :) therefore I put notes here in the commit message whereas the first actual patch will have notes below the comment ('---') line of course.) Current LDS files /DISCARD/ a lot of sections when linking ELF files, causing diagnostic tools such as readelf or objdump to produce partial output. Keep all section at link stage, filter only at objcopy time so that .bin remains minimal. NOTES: *Please test*! :) While the build reports show slightly text/data/bss/size increases, .bin sizes are actually slightly reduced. Go figure. I have not modified the x86 and MIPS lds files, which still /DISCARD/ unwanted sections. If the maintainers (Cc:ed) wish that I include their lds files in the patch, just let me know (and please test, too). The added line in Makefile is there only to help testing: it generates an ELF version of u-boot.bin called u-boot.bin.elf in which you can see which sections were kept and where they are supposed to map. This will not be present in the actual patch. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Simon Glass <sjg(a)chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)googlemail.com> --- Makefile | 1 + arch/arm/config.mk | 3 +++ arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 16 +++++++++------- arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 16 +++++++++------- arch/arm/cpu/ixp/u-boot.lds | 15 +++++++++------ arch/arm/cpu/u-boot-spl.lds | 15 +++++++++------ arch/arm/cpu/u-boot.lds | 19 +++++++++++-------- board/actux1/u-boot.lds | 15 +++++++++------ board/actux2/u-boot.lds | 15 +++++++++------ board/actux3/u-boot.lds | 15 +++++++++------ board/dvlhost/u-boot.lds | 15 +++++++++------ board/freescale/mx31ads/u-boot.lds | 18 +++++++++--------- board/ti/am335x/u-boot.lds | 15 +++++++++------ board/vpac270/u-boot-spl.lds | 18 +++++++++--------- 14 files changed, 114 insertions(+), 82 deletions(-) diff --git a/Makefile b/Makefile index 7d62f38..aa60f1a 100644 --- a/Makefile +++ b/Makefile @@ -432,6 +432,7 @@ $(obj)u-boot.srec: $(obj)u-boot $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + $(OBJCOPY) ${OBJCFLAGS} $< $@.elf $(BOARD_SIZE_CHECK) $(obj)u-boot.ldr: $(obj)u-boot diff --git a/arch/arm/config.mk b/arch/arm/config.mk index d0cf43f..7d1b049 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -103,3 +103,6 @@ ALL-y += checkarmreloc # such usage by requiring word relocations. PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif + +# limit ourselves to the sections we want in the .bin. +OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 40bcc31..80fb9bd 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -51,11 +51,13 @@ SECTIONS _end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index 4927736..76b499d 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -51,11 +51,13 @@ SECTIONS _end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index c8d2e12..676ae2c 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -79,10 +79,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 36cc54a..4880d0f 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -51,12 +51,15 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } #if defined(CONFIG_SPL_MAX_SIZE) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 23bf030..b696ad1 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -60,6 +60,9 @@ SECTIONS *(.__rel_dyn_end) } + .hash : { *(.hash) } + .got.plt : { *(.got.plt) } + _end = .; /* @@ -91,12 +94,12 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } - /DISCARD/ : { *(.ARM.exidx*) } - /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index a656fa9..12e018f 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 7a17176..300273b 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index aadfdd2..9c97c53 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 40c9c80..057d94b 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index a6ef66e..4f4821c 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -90,13 +90,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index a173f62..9f96a43 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -108,10 +108,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 7eac497..08c78b3 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -62,13 +62,13 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } -- 1.8.3.2

2 1

[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 11 Oct '13

11 Oct '13

Dear Albert, The following changes since commit 12eba1b49380988fd87cc0b3af44014cca8b71c4: README: update ARM register usage (2013-09-23 18:00:36 +0200) are available in the git repository at: git://git.denx.de/u-boot-samsung master for you to fetch changes up to 4d6c96711bd550ae292df566c2b36ff3e3dac24c: samsung: trats2: add support for new board Trats2 (2013-09-25 10:52:33 +0900) ---------------------------------------------------------------- Piotr Wilczek (4): drivers:power:max77693: add support for new multi function pmic max77693 power:battery: add battery support for Trats2 board samsung:common:i2c: add definions for third soft I2C adapter for Trats2 board samsung: trats2: add support for new board Trats2 Makefile | 1 + board/samsung/common/multi_i2c.c | 12 + board/samsung/trats2/Makefile | 34 +++ board/samsung/trats2/trats2.c | 513 ++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + drivers/power/battery/Makefile | 1 + drivers/power/battery/bat_trats2.c | 65 +++++ drivers/power/mfd/Makefile | 33 +++ drivers/power/mfd/fg_max77693.c | 139 ++++++++++ drivers/power/mfd/muic_max77693.c | 77 ++++++ drivers/power/mfd/pmic_max77693.c | 96 +++++++ include/configs/trats2.h | 311 ++++++++++++++++++++++ include/power/max77693_fg.h | 49 ++++ include/power/max77693_muic.h | 74 ++++++ include/power/max77693_pmic.h | 43 +++ 15 files changed, 1449 insertions(+) create mode 100644 board/samsung/trats2/Makefile create mode 100644 board/samsung/trats2/trats2.c create mode 100644 drivers/power/battery/bat_trats2.c create mode 100644 drivers/power/mfd/Makefile create mode 100644 drivers/power/mfd/fg_max77693.c create mode 100644 drivers/power/mfd/muic_max77693.c create mode 100644 drivers/power/mfd/pmic_max77693.c create mode 100644 include/configs/trats2.h create mode 100644 include/power/max77693_fg.h create mode 100644 include/power/max77693_muic.h create mode 100644 include/power/max77693_pmic.h -- Thanks, Minkyu Kang.

2 1

[U-Boot] sandbox is broken
by Masahiro Yamada 11 Oct '13

11 Oct '13

Hello Wolfgang, Simon I cannot build sandbox for the current u-boot/master. Could you check please? The error is like this: cmd_sandbox.c: In function 'do_sandbox_load': cmd_sandbox.c:13:2: error: too many arguments to function 'do_load' In file included from cmd_sandbox.c:8:0: /home/yamada/workspace/eclipse/u-boot/include/fs.h:61:5: note: declared here cmd_sandbox.c: In function 'do_sandbox_save': cmd_sandbox.c:25:2: error: too many arguments to function 'do_save' In file included from cmd_sandbox.c:8:0: /home/yamada/workspace/eclipse/u-boot/include/fs.h:65:5: note: declared here make[2]: *** [cmd_sandbox.o] Error 1 make[2]: Leaving directory `/home/yamada/workspace/eclipse/u-boot/common' make[1]: *** [common/libcommon.o] Error 2 make[1]: Leaving directory `/home/yamada/workspace/eclipse/u-boot' make: *** [sandbox] Error 2 It looks like this error was caused by the following commit. commit b770e88a6c2548727f0d57a3e9e8bb0830f977b5 Author: Wolfgang Denk <wd(a)denx.de> Date: Sat Oct 5 21:07:25 2013 +0200 Fix number base handling of "load" command Best Regards Masahiro Yamada

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[U-Boot] U-Boot Regression Testing
by Curt Brune 11 Oct '13

11 Oct '13

Hello, I have some questions about how U-Boot regression testing works. I am assuming some regression testing happens during the release period across some representative sample of boards and architectures. I know people check for compilation failures with MAKEALL, but I am wondering about runtime testing. I also understand that testing platform specific boot code is rather difficult (or easy depending on your perspective) - it boots or it does not boot. To be concrete -- how are core U-Boot commands and features tested? For example how do you test that FIT image support is not broken or that the 'env' command and all its options work properly? Googling did not turn up much on how this is done. On the social side -- is that something the community helps out with or something DENX does, or a mix? Are you using a test framework of some kind, either home grown or open source? These things tend to become home grown over time :) This kind of testing usually takes the form of 'chat' scripts communicating over serial consoles. Perhaps you are using expect, pexpect, python nose? We have a project, of which U-Boot is a part, that is starting to span multiple boards and architectures. We make a few modifications to U-Boot and I want to start automated regression testing as the number of boards increases. If an existing framework exists that folks are happy with I would love to hear about it. Equally, I am interested to hear about what did *not* work for people. Whatever method our project uses the scripts will be publicly available. Cheers, Curt

4 4

[U-Boot] [PATCH v4] PCIe:change the method to get the address of a requested capability in configuration space.
by Zhao Qiang 11 Oct '13

11 Oct '13

Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- Changes for v2: -Put an variable into "#ifdef" and "#endif" Changes for v3: -Modify the patch description Changes for v4: -rebase on u-boot master branch arch/powerpc/include/asm/fsl_pci.h | 18 ----------- drivers/pci/fsl_pci_init.c | 44 +++++++++++++++++++------- drivers/pci/pci.c | 65 ++++++++++++++++++++++++++++++++++++++ include/pci.h | 10 ++++++ 4 files changed, 107 insertions(+), 30 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 749411c..5be718b 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -18,24 +18,6 @@ /* Freescale-specific PCI config registers */ #define FSL_PCI_PBFR 0x44 -#ifdef CONFIG_SYS_FSL_PCI_VER_3_X -/* Currently only the PCIe capability is used, so hardcode the offset. - * if more capabilities need to be justified, the capability link method - * should be applied here - */ -#define FSL_PCIE_CAP_ID 0x70 -#define PCI_DCR 0x78 /* PCIe Device Control Register */ -#define PCI_DSR 0x7a /* PCIe Device Status Register */ -#define PCI_LSR 0x82 /* PCIe Link Status Register */ -#define PCI_LCR 0x80 /* PCIe Link Control Register */ -#else -#define FSL_PCIE_CAP_ID 0x4c -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#endif - #define FSL_PCIE_CFG_RDY 0x4b0 #define FSL_PROG_IF_AGENT 0x1 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index d55db1a..1c202ca 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -295,6 +295,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; + int pcie_cap_pos; + int pci_dcr; + int pci_dsr; + int pci_lsr; + +#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + int pci_lcr; +#endif + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; struct pci_region *reg = hose->regions + hose->region_count; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); @@ -367,7 +376,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) hose->region_count++; /* see if we are a PCIe or PCI controller */ - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_dcr = pcie_cap_pos + 0x08; + pci_dsr = pcie_cap_pos + 0x0a; + pci_lsr = pcie_cap_pos + 0x12; + + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ @@ -406,15 +420,16 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) * - Master PERR (pci) * - ICCA (PCIe) */ - pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ - pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + pci_lcr = pcie_cap_pos + 0x10; temp32 = 0; - pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); temp32 &= ~0x03; /* Disable ASPM */ - pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { @@ -494,7 +509,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_int_en, 0xffffffff); /* Print the negotiated PCIe link width */ - pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); + pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, pci_info->regs); @@ -541,9 +556,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pedr, 0xffffffff); - pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + pci_hose_read_config_word (hose, dev, pci_dsr, &temp16); if (temp16) { - pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); + pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); @@ -554,10 +569,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int fsl_is_pci_agent(struct pci_controller *hose) { + int pcie_cap_pos; u8 pcie_cap; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap == PCI_CAP_ID_EXP) { u8 header_type; @@ -582,6 +599,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, volatile ccsr_fsl_pci_t *pci; struct pci_region *r; pci_dev_t dev = PCI_BDF(busno,0,0); + int pcie_cap_pos; u8 pcie_cap; pci = (ccsr_fsl_pci_t *) pci_info->regs; @@ -631,11 +649,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, #endif } - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); - return(hose->last_busno + 1); } @@ -643,13 +661,15 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, void fsl_pci_config_unlock(struct pci_controller *hose) { pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); + int pcie_cap_pos; u8 pcie_cap; u16 pbfr; if (!fsl_is_pci_agent(hose)) return; - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { /* PCIe - set CFG_READY bit of Configuration Ready Register */ pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 2c07158..ed113bf 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -722,3 +722,68 @@ void pci_init(void) /* now call board specific pci_init()... */ pci_init_board(); } + +/* Returns the address of the requested capability structure within the + * device's PCI configuration space or 0 in case the device does not + * support it. + * */ +int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap) +{ + int pos; + u8 hdr_type; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); + + pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); + + if (pos) + pos = pci_find_cap(hose, dev, pos, cap); + + return pos; +} + +/* Find the header pointer to the Capabilities*/ +int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type) +{ + u16 status; + + pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + switch (hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + return PCI_CAPABILITY_LIST; + case PCI_HEADER_TYPE_CARDBUS: + return PCI_CB_CAPABILITY_LIST; + default: + return 0; + } +} + +int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) +{ + int ttl = PCI_FIND_CAP_TTL; + u8 id; + u8 next_pos; + + while (ttl--) { + pci_hose_read_config_byte(hose, dev, pos, &next_pos); + if (next_pos < CAP_START_POS) + break; + next_pos &= ~3; + pos = (int) next_pos; + pci_hose_read_config_byte(hose, dev, + pos + PCI_CAP_LIST_ID, &id); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos += PCI_CAP_LIST_NEXT; + } + return 0; +} diff --git a/include/pci.h b/include/pci.h index 911ba89..d462479 100644 --- a/include/pci.h +++ b/include/pci.h @@ -410,6 +410,9 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 +#define PCI_FIND_CAP_TTL 0x48 +#define CAP_START_POS 0x40 + /* Include the ID list */ #include <pci_ids.h> @@ -647,6 +650,13 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command); +extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap); +extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type); +extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, + int cap); + const char * pci_class_str(u8 class); int pci_last_busno(void); -- 1.8.0

1 0

[U-Boot] Got u-boot-2012.10 running on at91sam9200 - but why does it work?
by Arvid Brodin 11 Oct '13

11 Oct '13

Hi, I managed to get u-boot-2012.10 to boot from NOR flash on a custom at91rm9200 board by doing this: Signed-off-by: Arvid Brodin <arvid.brodin(a)xdin.com> --- arch/arm/cpu/arm920t/start.S | 8 +++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 14c9156..efc4ea3 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -294,9 +294,7 @@ clbss_e: _nand_boot_ofs: .word nand_boot #else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 + ldr lr, _board_init_r add lr, lr, r9 /* setup parameters for board_init_r */ mov r0, r5 /* gd_t */ @@ -304,8 +302,8 @@ _nand_boot_ofs: /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start +_board_init_r: + .word board_init_r #endif _rel_dyn_start_ofs: -- 1.8.1.5 (I also had to comment out the CONFIG_AT91RM9200EK define in my custom board config file.) Any idea why this is needed? I simply used a LED to see where the un-touched code failed, and noticed it reached the board_init_r call but never entered the function. I thought it a bit strange to first subtract _start in the variable definition and the add it again in the code, so I tried without it, and -- lo and behold! -- it worked. -- Arvid Brodin | Consultant (Linux) XDIN AB | Knarrarnäsgatan 7 | SE-164 40 Kista | Sweden | xdin.com

2 3

Re: [U-Boot] [RFC PATCH 4/3] i.MX6DQ/DLS: remove unused pad declarations
by Fabio Estevam 11 Oct '13

11 Oct '13

[Re-sending to the list as the original address was incorrect] On Thu, Oct 10, 2013 at 12:34 PM, Fabio Estevam <festevam(a)gmail.com> wrote: > On Thu, Oct 10, 2013 at 12:29 PM, Eric Nelson > <eric.nelson(a)boundarydevices.com> wrote: > >>> Personally, I think it is better to remove everything that is not used, >>> and add it later when it is really needed. >>> >> It seems like we mostly have consensus here. >> >> Fabio/Shawn/Tapani, can we get a head nod? > > Sounds good for me as well. > > Regards, > > Fabio Estevam

3 2

[U-Boot] [PATCH] imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
by Otavio Salvador 11 Oct '13

11 Oct '13

The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com>, Fabio Estevam <fabio.estevam(a)freescale.com> and Eric Bénard <eric(a)eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- Changes in v2: - Fix too long line - Move it just before MUX_PAD_CTRL(x) arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef..dec11a1 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t; #define MUX_SEL_INPUT_SHIFT 59 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ + MUX_MODE_SHIFT) #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ -- 1.8.4.rc3

2 2

[U-Boot] [PATCH v3] PCIe:change the method to get the address of a requested capability in configuration space.
by Zhao Qiang 11 Oct '13

11 Oct '13

Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475(a)freescale.com> --- Changes for v2: -Put an variable into "#ifdef" and "#endif" Changes for v3: -Modify the patch description arch/powerpc/include/asm/fsl_pci.h | 13 +------- drivers/pci/fsl_pci_init.c | 44 +++++++++++++++++++------- drivers/pci/pci.c | 65 ++++++++++++++++++++++++++++++++++++++ include/pci.h | 10 ++++++ 4 files changed, 108 insertions(+), 24 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 90b0a2f..6b12afa 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -32,22 +32,11 @@ /* Freescale-specific PCI config registers */ #define FSL_PCI_PBFR 0x44 -#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +#ifndef CONFIG_SYS_FSL_PCI_VER_3_X /* Currently only the PCIe capability is used, so hardcode the offset. * if more capabilities need to be justified, the capability link method * should be applied here */ -#define FSL_PCIE_CAP_ID 0x70 -#define PCI_DCR 0x78 /* PCIe Device Control Register */ -#define PCI_DSR 0x7a /* PCIe Device Status Register */ -#define PCI_LSR 0x82 /* PCIe Link Status Register */ -#define PCI_LCR 0x80 /* PCIe Link Control Register */ -#else -#define FSL_PCIE_CAP_ID 0x4c -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ #define FSL_PCIE_CFG_RDY 0x4b0 #endif #define FSL_PCI_CFG_READY 1 /* Endpoint: allow inbound configuration */ diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 76337fe..492efcf 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -308,6 +308,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int enabled, r, inbound = 0; u16 ltssm; u8 temp8, pcie_cap; + int pcie_cap_pos; + int pci_dcr; + int pci_dsr; + int pci_lsr; + +#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + int pci_lcr; +#endif + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr; struct pci_region *reg = hose->regions + hose->region_count; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); @@ -380,7 +389,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) hose->region_count++; /* see if we are a PCIe or PCI controller */ - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_dcr = pcie_cap_pos + 0x08; + pci_dsr = pcie_cap_pos + 0x0a; + pci_lsr = pcie_cap_pos + 0x12; + + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ @@ -419,15 +433,16 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) * - Master PERR (pci) * - ICCA (PCIe) */ - pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32); temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ - pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_dcr, temp32); #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM) + pci_lcr = pcie_cap_pos + 0x10; temp32 = 0; - pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32); + pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32); temp32 &= ~0x03; /* Disable ASPM */ - pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32); + pci_hose_write_config_dword(hose, dev, pci_lcr, temp32); udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { @@ -507,7 +522,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_int_en, 0xffffffff); /* Print the negotiated PCIe link width */ - pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); + pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, pci_info->regs); @@ -554,9 +569,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pedr, 0xffffffff); - pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + pci_hose_read_config_word(hose, dev, pci_dsr, &temp16); if (temp16) { - pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff); + pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff); } pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); @@ -567,10 +582,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) int fsl_is_pci_agent(struct pci_controller *hose) { + int pcie_cap_pos; u8 pcie_cap; pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap == PCI_CAP_ID_EXP) { u8 header_type; @@ -595,6 +612,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, volatile ccsr_fsl_pci_t *pci; struct pci_region *r; pci_dev_t dev = PCI_BDF(busno,0,0); + int pcie_cap_pos; u8 pcie_cap; pci = (ccsr_fsl_pci_t *) pci_info->regs; @@ -644,7 +662,8 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, #endif } - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); @@ -656,13 +675,14 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, void fsl_pci_config_unlock(struct pci_controller *hose) { pci_dev_t dev = PCI_BDF(hose->first_busno,0,0); + int pcie_cap_pos; u8 pcie_cap; u16 pbfr; if (!fsl_is_pci_agent(hose)) return; - - pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); + pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP); + pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap); if (pcie_cap != 0x0) { /* PCIe - set CFG_READY bit of Configuration Ready Register */ #ifdef CONFIG_SYS_FSL_PCI_VER_3_X diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d864f13..c57ea6f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -738,3 +738,68 @@ void pci_init(void) /* now call board specific pci_init()... */ pci_init_board(); } + +/* Returns the address of the requested capability structure within the + * device's PCI configuration space or 0 in case the device does not + * support it. + * */ +int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap) +{ + int pos; + u8 hdr_type; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type); + + pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F); + + if (pos) + pos = pci_find_cap(hose, dev, pos, cap); + + return pos; +} + +/* Find the header pointer to the Capabilities*/ +int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type) +{ + u16 status; + + pci_hose_read_config_word(hose, dev, PCI_STATUS, &status); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + switch (hdr_type) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + return PCI_CAPABILITY_LIST; + case PCI_HEADER_TYPE_CARDBUS: + return PCI_CB_CAPABILITY_LIST; + default: + return 0; + } +} + +int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap) +{ + int ttl = PCI_FIND_CAP_TTL; + u8 id; + u8 next_pos; + + while (ttl--) { + pci_hose_read_config_byte(hose, dev, pos, &next_pos); + if (next_pos < CAP_START_POS) + break; + next_pos &= ~3; + pos = (int) next_pos; + pci_hose_read_config_byte(hose, dev, + pos + PCI_CAP_LIST_ID, &id); + if (id == 0xff) + break; + if (id == cap) + return pos; + pos += PCI_CAP_LIST_NEXT; + } + return 0; +} diff --git a/include/pci.h b/include/pci.h index 7e3b3b6..477835e 100644 --- a/include/pci.h +++ b/include/pci.h @@ -426,6 +426,9 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 +#define PCI_FIND_CAP_TTL 0x48 +#define CAP_START_POS 0x40 + /* Include the ID list */ #include <pci_ids.h> @@ -663,6 +666,13 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command); +extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, + int cap); +extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, + u8 hdr_type); +extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, + int cap); + const char * pci_class_str(u8 class); int pci_last_busno(void); -- 1.8.0

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