October 2013 - U-Boot

[U-Boot] powerpc/mpc85xx: Increase image size
by York Sun 17 Oct '13

17 Oct '13

Scott, et al. I'd like to start the discussion to increase u-boot image size for some mpc85xx targets. As we all know the reset vector is at the very end and linking process start from the top. This gives us no good choice but to use fixed image size. While we have more and more features, the size increases inevitably. It's time to adjust the arbitrary size. We are now using 512KB. Shall we go with 768KB, or even 1MB? For the first step, I think we don't have to increase size for all targets. We can adjust those with CONFIG_SYS_TEXT_BASE=0xeff80000. Those are the most recent used. There are other targets which don't use NOR flash boot method. They should be considered as well. It is per board configuration. But it may be better if we keep them consistent. Please comment. Regards, York

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[U-Boot] [PATCH] Tegra114: Add support for more clock sources for T1x4 periphs
by Tom Warren 16 Oct '13

16 Oct '13

Some T1x4 peripherals can take up to 8 different clock sources (parents), including 4 new ones that don't exist on previous chips (PLLC2/C3/MEM2/SRC2). Expand clock/pll code/tables to support these additional bits/sources. Changes were made to some common code. Testing on T30/T20 showed no changes in periph clock sources/divisors. Signed-off-by: Tom Warren <twarren(a)nvidia.com> Change-Id: I396169cd5732ad42aeddefa70fc43f79e969a70d --- arch/arm/cpu/tegra-common/clock.c | 52 ++- arch/arm/cpu/tegra114-common/clock.c | 422 +++++++++++++--------- arch/arm/cpu/tegra30-common/clock.c | 6 - arch/arm/include/asm/arch-tegra/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra/clock.h | 17 + arch/arm/include/asm/arch-tegra114/clock-tables.h | 178 +++++---- 6 files changed, 422 insertions(+), 256 deletions(-) diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 268fb91..c703c40 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -304,13 +304,24 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == 4) { - clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, - source << OUT_CLK_SOURCE4_SHIFT); - } else { + + switch (mux_bits) { + case MASK_BITS_31_30: clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK, source << OUT_CLK_SOURCE_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE3_MASK, + source << OUT_CLK_SOURCE3_SHIFT); + break; + + case MASK_BITS_29_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK, + source << OUT_CLK_SOURCE4_SHIFT); + break; } + udelay(2); return 0; } @@ -561,3 +572,36 @@ void clock_init(void) /* Do any special system timer/TSC setup */ arch_timer_init(); } + +int clock_periph_enable(enum periph_id periph_id, enum clock_id parent, + int divisor) +{ + int mux_bits, divider_bits, source; + + /* Assert reset and enable clock */ + reset_set_enable(periph_id, 1); + clock_enable(periph_id); + + /* work out the source clock and set it */ + source = get_periph_clock_source(periph_id, parent, &mux_bits, + &divider_bits); + + assert(divisor >= 0); + divisor = (divisor - 1) << 1; + debug("%s: source %d, mux_bits %d, divider_bits %d, raw divisor = %x\n", + __func__, source, mux_bits, divider_bits, divisor); + + if (adjust_periph_pll(periph_id, source, mux_bits, divisor)) + return -1; + + debug("%s: periph %d, parent=%d, reg=%p = %x\n", __func__, + periph_id, parent, get_periph_source_reg(periph_id), + readl(get_periph_source_reg(periph_id))); + + /* wait for 2us */ + udelay(2); + + /* De-assert reset */ + reset_set_enable(periph_id, 0); + return 0; +} diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 5c4305a..9bb6529 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -46,13 +46,22 @@ enum clock_type_id { CLOCK_TYPE_MCPT, CLOCK_TYPE_PCM, CLOCK_TYPE_PCMT, - CLOCK_TYPE_PCMT16, CLOCK_TYPE_PDCT, CLOCK_TYPE_ACPT, CLOCK_TYPE_ASPTE, CLOCK_TYPE_PMDACD2T, CLOCK_TYPE_PCST, + CLOCK_TYPE_PC2CC3M, + CLOCK_TYPE_PC2CC3S_T, + CLOCK_TYPE_PC2CC3M_T, + CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */ + CLOCK_TYPE_MC2CC3P_A, + CLOCK_TYPE_M, + CLOCK_TYPE_MCPTM2C2C3, + CLOCK_TYPE_PC2CC3T_S, + CLOCK_TYPE_AC2CC3P_TS2, + CLOCK_TYPE_COUNT, CLOCK_TYPE_NONE = -1, /* invalid clock type */ }; @@ -61,12 +70,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. @@ -92,9 +95,6 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, - { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC), - CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_31_30}, { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, @@ -109,7 +109,45 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { MASK_BITS_31_29}, { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), - MASK_BITS_29_28} + MASK_BITS_29_28}, + + /* Additional clock types on T114 */ + /* CLOCK_TYPE_PC2CC3M */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3S_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_MC2CC3P_A */ + { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_M */ + { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE), + CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), + MASK_BITS_31_30}, + /* CLOCK_TYPE_MCPTM2C2C3 */ + { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC), + CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_PC2CC3T_S */ + { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE), + MASK_BITS_31_29}, + /* CLOCK_TYPE_AC2CC3P_TS2 */ + { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3), + CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2), + MASK_BITS_31_29}, }; /* @@ -122,110 +160,120 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = { TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT), TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT), TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM), - TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M), + TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T), + TYPE(PERIPHC_05h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T), /* 0x08 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_08h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T), TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T), TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T), /* 0x10 */ - TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA), + TYPE(PERIPHC_10h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_11h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_13h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_G3D, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_G2D, CLOCK_TYPE_MC2CC3P_A), /* 0x18 */ - TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */ - TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_EPP, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_MPE, CLOCK_TYPE_M), + TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T), /* 0x20 */ - TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT), + TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_21h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_22h, CLOCK_TYPE_NONE), TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT), - TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT), + TYPE(PERIPHC_24h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_25h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3), /* 0x28 */ - TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_29h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T), /* 0x30 */ - TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - - /* 0x38h */ /* Jumps to reg offset 0x3B0h */ - TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA), - TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */ + TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT), + TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE), + + /* 0x38 */ + TYPE(PERIPHC_38h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_39h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A), + TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE), + + /* 0x40 */ + TYPE(PERIPHC_G3D2, CLOCK_TYPE_MC2CC3P_A), /* start with 0x3b0 */ + TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S), TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT), TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT), - TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16), - TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16), + TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T), - /* 0x40 */ - TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT), - TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */ + /* 0x48 */ + TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_49h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2), + TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T), TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE), - /* 0x48 */ + /* 0x50 */ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE), TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE), - TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */ + TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PC2CC3M_T), + TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T), TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - - /* 0x50 */ - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE), - TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */ + TYPE(PERIPHC_55h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_56h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_57h, CLOCK_TYPE_NONE), + + /* 0x58 */ + TYPE(PERIPHC_58h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_59h, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE), + TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE), + TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT), - TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT), + TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T), }; /* @@ -244,7 +292,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(COP), NONE(TRIGSYS), NONE(RESERVED3), - NONE(RTC), + NONE(RESERVED4), NONE(TMR), PERIPHC_UART1, PERIPHC_UART2, /* and vfir 0x68 */ @@ -252,7 +300,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 8 */ NONE(GPIO), PERIPHC_SDMMC2, - NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */ + PERIPHC_SPDIF_IN, PERIPHC_I2S1, PERIPHC_I2C1, PERIPHC_NDFLASH, @@ -291,7 +339,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 40 */ NONE(KFUSE), - NONE(SBC1), /* SBC1, 0x34, is this SPI1? */ + NONE(SBC1), /* SBC1, SPI1 */ PERIPHC_NOR, NONE(RESERVED43), PERIPHC_SBC2, @@ -301,16 +349,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { /* 48 */ NONE(DSI), - PERIPHC_TVO, /* also CVE 0x40 */ - PERIPHC_MIPI, + NONE(RESERVED49), + PERIPHC_HSI, PERIPHC_HDMI, NONE(CSI), - PERIPHC_TVDAC, + NONE(RESERVED53), PERIPHC_I2C2, PERIPHC_UART3, /* 56 */ - NONE(RESERVED56), + NONE(MIPI_CAL), PERIPHC_EMC, NONE(USB2), NONE(USB3), @@ -320,7 +368,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(BSEV), /* Upper word 95:64 */ - PERIPHC_SPEEDO, + NONE(RESERVED64), PERIPHC_UART4, PERIPHC_UART5, PERIPHC_I2C3, @@ -335,41 +383,41 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { NONE(PCIEXCLK), NONE(AVPUCQ), NONE(RESERVED76), - NONE(RESERVED77), - NONE(RESERVED78), + NONE(TRACECLKIN), + NONE(SOC_THERM), NONE(DTV), /* 80 */ PERIPHC_NANDSPEED, PERIPHC_I2CSLOW, NONE(DSIB), - NONE(RESERVED83), - NONE(IRAMA), - NONE(IRAMB), - NONE(IRAMC), - NONE(IRAMD), + PERIPHC_TSEC, + NONE(RESERVED84), + NONE(RESERVED85), + NONE(RESERVED86), + NONE(EMUCIF), /* 88 */ - NONE(CRAM2), - NONE(RESERVED89), - NONE(MDOUBLER), - NONE(RESERVED91), - NONE(SUSOUT), + NONE(RESERVED88), + NONE(XUSB_HOST), + NONE(RESERVED90), + PERIPHC_MSENC, + NONE(RESERVED92), NONE(RESERVED93), NONE(RESERVED94), - NONE(RESERVED95), + NONE(XUSB_DEV), /* V word: 31:0 */ NONE(CPUG), NONE(CPULP), PERIPHC_G3D2, PERIPHC_MSELECT, - PERIPHC_TSENSOR, + NONE(V_RESERVED4), PERIPHC_I2S3, PERIPHC_I2S4, PERIPHC_I2C4, - /* 08 */ + /* 104 */ PERIPHC_SBC5, PERIPHC_SBC6, PERIPHC_AUDIO, @@ -379,63 +427,63 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = { PERIPHC_DAM2, PERIPHC_HDA2CODEC2X, - /* 16 */ + /* 112 */ NONE(ATOMICS), - NONE(RESERVED17), - NONE(RESERVED18), - NONE(RESERVED19), - NONE(RESERVED20), - NONE(RESERVED21), - NONE(RESERVED22), + NONE(V_RESERVED17), + NONE(V_RESERVED18), + NONE(V_RESERVED19), + NONE(V_RESERVED20), + NONE(V_RESERVED21), + NONE(V_RESERVED22), PERIPHC_ACTMON, - /* 24 */ - NONE(RESERVED24), - NONE(RESERVED25), - NONE(RESERVED26), - NONE(RESERVED27), + /* 120 */ + NONE(V_RESERVED24), + NONE(V_RESERVED25), + NONE(V_RESERVED26), + NONE(V_RESERVED27), PERIPHC_SATA, PERIPHC_HDA, - NONE(RESERVED30), - NONE(RESERVED31), + NONE(V_RESERVED30), + NONE(V_RESERVED31), /* W word: 31:0 */ NONE(HDA2HDMICODEC), - NONE(RESERVED1_SATACOLD), - NONE(RESERVED2_PCIERX0), - NONE(RESERVED3_PCIERX1), - NONE(RESERVED4_PCIERX2), - NONE(RESERVED5_PCIERX3), - NONE(RESERVED6_PCIERX4), - NONE(RESERVED7_PCIERX5), - - /* 40 */ + NONE(SATACOLD), + NONE(W_RESERVED2), + NONE(W_RESERVED3), + NONE(W_RESERVED4), + NONE(W_RESERVED5), + NONE(W_RESERVED6), + NONE(W_RESERVED7), + + /* 136 */ NONE(CEC), - NONE(PCIE2_IOBIST), - NONE(EMC_IOBIST), - NONE(HDMI_IOBIST), - NONE(SATA_IOBIST), - NONE(MIPI_IOBIST), - NONE(EMC1_IOBIST), - NONE(XUSB), - - /* 48 */ - NONE(CILAB), - NONE(CILCD), - NONE(CILE), - NONE(DSIA_LP), - NONE(DSIB_LP), - NONE(RESERVED21_ENTROPY), - NONE(RESERVED22_W), - NONE(RESERVED23_W), - - /* 56 */ - NONE(RESERVED24_W), + NONE(W_RESERVED9), + NONE(W_RESERVED10), + NONE(W_RESERVED11), + NONE(W_RESERVED12), + NONE(W_RESERVED13), + NONE(XUSB_PADCTL), + NONE(W_RESERVED15), + + /* 144 */ + NONE(W_RESERVED16), + NONE(W_RESERVED17), + NONE(W_RESERVED18), + NONE(W_RESERVED19), + NONE(W_RESERVED20), + NONE(ENTROPY), + NONE(W_RESERVED22), + NONE(W_RESERVED23), + + /* 152 */ + NONE(W_RESERVED24), NONE(AMX0), NONE(ADX0), NONE(DVFS), NONE(XUSB_SS), - NONE(EMC_DLL), + NONE(W_RESERVED29), NONE(MC1), NONE(EMC1), }; @@ -510,7 +558,7 @@ int get_periph_clock_source(enum periph_id periph_id, *mux_bits = clock_source[type][CLOCK_MAX_MUX]; - if (type == CLOCK_TYPE_PCMT16) + if (type == CLOCK_TYPE_PC2CC3M_T16) *divider_bits = 16; else *divider_bits = 8; @@ -583,21 +631,61 @@ enum periph_id clk_id_to_periph_id(int clk_id) switch (clk_id) { case PERIPH_ID_RESERVED3: + case PERIPH_ID_RESERVED4: case PERIPH_ID_RESERVED16: - case PERIPH_ID_RESERVED24: + case PERIPH_ID_RESERVED25: case PERIPH_ID_RESERVED35: + case PERIPH_ID_RESERVED36: + case PERIPH_ID_RESERVED38: + case PERIPH_ID_RESERVED39: case PERIPH_ID_RESERVED43: case PERIPH_ID_RESERVED45: - case PERIPH_ID_RESERVED56: + case PERIPH_ID_RESERVED49: + case PERIPH_ID_RESERVED53: + case PERIPH_ID_RESERVED64: case PERIPH_ID_RESERVED76: - case PERIPH_ID_RESERVED77: - case PERIPH_ID_RESERVED78: - case PERIPH_ID_RESERVED83: - case PERIPH_ID_RESERVED89: - case PERIPH_ID_RESERVED91: + case PERIPH_ID_RESERVED84: + case PERIPH_ID_RESERVED85: + case PERIPH_ID_RESERVED86: + case PERIPH_ID_RESERVED88: + case PERIPH_ID_RESERVED90: + case PERIPH_ID_RESERVED92: case PERIPH_ID_RESERVED93: case PERIPH_ID_RESERVED94: - case PERIPH_ID_RESERVED95: + case PERIPH_ID_V_RESERVED4: + case PERIPH_ID_V_RESERVED17: + case PERIPH_ID_V_RESERVED18: + case PERIPH_ID_V_RESERVED19: + case PERIPH_ID_V_RESERVED20: + case PERIPH_ID_V_RESERVED21: + case PERIPH_ID_V_RESERVED22: + case PERIPH_ID_V_RESERVED24: + case PERIPH_ID_V_RESERVED25: + case PERIPH_ID_V_RESERVED26: + case PERIPH_ID_V_RESERVED27: + case PERIPH_ID_V_RESERVED30: + case PERIPH_ID_V_RESERVED31: + case PERIPH_ID_W_RESERVED2: + case PERIPH_ID_W_RESERVED3: + case PERIPH_ID_W_RESERVED4: + case PERIPH_ID_W_RESERVED5: + case PERIPH_ID_W_RESERVED6: + case PERIPH_ID_W_RESERVED7: + case PERIPH_ID_W_RESERVED9: + case PERIPH_ID_W_RESERVED10: + case PERIPH_ID_W_RESERVED11: + case PERIPH_ID_W_RESERVED12: + case PERIPH_ID_W_RESERVED13: + case PERIPH_ID_W_RESERVED15: + case PERIPH_ID_W_RESERVED16: + case PERIPH_ID_W_RESERVED17: + case PERIPH_ID_W_RESERVED18: + case PERIPH_ID_W_RESERVED19: + case PERIPH_ID_W_RESERVED20: + case PERIPH_ID_W_RESERVED22: + case PERIPH_ID_W_RESERVED23: + case PERIPH_ID_W_RESERVED24: + case PERIPH_ID_W_RESERVED29: return PERIPH_ID_NONE; default: return clk_id; diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c index 74bd22b..89c3529 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/cpu/tegra30-common/clock.c @@ -60,12 +60,6 @@ enum { CLOCK_MAX_MUX = 8 /* number of source options for each clock */ }; -enum { - MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ - MASK_BITS_31_29, - MASK_BITS_29_28, -}; - /* * Clock source mux for each clock type. This just converts our enum into * a list of mux sources for use by the code. diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 074b3bc..5f52d60 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -236,6 +236,9 @@ enum { #define OUT_CLK_SOURCE_SHIFT 30 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define OUT_CLK_SOURCE3_SHIFT 29 +#define OUT_CLK_SOURCE3_MASK (7U << OUT_CLK_SOURCE3_SHIFT) + #define OUT_CLK_SOURCE4_SHIFT 28 #define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd..9495179 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -20,6 +20,12 @@ enum clock_osc_freq { CLOCK_OSC_FREQ_COUNT, }; +enum { + MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */ + MASK_BITS_31_29, + MASK_BITS_29_28, +}; + #include <asm/arch/clock-tables.h> /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 @@ -305,4 +311,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); /* SoC-specific TSC init */ void arch_timer_init(void); +/** + * Enable a peripheral clock with a certain clock source/divisor + * + * @param periph_id peripheral to enable/change + * @param src PLL id of required parent clock + * @param divisor required integer divisor (not 7.1) + * @return 0 if ok + * -1 on error (bad divisor, etc.). + */ +int clock_periph_enable(enum periph_id pid, int src, int divisor); + #endif /* _TEGRA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index d8fa0e1..19b8acf 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -40,7 +40,17 @@ enum clock_id { CLOCK_ID_OSC, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ + + /* + * These are clock ids that are used in table clock_source[][] + * but will not be assigned as a clock source for any peripheral. + */ + CLOCK_ID_DISPLAY2, + CLOCK_ID_CGENERAL2, + CLOCK_ID_CGENERAL3, + CLOCK_ID_MEMORY2, + CLOCK_ID_SRC2, + CLOCK_ID_NONE = -1, }; @@ -53,7 +63,7 @@ enum periph_id { PERIPH_ID_COP, PERIPH_ID_TRIGSYS, PERIPH_ID_RESERVED3, - PERIPH_ID_RTC, + PERIPH_ID_RESERVED4, PERIPH_ID_TMR, PERIPH_ID_UART1, PERIPH_ID_UART2, @@ -80,7 +90,7 @@ enum periph_id { /* 24 */ PERIPH_ID_3D, - PERIPH_ID_RESERVED24, + PERIPH_ID_RESERVED25, PERIPH_ID_DISP2, PERIPH_ID_DISP1, PERIPH_ID_HOST1X, @@ -93,10 +103,10 @@ enum periph_id { PERIPH_ID_AHBDMA, PERIPH_ID_APBDMA, PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, + PERIPH_ID_RESERVED36, PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, + PERIPH_ID_RESERVED38, + PERIPH_ID_RESERVED39, /* 40 */ PERIPH_ID_KFUSE, @@ -110,16 +120,16 @@ enum periph_id { /* 48 */ PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, + PERIPH_ID_RESERVED49, + PERIPH_ID_HSI, PERIPH_ID_HDMI, PERIPH_ID_CSI, - PERIPH_ID_TVDAC, + PERIPH_ID_RESERVED53, PERIPH_ID_I2C2, PERIPH_ID_UART3, /* 56 */ - PERIPH_ID_RESERVED56, + PERIPH_ID_MIPI_CAL, PERIPH_ID_EMC, PERIPH_ID_USB2, PERIPH_ID_USB3, @@ -129,7 +139,7 @@ enum periph_id { PERIPH_ID_BSEV, /* Upper word 95:64 (DEVICES_U) */ - PERIPH_ID_SPEEDO, + PERIPH_ID_RESERVED64, PERIPH_ID_UART4, PERIPH_ID_UART5, PERIPH_ID_I2C3, @@ -144,29 +154,29 @@ enum periph_id { PERIPH_ID_PCIEXCLK, PERIPH_ID_AVPUCQ, PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, + PERIPH_ID_TRACECLKIN, + PERIPH_ID_SOC_THERM, PERIPH_ID_DTV, /* 80 */ PERIPH_ID_NANDSPEED, PERIPH_ID_I2CSLOW, PERIPH_ID_DSIB, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, + PERIPH_ID_TSEC, + PERIPH_ID_RESERVED84, + PERIPH_ID_RESERVED85, + PERIPH_ID_RESERVED86, + PERIPH_ID_EMUCIF, /* 88 */ - PERIPH_ID_CRAM2, - PERIPH_ID_RESERVED89, - PERIPH_ID_MDOUBLER, - PERIPH_ID_RESERVED91, - PERIPH_ID_SUSOUT, + PERIPH_ID_RESERVED88, + PERIPH_ID_XUSB_HOST, + PERIPH_ID_RESERVED90, + PERIPH_ID_MSENC, + PERIPH_ID_RESERVED92, PERIPH_ID_RESERVED93, PERIPH_ID_RESERVED94, - PERIPH_ID_RESERVED95, + PERIPH_ID_XUSB_DEV, PERIPH_ID_VW_FIRST, /* V word: 31:0 */ @@ -174,7 +184,7 @@ enum periph_id { PERIPH_ID_CPULP, PERIPH_ID_3D2, PERIPH_ID_MSELECT, - PERIPH_ID_TSENSOR, + PERIPH_ID_V_RESERVED4, PERIPH_ID_I2S3, PERIPH_ID_I2S4, PERIPH_ID_I2C4, @@ -191,61 +201,61 @@ enum periph_id { /* 112 */ PERIPH_ID_ATOMICS, - PERIPH_ID_EX_RESERVED17, - PERIPH_ID_EX_RESERVED18, - PERIPH_ID_EX_RESERVED19, - PERIPH_ID_EX_RESERVED20, - PERIPH_ID_EX_RESERVED21, - PERIPH_ID_EX_RESERVED22, + PERIPH_ID_V_RESERVED17, + PERIPH_ID_V_RESERVED18, + PERIPH_ID_V_RESERVED19, + PERIPH_ID_V_RESERVED20, + PERIPH_ID_V_RESERVED21, + PERIPH_ID_V_RESERVED22, PERIPH_ID_ACTMON, /* 120 */ - PERIPH_ID_EX_RESERVED24, - PERIPH_ID_EX_RESERVED25, - PERIPH_ID_EX_RESERVED26, - PERIPH_ID_EX_RESERVED27, + PERIPH_ID_V_RESERVED24, + PERIPH_ID_V_RESERVED25, + PERIPH_ID_V_RESERVED26, + PERIPH_ID_V_RESERVED27, PERIPH_ID_SATA, PERIPH_ID_HDA, - PERIPH_ID_EX_RESERVED30, - PERIPH_ID_EX_RESERVED31, + PERIPH_ID_V_RESERVED30, + PERIPH_ID_V_RESERVED31, /* W word: 31:0 */ PERIPH_ID_HDA2HDMICODEC, - PERIPH_ID_RESERVED1_SATACOLD, - PERIPH_ID_RESERVED2_PCIERX0, - PERIPH_ID_RESERVED3_PCIERX1, - PERIPH_ID_RESERVED4_PCIERX2, - PERIPH_ID_RESERVED5_PCIERX3, - PERIPH_ID_RESERVED6_PCIERX4, - PERIPH_ID_RESERVED7_PCIERX5, + PERIPH_ID_SATACOLD, + PERIPH_ID_W_RESERVED2, + PERIPH_ID_W_RESERVED3, + PERIPH_ID_W_RESERVED4, + PERIPH_ID_W_RESERVED5, + PERIPH_ID_W_RESERVED6, + PERIPH_ID_W_RESERVED7, /* 136 */ PERIPH_ID_CEC, - PERIPH_ID_PCIE2_IOBIST, - PERIPH_ID_EMC_IOBIST, - PERIPH_ID_HDMI_IOBIST, - PERIPH_ID_SATA_IOBIST, - PERIPH_ID_MIPI_IOBIST, - PERIPH_ID_EMC1_IOBIST, - PERIPH_ID_XUSB, + PERIPH_ID_W_RESERVED9, + PERIPH_ID_W_RESERVED10, + PERIPH_ID_W_RESERVED11, + PERIPH_ID_W_RESERVED12, + PERIPH_ID_W_RESERVED13, + PERIPH_ID_XUSB_PADCTL, + PERIPH_ID_W_RESERVED15, /* 144 */ - PERIPH_ID_CILAB, - PERIPH_ID_CILCD, - PERIPH_ID_CILE, - PERIPH_ID_DSIA_LP, - PERIPH_ID_DSIB_LP, - PERIPH_ID_RESERVED21_ENTROPY, - PERIPH_ID_RESERVED22_W, - PERIPH_ID_RESERVED23_W, + PERIPH_ID_W_RESERVED16, + PERIPH_ID_W_RESERVED17, + PERIPH_ID_W_RESERVED18, + PERIPH_ID_W_RESERVED19, + PERIPH_ID_W_RESERVED20, + PERIPH_ID_ENTROPY, + PERIPH_ID_W_RESERVED22, + PERIPH_ID_W_RESERVED23, /* 152 */ - PERIPH_ID_RESERVED24_W, + PERIPH_ID_W_RESERVED24, PERIPH_ID_AMX0, PERIPH_ID_ADX0, PERIPH_ID_DVFS, PERIPH_ID_XUSB_SS, - PERIPH_ID_EMC_DLL, + PERIPH_ID_W_RESERVED29, PERIPH_ID_MC1, PERIPH_ID_EMC1, @@ -290,7 +300,7 @@ enum periphc_internal_id { PERIPHC_DISP2, /* 0x10 */ - PERIPHC_CVE, + PERIPHC_10h, PERIPHC_11h, PERIPHC_VI, PERIPHC_13h, @@ -305,17 +315,17 @@ enum periphc_internal_id { PERIPHC_VFIR, PERIPHC_EPP, PERIPHC_MPE, - PERIPHC_MIPI, + PERIPHC_HSI, PERIPHC_UART1, PERIPHC_UART2, /* 0x20 */ PERIPHC_HOST1X, PERIPHC_21h, - PERIPHC_TVO, + PERIPHC_22h, PERIPHC_HDMI, PERIPHC_24h, - PERIPHC_TVDAC, + PERIPHC_25h, PERIPHC_I2C2, PERIPHC_EMC, @@ -337,10 +347,20 @@ enum periphc_internal_id { PERIPHC_NOR, PERIPHC_CSITE, PERIPHC_I2S0, - PERIPHC_37h, + PERIPHC_DTV, - PERIPHC_VW_FIRST, /* 0x38 */ + PERIPHC_38h, + PERIPHC_39h, + PERIPHC_3ah, + PERIPHC_3bh, + PERIPHC_MSENC, + PERIPHC_TSEC, + PERIPHC_3eh, + PERIPHC_OSC, + + PERIPHC_VW_FIRST, + /* 0x40 */ PERIPHC_G3D2 = PERIPHC_VW_FIRST, PERIPHC_MSELECT, PERIPHC_TSENSOR, @@ -350,9 +370,9 @@ enum periphc_internal_id { PERIPHC_SBC5, PERIPHC_SBC6, - /* 0x40 */ + /* 0x48 */ PERIPHC_AUDIO, - PERIPHC_41h, + PERIPHC_49h, PERIPHC_DAM0, PERIPHC_DAM1, PERIPHC_DAM2, @@ -360,21 +380,21 @@ enum periphc_internal_id { PERIPHC_ACTMON, PERIPHC_EXTPERIPH1, - /* 0x48 */ + /* 0x50 */ PERIPHC_EXTPERIPH2, PERIPHC_EXTPERIPH3, PERIPHC_NANDSPEED, PERIPHC_I2CSLOW, PERIPHC_SYS, - PERIPHC_SPEEDO, - PERIPHC_4eh, - PERIPHC_4fh, - - /* 0x50 */ - PERIPHC_50h, - PERIPHC_51h, - PERIPHC_52h, - PERIPHC_53h, + PERIPHC_55h, + PERIPHC_56h, + PERIPHC_57h, + + /* 0x58 */ + PERIPHC_58h, + PERIPHC_59h, + PERIPHC_5ah, + PERIPHC_5bh, PERIPHC_SATAOOB, PERIPHC_SATA, PERIPHC_HDA, -- 1.8.1.5

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[U-Boot] [PATCH v2] Tegra114: SPL: Set SCLK source to CLK_M before PLLP init.
by Tom Warren 16 Oct '13

16 Oct '13

From: Jimmy Zhang <jimmzhang(a)nvidia.com> Based on the Tegra114 TRM, SCLK (system clock) can run up to 275MHz. At POR, the default SCLK source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 480MHz which is beyond the SCLK's upper limit. The fix is to set SCLK source to CLK_M before initializing PLLP. Tested on A02 dalmore board. Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Signed-off-by: Tom Warren <twarren(a)nvidia.com> --- v2: - Move/clarify comments and commit msg as per StephenW - Don't remove various unrelated clock enable/reset calls arch/arm/cpu/arm720t/tegra-common/spl.c | 12 ++++++++++++ arch/arm/cpu/arm720t/tegra114/cpu.c | 20 ++++++++++++++++++-- arch/arm/cpu/tegra114-common/clock.c | 13 +++++++++++++ arch/arm/include/asm/arch-tegra/clk_rst.h | 7 +++++++ 4 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 5171a8f..49a0544 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -17,6 +17,10 @@ #include <asm/arch/spl.h> #include "cpu.h" +__weak void set_avp_clock_to_clkm(void) +{ +} + void spl_board_init(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; @@ -24,6 +28,14 @@ void spl_board_init(void) /* enable JTAG */ writel(0xC0, &pmt->pmt_cfg_ctl); + /* + * On poweron, AVP's clock source (also called system clock, or SCLK) + * is set to PLLP_OUT0 with a frequency of 1MHz. Before initializing + * PLLP, we need to move the SCLK source to CLK_M temporarily, and then + * switch it to PLLP_OUT4 (204MHz) at a later time. + */ + set_avp_clock_to_clkm(); + board_init_uart_f(); /* Initialize periph GPIOs */ diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 51ecff7..8f7bce4 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -127,8 +127,8 @@ void t114_init_clocks(void) clrbits_le32(&flow->cluster_control, 1); /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no + * Switch system clock to PLLP_OUT4 (204 MHz), AVP will now run + * at 204 MHz. This is glitch free as only the source is changed, no * special precaution needed. */ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | @@ -322,3 +322,19 @@ void start_cpu(u32 reset_vector) /* If the CPU(s) don't already have power, power 'em up */ powerup_cpus(); } + +/* Use CLK_M (crystal freq) as AVP/COP (SCLK) clock source */ +void set_avp_clock_to_clkm(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clkrst->crc_sclk_brst_pol); + udelay(3); +} diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 5c4305a..e9a1a80 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -609,6 +609,7 @@ void clock_early_init(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; /* * PLLP output frequency set to 408Mhz @@ -653,6 +654,18 @@ void clock_early_init(void) /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); + + /* Set PLLP_OUT3 and 4 freqs to 102MHz and 204MHz */ + /* Assert RSTN before enable */ + reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + + /* set divisor and reenable */ + reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) + | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) + | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); } void arch_timer_init(void) diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 074b3bc..a4c17e7 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -209,6 +209,13 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; +#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_EN (0 << 0) +#define PLLP_OUT3_CLKEN (1 << 1) +#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT4_RSTN_EN (0 << 16) +#define PLLP_OUT4_CLKEN (1 << 17) + /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ #define PLLU_POWERDOWN (1 << 16) #define PLL_ENABLE_POWERDOWN (1 << 14) -- 1.8.1.5

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[U-Boot] [PATCH 0/2] Microblaze bug-fixes
by Michal Simek 16 Oct '13

16 Oct '13

Hi Tom, I have just found that there are two problems in microblaze compilation. Also I have found that my regular testing is broken that's why I haven't found these problems earlier. Would it be possible to add these two patches to your tree. I know it is late but still v2013.10 hasn't been tagged. Thanks, Michal Michal Simek (2): common: fsl: Fix broken SPDX-License-Identifier change microblaze: Fix watchdog initialization arch/microblaze/include/asm/processor.h | 1 - arch/microblaze/lib/board.c | 6 +++--- common/cmd_mfsl.c | 8 ++++---- drivers/watchdog/xilinx_tb_wdt.c | 6 ++---- 4 files changed, 9 insertions(+), 12 deletions(-) -- 1.8.2.3

3 4

[U-Boot] [PATCH 0/6] [U-boot] SMDK5420: Add support for FIMD and DP
by Ajay Kumar 16 Oct '13

16 Oct '13

This patchset adds support for FIMD and DP on SMDK5420. This patchset has dependency on Rajeshwari's base patchset: [V4] EXYNOS5420: Add SMDK5420 board support http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/170582 Also, for testing we need Naveen's i2c patchset aswell: i2c: improve s3c24x0 with High-speed and new SYS_I2C framework support http://www.mail-archive.com/u-boot@lists.denx.de/msg122679.html Ajay Kumar (6): [PATCH 1/6] exynos_fb: Remove usage of static defines [PATCH 2/6] arm: exynos: Add RPLL for Exynos5420 [PATCH 3/6] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 [PATCH 4/6] video: exynos_fimd: Add framework to disable FIMD sysmmu [PATCH 5/6] smdk5420: Implement callbacks needed by exynos_fb driver [PATCH 6/6] CONFIG: SMDK5420: Enable FIMD and DP arch/arm/cpu/armv7/exynos/clock.c | 74 +++++++++++++++- arch/arm/cpu/armv7/exynos/clock_init.h | 3 + arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 13 +++ arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +- arch/arm/dts/exynos5420.dtsi | 5 ++ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/system.h | 1 + board/samsung/common/board.c | 15 ++++ board/samsung/smdk5420/smdk5420.c | 118 +++++++------------------ doc/device-tree-bindings/video/exynos-fb.txt | 2 + drivers/video/exynos_fb.c | 20 ++--- drivers/video/exynos_fimd.c | 12 +++ include/configs/exynos5250-dt.h | 2 - include/configs/smdk5420.h | 8 ++ 14 files changed, 172 insertions(+), 104 deletions(-) -- 1.7.12.4

3 20

[U-Boot] [PATCH v4] socfpga: Adding Freeze Controller driver
by Chin Liang See 16 Oct '13

16 Oct '13

Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Wolfgang Denk <wd(a)denx.de> CC: Pavel Machek <pavel(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)altera.com> Cc: Tom Rini <trini(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> --- Changes for v4 - Removed additional lines - Single function call to freeze and thaw all channels Changes for v3 - Removed unused macro in freeze_controller.h Changes for v2 - Removed FREEZE_CONTROLLER_FSM_HW - Removed the get_timer_count_masked and convert to use delay in us - Used shorter local variables --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/freeze_controller.c | 216 ++++++++++++++++++++ arch/arm/cpu/armv7/socfpga/spl.c | 9 + .../include/asm/arch-socfpga/freeze_controller.h | 50 +++++ 4 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/socfpga/freeze_controller.c create mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 0859e44..10d20f2 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -14,7 +14,7 @@ LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o COBJS-y := misc.o timer.o reset_manager.o system_manager.o -COBJS-$(CONFIG_SPL_BUILD) += spl.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c new file mode 100644 index 0000000..330b4aa --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/timer.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Default state from cold reset is FREEZE_ALL; the global + * flag is set to TRUE to indicate the IO banks are frozen + */ +static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] + = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, + FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; + +/* Freeze HPS IOs */ +void sys_mgr_frzctrl_freeze_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_value; + u32 reg_cfg_mask; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Freeze channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset = (u32)( + &freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low enrnsl, plniotri + * and niotri signals + */ + reg_cfg_mask = + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * Assert active low bhniotri signal and de-assert + * active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; + } + + /* Freeze channel 3 */ + /* + * Assert active low enrnsl, plniotri and + * niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * assert active low bhniotri & nfrzdrv signals, + * de-assert active high csrdone and assert + * active high frzreg and nfrzdrv signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; + reg_value + = (reg_value & ~reg_cfg_mask) + | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK + | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * assert active high reinit signal and de-assert + * active high pllbiasen signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value + = (reg_value & + ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) + | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; +} + +/* Unfreeze/Thaw HPS IOs */ +void sys_mgr_frzctrl_thaw_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_cfg_mask; + u32 reg_value; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Thaw channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset + = (u32)(&freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low bhniotri signal and + * de-assert active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low plniotri and niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(ioctrl_reg_offset, + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; + } + + /* Thaw channel 3 */ + /* de-assert active high reinit signal */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Note: Delay for 40ns at min + * assert active high pllbiasen signals + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); + + /* + * Delay 1000 intosc. intosc is based on eosc1 + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 1000 = 20us + */ + udelay(20); + + /* + * de-assert active low bhniotri signals, + * assert active high csrdone and nfrzdrv signal + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value = (reg_value + | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) + & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * Delay 33 intosc + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 33 = 660ns ~= 1us + */ + udelay(1); + + /* de-assert active low plniotri and niotri signals */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + + setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * Note: Delay for 40ns at min + * de-assert active high frzreg signal + */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); + + /* + * Note: Delay for 40ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; +} + diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 74bceab..36a00c3 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/reset_manager.h> #include <spl.h> #include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,10 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + debug("Freezing all I/O banks\n"); + /* freeze all IO banks */ + sys_mgr_frzctrl_freeze_req(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ @@ -34,6 +39,10 @@ void spl_board_init(void) /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + debug("Unfreezing/Thaw all I/O banks\n"); + /* unfreeze / thaw all IO banks */ + sys_mgr_frzctrl_thaw_req(); + /* enable console uart printing */ preloader_console_init(); } diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h new file mode 100644 index 0000000..120f20e --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FREEZE_CONTROLLER_H_ +#define _FREEZE_CONTROLLER_H_ + +struct socfpga_freeze_controller { + u32 vioctrl; + u32 padding[3]; + u32 hioctrl; + u32 src; + u32 hwctrl; +}; + +#define FREEZE_CHANNEL_NUM (4) + +typedef enum { + FREEZE_CTRL_FROZEN = 0, + FREEZE_CTRL_THAWED = 1 +} FREEZE_CTRL_CHAN_STATE; + +#define SYSMGR_FRZCTRL_ADDRESS 0x40 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 +#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 +#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 +#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 + +void sys_mgr_frzctrl_freeze_req(void); +void sys_mgr_frzctrl_thaw_req(void); + +#endif /* _FREEZE_CONTROLLER_H_ */ -- 1.7.9.5

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[U-Boot] [PATCH v3 0/11] Support for the kmp204x reference design
by Valentin Longchamp 16 Oct '13

16 Oct '13

This series includes all the needed patches to run u-boot on Keymile's kmp204x reference design. The kmp204x is a reference design based on Freescale's P2040/P2041 SoC. It is supposed to be a reference platform for future boards. There is currently only one board that is based on this design which is called kmlion1. The first 10 patches of the series are small changes to the generic Keymile board support code as well as minor changes to some Freescale drivers and CPU support. The final patch 11 is where the new kmp204x code is introduced. It is mostly based on the existing P2041rdb code by Freescale which was adapted to our design. Changes in v3: - Add SYS_MALLOC_LEN to km_arm.h as well, as it was omitted before. - take the new I2C defines into account and use CONFIG_SYS_I2C_INIT_BOARD instead of an additional option and define it only for the I2C bitbang KM boards (km_arm and km82xx) and not for all KM boards. - add a call to fman_enable_port in fm_enable_port enable the port in hardware as well. - rebased on mainline u-boot 2013.10-rc2 (+ a few patches) - use new licensing string - move BCH #defines before keymile-common.h #include - remove common RCW printing patch - remove RCW printing form checkboard() as it is now in mpc85xx/cpu.c - new I2C #defines for new I2C subsystem - remove patch km-powerpc: move CONFIG_FLASH_CFI_MTD from km-powerpc.h since km-powerpc is not included by kmp204x.h - fix RCW for new IRQ/GPIO usage of kmp204x - set netdev to eth0 since the new DTS now correctly assigns FM1@DTSEC to eth0 Changes in v2: - Introduce CONFIG_KM_I2C_ABORT #define to avoid #if !defined in common.c - add CONFIG_KM_COMMON_ETH_INIT for the km board that need the common.c board_eth_init - when refresh rate gets halved for extended range temperature operations, the srt bit in the mode register 2 is set. - Remove patch "5/8 fsl: do not define FSL_SRIO_PCIE_BOOT_MASTER for all P2041 systems" from the series as it is not needed with current u-boot. - fix the defines used in kmp204x/law.c for the lbus local address windows. - fix the header files to include Freescale's copyrights - integrate Scott's feedback Valentin Longchamp (11): powerpc: cast bi_memsize to ulong for %ld usage km-powerpc: move SYS_MALLOC_LEN out of keymile-common.h KM: fix typo in default environment KM: define CONFIG_SYS_I2C_INIT_BOARD only for concerned board KM: add CONFIG_KM_COMMON_ETH_INIT for km common eth init mpc8xxx: call i2c_set_bus_num in __get_spd mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it net/fman: add a fm_enable_port function mtd/fsl_elbc: take NAND_ECC_SOFT_BCH config option into account fsl/mpc85xx: define common serdes_clock_to_string function mpc85xx: introduce the kmp204x reference design support MAINTAINERS | 1 + arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 21 + arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 17 + .../powerpc/cpu/mpc8xxx/ddr/common_timing_params.h | 1 + arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 7 +- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 + .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 5 + arch/powerpc/cpu/mpc8xxx/ddr/main.c | 6 +- arch/powerpc/include/asm/fsl_ddr_dimm_params.h | 1 + arch/powerpc/include/asm/fsl_serdes.h | 1 + arch/powerpc/lib/board.c | 2 +- board/freescale/b4860qds/b4860qds.c | 16 - board/freescale/corenet_ds/corenet_ds.c | 14 - board/freescale/p2041rdb/p2041rdb.c | 14 - board/freescale/t4qds/t4240qds.c | 16 - board/keymile/common/common.c | 27 +- board/keymile/kmp204x/Makefile | 48 +++ board/keymile/kmp204x/ddr.c | 64 +++ board/keymile/kmp204x/eth.c | 71 ++++ board/keymile/kmp204x/kmp204x.c | 258 ++++++++++++ board/keymile/kmp204x/kmp204x.h | 15 + board/keymile/kmp204x/law.c | 40 ++ board/keymile/kmp204x/pbi.cfg | 35 ++ board/keymile/kmp204x/pci.c | 35 ++ board/keymile/kmp204x/rcw_kmp204x.cfg | 11 + board/keymile/kmp204x/tlb.c | 110 +++++ boards.cfg | 1 + drivers/mtd/nand/fsl_elbc_nand.c | 6 +- drivers/net/fm/b4860.c | 7 + drivers/net/fm/fm.h | 1 + drivers/net/fm/init.c | 8 + drivers/net/fm/p1023.c | 7 + drivers/net/fm/p4080.c | 7 + drivers/net/fm/p5020.c | 7 + drivers/net/fm/p5040.c | 7 + drivers/net/fm/t4240.c | 7 + include/configs/km/keymile-common.h | 6 +- include/configs/km/km-powerpc.h | 6 + include/configs/km/km_arm.h | 8 +- include/configs/km/kmp204x-common.h | 451 +++++++++++++++++++++ include/configs/km82xx.h | 2 + include/configs/kmp204x.h | 68 ++++ include/fm_eth.h | 1 + 43 files changed, 1343 insertions(+), 97 deletions(-) create mode 100644 board/keymile/kmp204x/Makefile create mode 100644 board/keymile/kmp204x/ddr.c create mode 100644 board/keymile/kmp204x/eth.c create mode 100644 board/keymile/kmp204x/kmp204x.c create mode 100644 board/keymile/kmp204x/kmp204x.h create mode 100644 board/keymile/kmp204x/law.c create mode 100644 board/keymile/kmp204x/pbi.cfg create mode 100644 board/keymile/kmp204x/pci.c create mode 100644 board/keymile/kmp204x/rcw_kmp204x.cfg create mode 100644 board/keymile/kmp204x/tlb.c create mode 100644 include/configs/km/kmp204x-common.h create mode 100644 include/configs/kmp204x.h -- 1.8.0.1

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[U-Boot] [PATCH] ARM: mxs: Do not reconfigure FEC clock in FEC init
by Marek Vasut 16 Oct '13

16 Oct '13

Do not reconfigure the FEC clock during board_eth_init(), otherwise the FEC might have stability issues, refuse to autonegotiate link entirely or even corrupt packets while indicating correct checksum on them. Instead, move the FEC clock init to board_early_init_f(), where all the other upstream clock are initialized and also make sure there is proper stabilization delay. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Hector Palacios <hector.palacios(a)digi.com> Cc: Oliver Metz <oliver(a)freetz.org> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)ti.com> --- board/bluegiga/apx4devkit/apx4devkit.c | 10 ++++------ board/denx/m28evk/m28evk.c | 21 +++++++++++---------- board/freescale/mx28evk/mx28evk.c | 9 +++++---- board/schulercontrol/sc_sps_1/sc_sps_1.c | 19 +++++++++++-------- 4 files changed, 31 insertions(+), 28 deletions(-) NOTE: I'd like to get this into current release as it fixes a serious issue I observe here on the MX28EVK (packets being corrupted on long transfers initiated early after boot). Please test this and report back ASAP. diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c index 08e79bd..044a182 100644 --- a/board/bluegiga/apx4devkit/apx4devkit.c +++ b/board/bluegiga/apx4devkit/apx4devkit.c @@ -39,6 +39,10 @@ int board_early_init_f(void) /* SSP0 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + udelay(10000); +#endif return 0; } @@ -79,12 +83,6 @@ int board_eth_init(bd_t *bis) int ret; struct eth_device *dev; - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXS: Unable to init FEC clocks\n"); - return ret; - } - ret = fecmxc_initialize(bis); if (ret) { printf("FEC MXS: Unable to init FEC\n"); diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index 33d38cf..5065ee8 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_early_init_f(void) { + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + /* IO0 clock at 480MHz */ mxs_set_ioclk(MXC_IOCLK0, 480000); /* IO1 clock at 480MHz */ @@ -36,6 +39,14 @@ int board_early_init_f(void) /* SSP2 clock at 160MHz */ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, + CLKCTRL_ENET_TIME_SEL_RMII_CLK); + udelay(10000); +#endif + #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | @@ -110,19 +121,9 @@ int fecmxc_mii_postcall(int phy) int board_eth_init(bd_t *bis) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; struct eth_device *dev; int ret; - ret = cpu_eth_init(bis); - if (ret) - return ret; - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, - CLKCTRL_ENET_TIME_SEL_RMII_CLK); - #if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) /* Reset the new PHY */ gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 5005fe2..2c93c44 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -41,6 +41,11 @@ int board_early_init_f(void) /* SSP2 clock at 160MHz */ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + udelay(10000); +#endif + #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | @@ -102,10 +107,6 @@ int board_eth_init(bd_t *bis) struct eth_device *dev; int ret; - ret = cpu_eth_init(bis); - if (ret) - return ret; - /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, &clkctrl_regs->hw_clkctrl_enet); diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c index 7f0b591..9d3c970 100644 --- a/board/schulercontrol/sc_sps_1/sc_sps_1.c +++ b/board/schulercontrol/sc_sps_1/sc_sps_1.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_early_init_f(void) { + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + /* IO0 clock at 480MHz */ mxs_set_ioclk(MXC_IOCLK0, 480000); /* IO1 clock at 480MHz */ @@ -36,6 +39,14 @@ int board_early_init_f(void) /* SSP2 clock at 96MHz */ mxs_set_sspclk(MXC_SSPCLK2, 96000, 0); +#ifdef CONFIG_CMD_NET + cpu_eth_init(NULL); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK, + CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); + udelay(10000); +#endif + #ifdef CONFIG_CMD_USB mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT); mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 | @@ -69,16 +80,8 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; int ret; - ret = cpu_eth_init(bis); - - clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, - CLKCTRL_ENET_TIME_SEL_MASK, - CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN); - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { printf("FEC MXS: Unable to init FEC0\n"); -- 1.8.4.rc3

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[U-Boot] [PATCH] spi: mxc: Fix data loss for non aligned write buffers.
by Martin Fuzzey 16 Oct '13

16 Oct '13

When writing buffers that are not 32 bit aligned data loss occurs. This can also occur when the total transfer size is not a multiple of 4 bytes since the extra bytes are written first causing the rest to be unaligned. This can be seen by writing to SPI flash a 57 byte file containing 00 01 .. 38: U-Boot > dhcp data.bin ... Bytes transferred = 57 (39 hex) U-Boot > md.b $loadaddr 72000000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................ 72000010: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................ 72000020: 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f !"#$%&'()*+,-./ 72000030: 30 31 32 33 34 35 36 37 38 ff ff ff ff ff ff ff 012345678....... U-Boot > sf write $loadaddr 0 $filesize U-Boot > mw.b $loadaddr ff 100 U-Boot > sf read $loadaddr 0 100 U-Boot > md.b $loadaddr 72000000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................ 72000010: 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................ 72000020: 20 21 22 23 24 29 2a 2b 2c 31 32 33 34 ff ff ff !"#$)*+,1234... 72000030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ [bytes 25-28, 2d-30, 35-38 are missing] Activating debug in the write command gave: spi_xchg_single: bitlen 256 dout 0x72000000 din 0x0 Sending SPI 0x10203 Sending SPI 0x4050607 Sending SPI 0x8090a0b Sending SPI 0xc0d0e0f Sending SPI 0x10111213 Sending SPI 0x14151617 Sending SPI 0x18191a1b Sending SPI 0x1c1d1e1f SPI Rx: 0xffffffff 0xffffffff ... SPI Rx: 0xffffffff 0xffffffff spi_xchg_single: bitlen 200 dout 0x72000020 din 0x0 Sending SPI 0x20 Sending SPI 0x21222324 Sending SPI 0x292a2b2c <=== What happened to 25262728? Sending SPI 0x31323334 Sending SPI 0xffffffff ... SF: program success 57 bytes @ 0x0 The problem was that the pointer was being incremented twice for the non aligned case. Signed-off-by: Martin Fuzzey <mfuzzey(a)parkeon.com> --- drivers/spi/mxc_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 859c43f..964a2b7 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -274,8 +274,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, } else { data = *(u32 *)dout; data = cpu_to_be32(data); + dout += 4; } - dout += 4; } debug("Sending SPI 0x%x\n", data); reg_write(&regs->txdata, data);

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[U-Boot] [PATCH] ARM: OMAP5: DDR3: Change io settings
by Sricharan R 16 Oct '13

16 Oct '13

Changing the IO settings to turn on VREF_DQ and disable weak pullup for DQS/nDQS. Signed-off-by: Sricharan R <r.sricharan(a)ti.com> --- arch/arm/include/asm/arch-omap5/omap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 414d37a..3c2306f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -145,9 +145,9 @@ struct s32ktimer { #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 #define EFUSE_1 0x45145100 -- 1.7.9.5

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