October 2013 - U-Boot

[U-Boot] [PATCH V2] ARM: OMAP5: DDR3: Change io settings
by Sricharan R 16 Oct '13

16 Oct '13

The DDR DQ lines are enabled with weak pull. So the DQ line was not staying at Vref when IDLE (retreats to ground) and because of this there were extra transitions and noise. So change from 0x64656465 to 0x64646464 to remove the weak pull. Also internal VREF_DQOUT is set to 0. This has to enabled as well. With the above two changes better memory stability was observed with extended temperature ranges around 100C Signed-off-by: Sricharan R <r.sricharan(a)ti.com> --- [V2] Added more descriptive commit log arch/arm/include/asm/arch-omap5/omap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 414d37a..3c2306f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -145,9 +145,9 @@ struct s32ktimer { #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 #define EFUSE_1 0x45145100 -- 1.7.9.5

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[U-Boot] [PATCH] mtd: fix warnings due to 64-bit partition support
by Scott Wood 16 Oct '13

16 Oct '13

commit 39ac34473f3c96e77cbe03a49141771ed1639486 ("cmd_mtdparts: use 64 bits for flash size, partition size & offset") introduced warnings in a couple places due to printf formats or pointer casting. This patch fixes the warnings pointed out here: http://lists.denx.de/pipermail/u-boot/2013-October/164981.html Signed-off-by: Scott Wood <scottwood(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Paul Burton <paul.burton(a)imgtec.com> Cc: Tom Rini <trini(a)ti.com> --- Alternatively, given the imminent release, perhaps all but the first patch of my recent NAND pull request should be reverted. The first patch was a regression fix, but on a second look the remaining patches look more like enabling a new feature (and I didn't look too closely at the ubi patches because Stefan had acked them and asked me to apply; patch 4 is clearly not a bugfix). I'm not sure why I didn't catch these warnings as I did run a makeall on arm and ppc. The only thing I can guess is that I forgot to check the ppc results, or I missed them among other pre-existing warnings such as the "AltiVec not supported in this target" warnings I get from 86xx builds. --- common/fdt_support.c | 4 ++-- fs/cramfs/cramfs.c | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index b034c98..1f0d8f5 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -766,11 +766,11 @@ int fdt_node_set_part_info(void *blob, int parent_offset, part = list_entry(pentry, struct part_info, link); - debug("%2d: %-20s0x%08x\t0x%08x\t%d\n", + debug("%2d: %-20s0x%08llx\t0x%08llx\t%d\n", part_num, part->name, part->size, part->offset, part->mask_flags); - sprintf(buf, "partition@%x", part->offset); + sprintf(buf, "partition@%llx", part->offset); add_sub: ret = fdt_add_subnode(blob, parent_offset, buf); if (ret == -FDT_ERR_NOSPACE) { diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c index e578a1e..fd8e4ef 100644 --- a/fs/cramfs/cramfs.c +++ b/fs/cramfs/cramfs.c @@ -43,9 +43,10 @@ struct cramfs_super super; * device address space offset, so we need to shift it by a device start address. */ #if !defined(CONFIG_SYS_NO_FLASH) extern flash_info_t flash_info[]; -#define PART_OFFSET(x) (x->offset + flash_info[x->dev->id->num].start[0]) +#define PART_OFFSET(x) ((ulong)x->offset + \ + flash_info[x->dev->id->num].start[0]) #else -#define PART_OFFSET(x) (x->offset) +#define PART_OFFSET(x) ((ulong)x->offset) #endif static int cramfs_read_super (struct part_info *info) -- 1.8.1.2

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[U-Boot] help on adding bootelf to u-boot
by Robin Fernandes 16 Oct '13

16 Oct '13

hi sir/madam I am trying to run bootelf command from u-boot. But the command is not inbuilt in it. So could you please let me know what is the procedure to compile.. -- Thanks and Regards *Robin Fernandes* Global Edge Software Ltd. Bangalore, India Tel : _+91 88 6164 8965_ Web : www.globaledgesoft.com Email: /robin.fernandes(a)globaledgesoft.com/ Have a Good day. -----------------------------------------

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[U-Boot] u-boot-xlnx 'master-next' branch: usb not working for microzed
by oller 16 Oct '13

16 Oct '13

Hi, I've been working with xilinx's microzed board (zynq) recently. The actual goal is a fsbl-less u-boot. But even with fsbl - USB is not working in u-boot-xlnx 'master-next' branch. At the same time it works in the 'master'. Mostly interested in 'master-next'. Has anyone tried USB in the 'master-next' for microzed/zedboard? OS: Ubuntu 13.04 x64 board: MicroZed u-boot-xlnx 'master-next' rev: bbd91fc9ae290c31dc52fd8322f43f67ddd39247 u-boot-xlnx 'master' rev: 0f6dbff16b792a106f52ca37f4503335af30601b cross-tools: cross compiler built with yocto poky: > export CROSS_COMPILE=arm-poky-linux-gnueabi- > export > PATH=/opt/poky/1.4.2/sysroots/x86_64-pokysdk-linux/usr/bin/armv7a-vfp-neon-poky-linux-gnueabi/:$PATH incorrect output: > ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver > ehci-pci: EHCI PCI platform driver correct output: > Found SMSC USB3320 ULPI transceiver. > ULPI integrity check: passed. > xusbps-ehci xusbps-ehci.0: Xilinx PS USB EHCI Host Controller > xusbps-ehci xusbps-ehci.0: new USB bus registered, assigned bus number 1 > xusbps-ehci xusbps-ehci.0: irq 53, io mem 0x00000000 > xusbps-ehci xusbps-ehci.0: USB 2.0 started, EHCI 1.00 Thanks -- View this message in context: http://u-boot.10912.n7.nabble.com/u-boot-xlnx-master-next-branch-usb-not-wo… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH] powerpc/t1040: Update defines to support T1040SoC personalities
by Priyanka Jain 16 Oct '13

16 Oct '13

T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in config_mpc85xx.h and immap_85xx.h to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> --- Based on u-boot-mpc85xx/next branch. arch/powerpc/include/asm/config_mpc85xx.h | 3 ++- arch/powerpc/include/asm/immap_85xx.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 946ea97..89a340a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -651,7 +651,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e516e07..9d6268d 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1847,7 +1847,8 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 -- 1.7.4.1

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[U-Boot] [PATCH 1/2] serial: xuartlite: Staticize local functions
by Axel Lin 16 Oct '13

16 Oct '13

Staticize local functions in xuartlite driver. Signed-off-by: Axel Lin <axel.lin(a)ingics.com> --- drivers/serial/serial_xuartlite.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index 9c1d025..daaf155 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -39,7 +39,7 @@ static struct uartlite *userial_ports[4] = { #endif }; -void uartlite_serial_putc(const char c, const int port) +static void uartlite_serial_putc(const char c, const int port) { struct uartlite *regs = userial_ports[port]; @@ -51,13 +51,13 @@ void uartlite_serial_putc(const char c, const int port) out_be32(&regs->tx_fifo, c & 0xff); } -void uartlite_serial_puts(const char *s, const int port) +static void uartlite_serial_puts(const char *s, const int port) { while (*s) uartlite_serial_putc(*s++, port); } -int uartlite_serial_getc(const int port) +static int uartlite_serial_getc(const int port) { struct uartlite *regs = userial_ports[port]; @@ -66,7 +66,7 @@ int uartlite_serial_getc(const int port) return in_be32(&regs->rx_fifo) & 0xff; } -int uartlite_serial_tstc(const int port) +static int uartlite_serial_tstc(const int port) { struct uartlite *regs = userial_ports[port]; -- 1.8.1.2

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[U-Boot] Preliminary schedule for U-Boot miniconf at ELCE2013
by Detlev Zundel 15 Oct '13

15 Oct '13

Hi, thanks to the excellent feedback we got on the U-Boot mini conference next week in Edinburgh, this is the current schedule for the mini conference next week: ,---------------+-----------------+----------------------------------------------. | Time | Speaker | Summary | |---------------+-----------------+----------------------------------------------+ | 13:00 - 13:20 | Marek Vasut | Generating bootstreams on i.mx28 | | | | without any external tools | | 13:30 - 13:50 | Scott Wood | SPL loading SPL (a.k.a. TPL) and SPL | | | | as just another U-Boot config | | 14:00 - 14:20 | Stefano Babic | Falcon Boot: current status and enhancements | |---------------+-----------------+----------------------------------------------+ | 14:30 - 14:45 | | Break | |---------------+-----------------+----------------------------------------------+ | 14:45 - 15:05 | Jagan Teki | Android Fastboot | | 15:15 - 15:35 | Lukasz Majewski | DFU | | 15:45 - 16:05 | Simon Glass | Driver model, Kconfig, Patman tutorial | |---------------+-----------------+----------------------------------------------+ | 16:15 - 16:30 | | Break | |---------------+-----------------+----------------------------------------------+ | 16:30 - 17:00 | Everybody | Open Discussion | `---------------+-----------------+----------------------------------------------/ (This is a transcript from the wiki page[1]) For the open discussion, we would especially like to ask all maintainers for proposals of things to discuss. The wiki page is a good place to collect ideas here. For the speakers: As far as I know, it should be possible to hook up your laptop to a beamer in the room, but it would be worthwhile to bring the slides as PDF or ODP no a usb stick in case some problems pop up. We will also collect the slides to publish them on the U-Boot web pages afterwards. Let us know if there are any problems that we may need to look into, otherwise we are looking forward to seeing you next week in Scotland! Best wishes Detlev [1] http://www.denx.de/wiki/edit/U-Boot/MiniSummitELCE2013?t=1381844125 -- I hear and I forget. I see and I remember. I do and I understand. -- Confucius -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu(a)denx.de

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[U-Boot] Pull request: u-boot-spi/master
by Jagannadha Sutradharudu Teki 15 Oct '13

15 Oct '13

Hi Tom, Simple PR - cleanup + some misc changes. Thanks, Jagan. The following changes since commit a707b3db562c4c3ae580e2eabb05b59adcc31846: buildman: Use env to pick the python from $PATH (2013-10-15 08:44:28 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 6d5ce1bd0048617d48c05de1a84fae8696081127: spi: mxc_spi: Fix double incrementing read pointer for unaligned buffers (2013-10-16 00:14:30 +0530) ---------------------------------------------------------------- Bo Shen (1): sf: probe: Add missing Atmel at25df321 flash Jagannadha Sutradharudu Teki (4): sf_ops: Unify bank_sel calculation code sf: Minor cleanups. sf: Add GPL-2.0+ SPDX-License-Identifier for missing ones spi: Add GPL-2.0+ SPDX-License-Identifier for missing files Timo Herbrecher (1): spi: mxc_spi: Fix double incrementing read pointer for unaligned buffers common/cmd_sf.c | 3 ++- drivers/mtd/spi/sf.c | 2 +- drivers/mtd/spi/sf_internal.h | 8 ++++---- drivers/mtd/spi/sf_ops.c | 40 ++++++++++++++++++++++------------------ drivers/mtd/spi/sf_probe.c | 8 +++++--- drivers/spi/altera_spi.c | 2 +- drivers/spi/bfin_spi.c | 2 +- drivers/spi/mxc_spi.c | 2 +- drivers/spi/oc_tiny_spi.c | 2 +- drivers/spi/xilinx_spi.c | 2 +- drivers/spi/xilinx_spi.h | 2 +- include/spi.h | 14 +++++++------- 12 files changed, 47 insertions(+), 40 deletions(-)

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[U-Boot] pxe incompatibility with x86
by Ian Campbell 15 Oct '13

15 Oct '13

Hi, I've noticed what appears to be an incompatibility between u-boot's pxe support and the x86 pxelinux stuff. I'm running on a Calxeda midway but AFAICT this not specific to the platform. It seems that Rob and Jason are both involved in u-boot pxe support as well as being from Calxeda so I guess I don't have to be too sure either way ;-) syslinux/README says: Note that all filename references are relative to the directory pxelinux.0 lives in. And u-boots emulation of pxelinux's behaviour seems to implement this for loading pxelinux.cfg but not for loading any files referenced by the config. This seems to have been related to https://bugs.launchpad.net/ubuntu/+source/u-boot-linaro/+bug/927781 The Xen.org osstest infrastructure has in dhcpd.conf: filename "pxe/syslinux.0" and runs a tftp server exporting /tftpboot with all the files in /tftpboot/pxe. This leads to: TFTP from server 10.80.248.135; our IP address is 10.80.229.106; sending through gateway 10.80.224.1 Filename 'pxe/syslinux.0'. Load address: 0x800000 Loading: ## done Bytes transferred = 26793 (68a9 hex) [...] TFTP from server 10.80.248.135; our IP address is 10.80.229.106; sending through gateway 10.80.224.1 Filename 'pxe/pxelinux.cfg/01-fc-2f-40-11-72-5c'. Load address: 0x700000 Loading: # done Bytes transferred = 513 (201 hex) Config file found However the config file contains: serial 0 115200 timeout 5 label overwrite menu label ^Overwrite menu default kernel /ianc/osstest/debian-installer/armhf/2013-09-23-wheezy/linux.armmp [...] append [...] initrd=/ianc/osstest/tmp/marilith-n4--initrd.gz [...] leading to: Retrieving file: /ianc/osstest/tmp/marilith-n4--initrd.gz Using xgmac0 device TFTP from server 10.80.248.135; our IP address is 10.80.229.106; sending through gateway 10.80.224.1 Filename '/ianc/osstest/tmp/marilith-n4--initrd.gz'. Load address: 0x4000000 Loading: * TFTP error: 'File not found' (1) The actual path to the initrd is /tftpboot/pxe/ianc/osstest/... IOW the /pxe prefix has been dropped. I think this differs from how real pxelinux on x86 behaves, at least judging from the osstest setup... Cheers, Ian.

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[U-Boot] [PATCH] Tegra114: spl: Set system clock to clk_m
by Tom Warren 15 Oct '13

15 Oct '13

From: Jimmy Zhang <jimmzhang(a)nvidia.com> Based on Tegra114 TRM, system clock can run up to 275MHz. On power on, the default sytem clock source is set to pllp_out0. In function clock_early_init(), pllp_out0 will be set to 480MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP. Tested on A02 dalmore board. Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> --- arch/arm/cpu/arm720t/tegra-common/spl.c | 7 ++++++ arch/arm/cpu/arm720t/tegra114/cpu.c | 35 +++++++++++++++++--------- arch/arm/cpu/tegra114-common/clock.c | 13 ++++++++++ arch/arm/include/asm/arch-tegra/clk_rst.h | 41 ++++++++++++++++++------------- 4 files changed, 68 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 5171a8f..8bb50b7 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -17,6 +17,10 @@ #include <asm/arch/spl.h> #include "cpu.h" +__weak void set_avp_clock_to_clkm(void) +{ +} + void spl_board_init(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; @@ -24,6 +28,9 @@ void spl_board_init(void) /* enable JTAG */ writel(0xC0, &pmt->pmt_cfg_ctl); + /* use clk_m as avp clock source */ + set_avp_clock_to_clkm(); + board_init_uart_f(); /* Initialize periph GPIOs */ diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index 51ecff7..844299b 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -127,8 +127,8 @@ void t114_init_clocks(void) clrbits_le32(&flow->cluster_control, 1); /* - * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run - * at 108 MHz. This is glitch free as only the source is changed, no + * Switch system clock to PLLP_OUT4 (204 MHz), AVP will now run + * at 204 MHz. This is glitch free as only the source is changed, no * special precaution needed. */ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | @@ -152,18 +152,11 @@ void t114_init_clocks(void) clock_set_enable(PERIPH_ID_CACHE2, 1); clock_set_enable(PERIPH_ID_GPIO, 1); clock_set_enable(PERIPH_ID_TMR, 1); - clock_set_enable(PERIPH_ID_RTC, 1); clock_set_enable(PERIPH_ID_CPU, 1); clock_set_enable(PERIPH_ID_EMC, 1); clock_set_enable(PERIPH_ID_I2C5, 1); - clock_set_enable(PERIPH_ID_FUSE, 1); - clock_set_enable(PERIPH_ID_PMC, 1); clock_set_enable(PERIPH_ID_APBDMA, 1); clock_set_enable(PERIPH_ID_MEM, 1); - clock_set_enable(PERIPH_ID_IRAMA, 1); - clock_set_enable(PERIPH_ID_IRAMB, 1); - clock_set_enable(PERIPH_ID_IRAMC, 1); - clock_set_enable(PERIPH_ID_IRAMD, 1); clock_set_enable(PERIPH_ID_CORESIGHT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_EMC1, 1); @@ -192,7 +185,6 @@ void t114_init_clocks(void) reset_set_enable(PERIPH_ID_COP, 0); reset_set_enable(PERIPH_ID_EMC, 0); reset_set_enable(PERIPH_ID_I2C5, 0); - reset_set_enable(PERIPH_ID_FUSE, 0); reset_set_enable(PERIPH_ID_APBDMA, 0); reset_set_enable(PERIPH_ID_MEM, 0); reset_set_enable(PERIPH_ID_CORESIGHT, 0); @@ -220,7 +212,7 @@ static int is_clamp_enabled(u32 mask) u32 reg; /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */ - reg = readl(&pmc->pmc_pwrgate_timer_on); + reg = readl(&pmc->pmc_clamp_status); return (reg & mask) == mask; } @@ -322,3 +314,24 @@ void start_cpu(u32 reset_vector) /* If the CPU(s) don't already have power, power 'em up */ powerup_cpus(); } + +/* + * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 + * with frequency set at 1MHz. Before initializing PLLP, we need to move the + * system clock's source to CLK_M temporarily. And then switch it to PLLP_out4 + * (204MHz) at a later time. + */ +void set_avp_clock_to_clkm(void) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 val; + + val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clkrst->crc_sclk_brst_pol); + udelay(3); +} diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 9bb6529..0626bcd 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -697,6 +697,7 @@ void clock_early_init(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; /* * PLLP output frequency set to 408Mhz @@ -741,6 +742,18 @@ void clock_early_init(void) /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */ writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); + + /* Set PLLP_OUT3 and 4 freqs to 102MHz and 204MHz */ + /* Assert RSTN before enable */ + reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); + + /* set divisor and reenable */ + reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) + | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) + | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; + writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); } void arch_timer_init(void) diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 5f52d60..7045266 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -209,6 +209,13 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; +#define PLLP_OUT3_RSTN_DIS (1 << 0) +#define PLLP_OUT3_RSTN_EN (0 << 0) +#define PLLP_OUT3_CLKEN (1 << 1) +#define PLLP_OUT4_RSTN_DIS (1 << 16) +#define PLLP_OUT4_RSTN_EN (0 << 16) +#define PLLP_OUT4_CLKEN (1 << 17) + /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ #define PLLU_POWERDOWN (1 << 16) #define PLL_ENABLE_POWERDOWN (1 << 14) -- 1.8.1.5

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