October 2013 - U-Boot

[U-Boot] [PATCH 1/2][v2]powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs
by Ramneek Mehresh 17 Oct '13

17 Oct '13

CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for initializing all USB controllers on a given platform. This macro is defined for all 85xx socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> --- Changes for v2: rebased on u-boot-mpc85xx-next arch/powerpc/cpu/mpc8xxx/fdt.c | 6 ++++-- arch/powerpc/include/asm/config_mpc85xx.h | 26 +++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index eb7cbbc..ceab92f 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -15,7 +15,9 @@ #include <phy.h> #include <hwconfig.h> -#define FSL_MAX_NUM_USB_CTRLS 2 +#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -128,7 +130,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) char str[5]; int i, j; - for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) { + for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { int mode_idx = -1, phy_idx = -1; snprintf(str, 5, "%s%d", "usb", i); if (hwconfig(str)) { diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 946ea97..4cc12ee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -133,6 +133,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -153,6 +154,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -162,6 +164,7 @@ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -178,6 +181,7 @@ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -196,6 +200,7 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 @@ -210,6 +215,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -228,6 +234,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 @@ -243,6 +250,7 @@ #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 @@ -250,6 +258,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -263,6 +272,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -280,6 +290,7 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -289,6 +300,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -307,6 +319,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 @@ -326,7 +339,7 @@ #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #define CONFIG_SYS_FSL_ERRATUM_A005125 - +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -338,6 +351,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -381,6 +395,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 @@ -413,6 +428,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" @@ -460,6 +476,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -495,6 +512,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" @@ -519,6 +537,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 @@ -535,6 +554,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 @@ -581,6 +601,7 @@ #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -615,6 +636,7 @@ #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 @@ -637,6 +659,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -671,6 +694,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -- 1.7.11.7

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[U-Boot] [PATCH v7 0/5] mtd: nand: omap: optimize and clean-up of OMAP NAND driver
by Pekon Gupta 17 Oct '13

17 Oct '13

*changes in v7* [PATCH 1/5] - omap_gpmc.c: fix: free bytes in OOB (ecclayout->oobfree[0].length) - omap_gpmc.c: cleanup: redundant code added in previous patch versions - am335x_evm.h: cleanup: redundant code added in previous patch versions - tricorder.h: fix: CONFIG_NAND_OMAP_ECCSCHEME [PATCH 2/5] removed: re-configuration of gpmc.config1[dev_width] added in previous version of patch [PATCH 3/5] <no update> [PATCH 4/5] <no update> [PATCH 5/5] minor fix: missing '$' in ${loadaddr} *changes in v6* [PATCH 1/5] incorporated feedbacks from Scott Wood <scottwood(a)freescale.com> - renamed CONFIG_SYS_NAND_ECCSCHEME to CONFIG_NAND_OMAP_ECCSCHEME - updated omap_select_ecc_scheme() to handle error conditions without depending on caller. - renamed OMAP_ECC_HAM1_CODE_HW_ROMCODE to OMAP_ECC_HAM1_CODE_HW to keep it naming compatible to linux kernel - updated doc/README.nand and doc/README.omap3 [PATCH 2/5] minor code clean-up [PATCH 3/5] minor code clean-up [PATCH 4/5] <no update> [PATCH 5/5] <moved CONFIG_NAND_OMAP_ECCSCHEME description to README.nand> *changes in v5* This version of patch is tested on am335x-evm with x8 NAND device, and boots SPL and u-boot from NAND [PATCH 1/5] - re-added omap_read_page_bch(): needed proper sequence of while reading DATA and ECC from NAND page, so that calc_ecc generated from GPMC is understood by ELM. - added check to see if NAND OOB can accomodate ECC for entire page [PATCH 2/5] fixed device-width in GPMC_CONFIG1_X to support x16 devices [PATCH 3/5] code clean-up for OMAP_ECC_BCH8_CODE_HW_DETECTION_SW mode [PATCH 4/5] - fixed omap_correct_data_bch() for correcting bit-flips using ELM - code-cleanup + added omap_reverse_list() [PATCH 5/5] incorporated feedbacks from Peter Korsgaard <jacmet(a)sunsite.dk> *changes in v4* [PATCH 1/5] - removed omap_read_page_bch(): chip->ecc.read_page uses default API nand_read_page_hwecc() in nand_base.c - updated tricorder.h: added new CONFIGS for ECCSCHEME & ONFI_DETECTION - converted printf("ECC-SCHEME") to debug("ECC-SCHEME") [PATCH 2/5] minor code clean-up [PATCH 3/5] <no update> [PATCH 4/5] <no update> [PATCH 5/5] updated README as per feedbacks from trini(a)ti.com *changes in v3* [PATCH 1/5] (complete change) - ecc-scheme is selection is controller by s/w, not CONFIG_NAND_xx - added omap_select_ecc_scheme(), as common function to handle all ecc-scheme related configurations for both board_nand_init() & omap_nand_switch_ecc(). - removed un-used defines from asm/arch-am33xx/omap_gpmc.h - updated doc/REAME.nand [PATCH 2/5] removed un-used defines from asm/omap_gpmc.h [PATCH 3/5] removed omap_calculate_ecc_bch_sw() and omap_calculate_ecc() and merged their logic into omap_calculate_ecc_bch() [PATCH 4/5] updated return error-code in-case of invalid conditions [PATCH 5/5] (new) for board/ti/am335x/README *changes in v2* - added documentation for CONFIG_NAND_OMAP_xx in doc/README.nand - added CONFIG_BCH along with CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW to include software library lib/bch.c - fixed board_nand_init() and omap_enable_hwecc() *original v1* This patch series updates BCH8_ECC schemes in mtd/nand/omap_gpmc.c driver - adds scalability for higher ECC schemes in future. - removes CONFIG_AM335x and it makes it generic for all platforms. - optimizes read_data paths Pekon Gupta (5): [PATCH 1/5] mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform [PATCH 2/5] mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes [PATCH 3/5] mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes [PATCH 4/5] mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes [PATCH 5/5] board/ti/am335x/README: update for NAND boot arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 52 +- arch/arm/include/asm/omap_gpmc.h | 7 - board/ti/am335x/README | 53 +- doc/README.nand | 30 + doc/README.omap3 | 4 +- drivers/mtd/nand/omap_gpmc.c | 822 +++++++++++---------------- include/configs/am335x_evm.h | 11 +- include/configs/tricorder.h | 3 +- 8 files changed, 416 insertions(+), 566 deletions(-) -- 1.8.1

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[U-Boot] [PATCH 0/2]powerpc/usb:Intergrate multiple USB controller support
by Ramneek Mehresh 17 Oct '13

17 Oct '13

Make multiple USB controllers work inside u-boot by doing the following: - Defining max. no of USB controllers for each soc - Defining proper base address for each controller so that initialization code can work for each of them Ramneek Mehresh (2): powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs powerpc/usb:Differentiate USB controller base address arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xxx/fdt.c | 6 ++++-- arch/powerpc/include/asm/config_mpc85xx.h | 24 ++++++++++++++++++++++++ arch/powerpc/include/asm/immap_512x.h | 6 +++--- arch/powerpc/include/asm/immap_83xx.h | 18 ++++++++++++------ arch/powerpc/include/asm/immap_85xx.h | 9 +++++---- drivers/usb/host/ehci-fsl.c | 15 +++++++++++++-- drivers/usb/host/ehci-mpc512x.c | 4 ++-- include/usb/ehci-fsl.h | 13 ++++++++++--- 9 files changed, 74 insertions(+), 23 deletions(-) -- 1.7.11.7

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[U-Boot] [PATCH] powerpc/c29xpcie: add DDR ECC on off config setting
by Po Liu 17 Oct '13

17 Oct '13

c29xpcie REV_A board DDR ECC chip has bad impedance in hardware, force that kind of board to be DDR ECC off when booting. Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on in uboot enviroment. Signed-off-by: Po Liu <Po.Liu(a)freescale.com> --- Add this patch after the camelcase patch http://patchwork.ozlabs.org/patch/271670/ was added. board/freescale/c29xpcie/ddr.c | 8 ++++++++ include/configs/C29XPCIE.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index b017cfd..4077ed9 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -9,6 +9,9 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> +#include "cpld.h" + +#define C29XPCIE_HARDWARE_REVA 0x40 /* * Micron MT41J128M16HA-15E * */ @@ -61,7 +64,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); int i; + popts->clk_adjust = 2; popts->cpo_override = 0x1f; popts->write_data_delay = 4; @@ -79,6 +84,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->trwt_override = 1; popts->trwt = 0; + if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) + popts->ecc_mode = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 83779ef..877375d 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -432,7 +432,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ + "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "loadaddr=1000000\0" \ -- 1.8.0 camelcase patch

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[U-Boot] [ANN] U-Boot v2013.10 released
by Tom Rini 17 Oct '13

17 Oct '13

Hey all, I've pushed v2013.10 out to the repository and tarballs should exist soon. Once again, lots of nice little things around the tree have been done, your favorite platform is probably gotten a nice tweak or two and we've now got things like QSPI support in for a few platforms and controllers. The big, diffstat wise at least, change is that now instead of large boilerplate messages in every file about the license we use SPDX tags in all files to identify what license(s) apply here. And the source code itself got trimmed down a good bit. Thanks Wolfgang! I'm pushing the merge window for 2014.01 out a week to Nov 07 to make up for getting this out a little late. We'll still aim to release v2014.01 on Jan 13. Thanks all! -- Tom

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[U-Boot] [PATCH 1/2] ARM: tegra: support SKU b1 of Tegra30
by Alban Bedel 17 Oct '13

17 Oct '13

Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel(a)avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel(a)avionic-design.de> --- arch/arm/cpu/tegra-common/ap.c | 1 + arch/arm/include/asm/arch-tegra/tegra.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c index 6fb11cb..9e4085c 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/cpu/tegra-common/ap.c @@ -71,6 +71,7 @@ int tegra_get_chip_sku(void) switch (sku_id) { case SKU_ID_T33: case SKU_ID_T30: + case SKU_ID_T30MQS: return TEGRA_SOC_T30; } break; diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 25d1fc4..6b6ce85 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -65,6 +65,7 @@ enum { SKU_ID_T25E = 0x1c, SKU_ID_T33 = 0x80, SKU_ID_T30 = 0x81, /* Cardhu value */ + SKU_ID_T30MQS = 0xb1, SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */ SKU_ID_T114_1 = 0x01, }; -- 1.8.4

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[U-Boot] [PATCH 1/3] fpga: zynqpl: Add dcache flush support
by Michal Simek 17 Oct '13

17 Oct '13

From: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-teki(a)xilinx.com> Buffers must be cache and dma aligned. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/fpga/zynqpl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 717c039..f2f49b5 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -177,8 +177,8 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if ((u32)buf_start & 0x3) { - u32 *new_buf = (u32 *)((u32)buf & ~0x3); + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); @@ -284,6 +284,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); + /* flush(clean & invalidate) d-cache range buf */ + flush_dcache_range((u32)buf, (u32)buf + + roundup(bsize, ARCH_DMA_MINALIGN)); + /* Set up the transfer */ writel((u32)buf | 1, &devcfg_base->dma_src_addr); writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); -- 1.8.2.3

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[U-Boot] Replace Redboot with U-boot
by Romain Crausaz 17 Oct '13

17 Oct '13

Dear, I found this message on the list : lists.denx.de/pipermail/u-boot/2012-March/120801.html I m able to start u-boot from Redboot but I don't know how to download the u-boot-nand.bin from my tftp with u-boot and then copy it to the flash to erase redboot. I m also using the KA-RO TX25 board. I have some ideas about how to do it but I m not sure and I don't have any J-TAG board in case something go wrong. Thanks Best Regards Crausaz Romain

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[U-Boot] [PATCH] zynq: Use arch_cpu_init() instead of lowlevel_init()
by Michal Simek 17 Oct '13

17 Oct '13

Zynq lowlevel_init() was implemented in C but stack pointer is setup after function call in _main(). Move architecture setup to arch_cpu_init() which is call as the first function in board_init_f() which already have correct stack pointer. Reported-by: Sven Schwermer <sven.schwermer(a)tuhh.de> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- I can't see any problem to call zynq setup a little bit later. There is already expectation that u-boot runs from DDR. Moving lowlevel_init from C to ASM is possible but I will have to introduce new macros with hardcoded values. Using structures is much nicer. --- arch/arm/cpu/armv7/zynq/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 4367d1a..8846f30 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -11,6 +11,10 @@ void lowlevel_init(void) { +} + +int arch_cpu_init(void) +{ zynq_slcr_unlock(); /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); @@ -31,6 +35,8 @@ void lowlevel_init(void) writel(0xC, &slcr_base->ddr_urgent); zynq_slcr_lock(); + + return 0; } void reset_cpu(ulong addr) -- 1.8.2.3

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[U-Boot] [PATCH v2 00/10] arm: vf610/vf610twr: vybrid tower fixes and enhancements
by Marcel Ziswiler 17 Oct '13

17 Oct '13

This patch series addresses several fixes and enhancements for the vybrid tower. Tested on a TWR-VF65GS10 Rev G. Changes v2: - Memory offset based reserved ANADIG field naming scheme. - Fixed mux_ctrl_ofs in secondary RMII1 iomux definitions. Marcel Ziswiler (10): arm: vf610: fix anadig register struct arm: vf610: clean-up anadig register struct arm: vf610: add uart0 clock definition arm: vf610: add anadig pll5 definitions arm: vf610: add enet1 base address definition arm: vf610: add rmii clkout iomux definition arm: vf610: add uart0 tx/rx iomux definitions arm: vf610: add rmii1 iomux definitions arm: vf610: fix double iomux configuration for vf610twr board arm: vf610: remove obsolete uart port configuration arch/arm/include/asm/arch-vf610/crm_regs.h | 57 ++++++++++++++----------- arch/arm/include/asm/arch-vf610/imx-regs.h | 1 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 12 ++++++ board/freescale/vf610twr/vf610twr.c | 1 - include/configs/vf610twr.h | 1 - 5 files changed, 45 insertions(+), 27 deletions(-) -- 1.7.9.5

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