August 2009 - U-Boot

[U-Boot] [PATCH] fsl: simplify the "mac id" command, improve boot-time informational message
by Timur Tabi 27 Aug '09

27 Aug '09

The "mac id" command took a 4-character parameter as the identifier string. However, for any given board, only one kind of identifier is acceptable, so it makes no sense to ask the user to type it in. Instead, if the user enters "mac id", the identifier (and also the version, if it's NXID) will automatically be set to the correct value. Improve the message that is displayed when EEPROM is read during boot. It now displays "EEPROM:" and then either an error message or the EEPROM identifier if successful. If the identifier in EEPROM is valid, then always reject a bad CRC, even if the CRC field has not been initialized. Don't force the MAC address count to MAX_NUM_PORTS or less. Forcing the value to be changed resulting in an in-memory copy that does not match what's in hardware, even though the user did not request that change. Finally, always update the CRC value in the in-memory copy after any field is changed, so that the CRC is always correct. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/common/sys_eeprom.c | 79 +++++++++++++++++++++-------------- lib_ppc/board.c | 1 + 2 files changed, 48 insertions(+), 32 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3e1e332..f11b249 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -186,12 +186,25 @@ static int read_eeprom(void) } /** + * update_crc - update the CRC + * + * This function should be called after each update to the EEPROM structure, + * to make sure the CRC is always correct. + */ +static void update_crc(void) +{ + u32 crc; + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + e.crc = cpu_to_be32(crc); +} + +/** * prog_eeprom - write the EEPROM from memory */ static int prog_eeprom(void) { - int ret, i, length; - unsigned int crc; + int ret, i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus; @@ -204,19 +217,16 @@ static int prog_eeprom(void) #else memset(e.res_0, 0xFF, sizeof(e.res_0)); #endif - - length = sizeof(e); - crc = crc32(0, (void *)&e, length - 4); - e.crc = cpu_to_be32(crc); + update_crc(); #ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif - for (i = 0, p = &e; i < length; i += 8, p += 8) { + for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min((length - i), 8)); + p, min((sizeof(e) - i), 8)); if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -273,6 +283,8 @@ static void set_date(const char *string) for (i = 0; i < 6; i++) e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); + + update_crc(); } /** @@ -297,11 +309,12 @@ static void set_mac_address(unsigned int index, const char *string) if (*p == ':') p++; } + + update_crc(); } int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - int i; char cmd; if (argc == 1) { @@ -316,9 +329,13 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } - if ((cmd == 'i') && (argc > 2)) { - for (i = 0; i < 4; i++) - e.id[i] = argv[2][i]; + if (cmd == 'i') { +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + memcpy(e.id, "NXID", sizeof(e.id)); + e.version = 0; +#else + memcpy(e.id, "CCID", sizeof(e.id)); +#endif return 0; } @@ -346,6 +363,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 'n': /* serial number */ memset(e.sn, 0, sizeof(e.sn)); strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); + update_crc(); break; case 'e': /* errata */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID @@ -355,12 +373,14 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) e.errata[0] = argv[2][0]; e.errata[1] = argv[2][1]; #endif + update_crc(); break; case 'd': /* date BCD format YYMMDDhhmmss */ set_date(argv[2]); break; case 'p': /* MAC table size */ e.mac_count = simple_strtoul(argv[2], NULL, 16); + update_crc(); break; case '0' ... '7': /* "mac 0" through "mac 7" */ set_mac_address(cmd - '0', argv[2]); @@ -388,6 +408,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int mac_read_from_eeprom(void) { unsigned int i; + u32 crc; if (read_eeprom()) { printf("Read failed.\n"); @@ -395,31 +416,18 @@ int mac_read_from_eeprom(void) } if (!is_valid) { - printf("Invalid ID (%02x %02x %02x %02x)\n", e.id[0], e.id[1], e.id[2], e.id[3]); + printf("Invalid ID (%02x %02x %02x %02x)\n", + e.id[0], e.id[1], e.id[2], e.id[3]); return -1; } - if (be32_to_cpu(e.crc) != 0xFFFFFFFF) { - u32 crc = crc32(0, (void *)&e, sizeof(e) - 4); - - if (crc != be32_to_cpu(e.crc)) { - printf("CRC mismatch (%08x != %08x).\n", crc, - be32_to_cpu(e.crc)); - return -1; - } - } - - /* Check the number of MAC addresses which is limited to - * MAX_NUM_PORTS. - */ - if (e.mac_count > MAX_NUM_PORTS) { - printf("Warning: The number of MAC addresses is greater" - " than %u, force it to %u.\n", MAX_NUM_PORTS, - MAX_NUM_PORTS); - e.mac_count = MAX_NUM_PORTS; + crc = crc32(0, (void *)&e, sizeof(e) - 4); + if (crc != be32_to_cpu(e.crc)) { + printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); + return -1; } - for (i = 0; i < e.mac_count; i++) { + for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { char ethaddr[18]; @@ -441,6 +449,13 @@ int mac_read_from_eeprom(void) } } +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], + be32_to_cpu(e.version)); +#else + printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); +#endif + return 0; } diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 6dd4d56..59a56d5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -889,6 +889,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET) + puts("EEPROM: "); mac_read_from_eeprom(); #endif -- 1.6.0.6

2 2

[U-Boot] [PATCH v5] use common code for Matrix Vision boards
by Andre Schwarz 27 Aug '09

27 Aug '09

clean up existing boards (mvBC-P/MPC5200 and mvBL-M7/MPC8343) by using common code. MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

3 5

[U-Boot] U-BOOT quiet build
by Michal Simek 27 Aug '09

27 Aug '09

Hi All, how to do quiet U-BOOT build? Mike: I think I saw in past any command which do it. Am I right? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian

3 7

[U-Boot] U-boot Version 2009.06
by ragh1981＠gmail.com 27 Aug '09

27 Aug '09

Hello Friends, I have a custom board with MPC8548E. I am trying to port u-boot 2009.06 By modifying the MPC8548CDS Files. The main difference between CDS and our custom board is in Flash Configuration. Our custom board has 128MB Flash? Which locations/file i have to change? i configured the MPC8548CDS.h file (Flash location) but when i program and run, the u-boot is getting struck at 0xfff80e00 location? (this is checked using "ti" command in BDI). What could be the problem? How can this be debugged? -- View this message in context: http://www.nabble.com/U-boot-Version-2009.06-tp24860826p24860826.html Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot] ARM926ej, trying to serve interrupt
by Ricardo Martínez 27 Aug '09

27 Aug '09

Hi, I'm trying to printf something when one timer generates an interrupt. u-boot version is 1.3.4. The steps I've followed: - #define CONFIG_USE_IRQ - I've enabled interrupts - I've enabled timer interrupt - I've enabled timer - I've checked interrupt masks - I've checked interrupt status flags prior to timer interrupt The problem is that when timer generates interrupt (reaches 0 after several cycles), I expect default u-boot code "do_irq", called from ".irq:" address defined in "start.S" get executed. In that function is where I want to printf anything to check it is working. But the whole system hangs. When timer generates the interrupt, ARM9 hangs without printing anything and normal execution is freezed. printf and serial driver work perfectly because I've checked the steps above with prinft debugguing. I bet that when timer interrupts CPU, it jumps to code section not defined. The question is... How can I program the expected behaviour? I mean executing "do_irq" when the interrupt is generated. Thanks in advance for your help. Best regards, Ricardo Martinez

2 2

[U-Boot] [PATCH v4] use common code for Matrix Vision boards
by André Schwarz 27 Aug '09

27 Aug '09

clean up existing boards (mvBC-P/MPC5200 and mvBL-M7/MPC8343) by using common code. Signed-off-by: André Schwarz <andre.schwarz(a)matrix-vision.de> --- Wolfgang, this is my current diff against your latest master repository - I'm unable to split it anymore. Unfortunately the e1000 is currently not working on the mvBC-P but this is due to changes in drivers/net/e1000.c ... using the last released version is working fine. Will contact the maintainer to fix it. Hopefully you'll nevertheless apply this patch so that everybody using the boards can get up-to-date again. Regards, André board/matrix_vision/mvbc_p/mvbc_p.c | 97 +++++--------------------- board/matrix_vision/mvbc_p/mvbc_p.h | 2 +- board/matrix_vision/mvbc_p/mvbc_p_autoscript | 10 ++- board/matrix_vision/mvblm7/mvblm7.c | 54 ++++++-------- board/matrix_vision/mvblm7/mvblm7.h | 3 +- board/matrix_vision/mvblm7/pci.c | 35 ++-------- include/configs/MVBC_P.h | 2 +- include/configs/MVBLM7.h | 49 +++++-------- 8 files changed, 77 insertions(+), 175 deletions(-) diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c index a300342..0cbe900 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ b/board/matrix_vision/mvbc_p/mvbc_p.c @@ -39,6 +39,7 @@ #include <asm/io.h> #include "fpga.h" #include "mvbc_p.h" +#include "../common/mv_common.h" #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 @@ -134,23 +135,6 @@ void mvbc_init_gpio(void) printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe); } -void reset_environment(void) -{ - char *s, sernr[64]; - - printf("\n*** RESET ENVIRONMENT ***\n"); - memset(sernr, 0, sizeof(sernr)); - s = getenv("serial#"); - if (s) { - printf("found serial# : %s\n", s); - strncpy(sernr, s, 64); - } - gd->env_valid = 0; - env_relocate(); - if (s) - setenv("serial#", sernr); -} - int misc_init_r(void) { char *s = getenv("reset_env"); @@ -166,7 +150,7 @@ int misc_init_r(void) return 0; } printf(" === FACTORY RESET ===\n"); - reset_environment(); + mv_reset_environment(); saveenv(); return -1; @@ -206,19 +190,28 @@ void flash_afterinit(ulong size) void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char line = 0xff; + char *s = getenv("pci_latency"); u32 base; + u8 val = 0; + + if (s) + val = simple_strtoul(s, NULL, 16); if (PCI_BUS(dev) == 0) { switch (PCI_DEV (dev)) { case 0xa: /* FPGA */ line = 3; pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base); - printf("found FPA - enable arbitration\n"); + printf("found FPGA - enable arbitration\n"); writel(0x03, (u32*)(base + 0x80c0)); writel(0xf0, (u32*)(base + 0x8080)); + if (val) + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); break; case 0xb: /* LAN */ line = 2; + if (val) + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val); break; case 0x1a: break; @@ -234,85 +227,31 @@ struct pci_controller hose = { fixup_irq:pci_mvbc_fixup_irq }; -int mvbc_p_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - extern void pci_mpc5xxx_init(struct pci_controller *); void pci_init_board(void) { - char *s; - int load_fpga = 1; - mvbc_p_init_fpga(); - s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - if (load_fpga) { - printf("loading FPGA ... "); - mvbc_p_load_fpga(); - printf("done\n"); - } + mv_load_fpga(); pci_mpc5xxx_init(&hose); } -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - - return e; -} - -u8 *dhcp_vendorex_proc (u8 *popt) -{ - return NULL; -} - void show_boot_progress(int val) { struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; switch(val) { case 0: /* FPGA ok */ - setbits_be32(&gpio->simple_dvo, 0x80); + setbits_be32(&gpio->simple_dvo, LED_G0); break; - case 1: - setbits_be32(&gpio->simple_dvo, 0x40); + case 65: + setbits_be32(&gpio->simple_dvo, LED_G1); break; case 12: - setbits_be32(&gpio->simple_dvo, 0x20); + setbits_be32(&gpio->simple_dvo, LED_Y); break; case 15: - setbits_be32(&gpio->simple_dvo, 0x10); + setbits_be32(&gpio->simple_dvo, LED_R); break; default: break; diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h index 3330798..be1542b 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p.h +++ b/board/matrix_vision/mvbc_p/mvbc_p.h @@ -23,7 +23,7 @@ #define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \ FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI) #define SIMPLE_DVO (FPGA_CONFIG) -#define SIMPLE_ODE (FPGA_CONFIG) +#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R) #define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \ FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\ WD_WDI | COP_PRESENT) diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript index 5cee6c5..1102354 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript +++ b/board/matrix_vision/mvbc_p/mvbc_p_autoscript @@ -5,7 +5,7 @@ setenv bootdtb bootm \${kernel_boot} \ ${mv_initrd_addr_ram} \${mv_dtb_addr_ram} setenv ramkernel setenv kernel_boot \${loadaddr} setenv flashkernel setenv kernel_boot \${mv_kernel_addr} setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \ ${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam addcons e1000para bootdtb +setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup @@ -16,12 +16,16 @@ setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baud else setenv addcons setenv bootargs \${bootargs} console=tty0 fi -setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=1500 e1000.SmartPowerDownEnable=1 +setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1 setenv set_static_ip setenv ipaddr \${static_ipaddr} setenv set_static_nm setenv netmask \${static_netmask} setenv set_static_gw setenv gatewayip \${static_gateway} setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs +if test ${oprofile} = yes; +then +setenv addprofile setenv bootargs \${bootargs} profile=\${profile} +fi if test ${autoscr_boot} != no; then if test ${netboot} = yes; @@ -31,7 +35,7 @@ then then echo "=== bootp succeeded -> netboot ===" run set_ip - run getdtb rundtb bootfromnet ramparam addcons e1000para bootdtb + run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb else echo "=== netboot failed ===" fi diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c index 8fe5b4b..b58c1b9 100644 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ b/board/matrix_vision/mvblm7/mvblm7.c @@ -42,8 +42,15 @@ int fixed_sdram(void) u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; + char *s = getenv("ddr_size"); msize = CONFIG_SYS_DDR_SIZE; + if (s) { + u32 env_ddr_size = simple_strtoul(s, NULL, 10); + if (env_ddr_size == 512) + msize = 512; + } + for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { @@ -63,14 +70,19 @@ int fixed_sdram(void) im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(300); + asm("sync;isync"); + udelay(600); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return CONFIG_SYS_DDR_SIZE; + asm("sync;isync"); + udelay(500); + + return msize; } phys_size_t initdram(int board_type) @@ -88,40 +100,22 @@ phys_size_t initdram(int board_type) return msize * 1024 * 1024; } -int checkboard(void) +int misc_init_r(void) { - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} + char *s = getenv("reset_env"); -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - ptr = getenv("dhcp_vendor-class-identifier"); - if (ptr) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - ptr = getenv("dhcp_client_id"); - if (ptr) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; + if (s) { + mv_reset_environment(); } - return e; + return 0; } -u8 *dhcp_vendorex_proc(u8 *popt) +int checkboard(void) { - return NULL; + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; } #ifdef CONFIG_HARD_SPI diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h index 03e9f41..de9fec7 100644 --- a/board/matrix_vision/mvblm7/mvblm7.h +++ b/board/matrix_vision/mvblm7/mvblm7.h @@ -8,14 +8,13 @@ #define FPGA_DIN 0x20000000 #define FPGA_STATUS 0x10000000 #define FPGA_CONF_DONE 0x08000000 -#define MMC_CS 0x04000000 #define WD_WDI 0x00400000 #define WD_TS 0x00200000 #define MAN_RST 0x00100000 #define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI| MMC_CS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|MVBLM7_MMC_CS) #define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) #endif diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index 4b74e6d..1cc524b 100644 --- a/board/matrix_vision/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c @@ -32,24 +32,10 @@ #include <fpga.h> #include "mvblm7.h" #include "fpga.h" +#include "../common/mv_common.h" DECLARE_GLOBAL_DATA_PTR; -int mvblm7_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -73,10 +59,8 @@ static struct pci_region pci_regions[] = { void pci_init_board(void) { - char *s; int i; int warmboot; - int load_fpga; volatile immap_t *immr; volatile pcictrl83xx_t *pci_ctrl; volatile gpio83xx_t *gpio; @@ -84,32 +68,23 @@ void pci_init_board(void) volatile law83xx_t *pci_law; struct pci_region *reg[] = { pci_regions }; - load_fpga = 1; immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) &immr->clk; pci_ctrl = immr->pci_ctrl; pci_law = immr->sysconf.pcilaw; gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - gpio->dat = MV_GPIO_DAT; gpio->odr = MV_GPIO_ODE; - if (load_fpga) - gpio->dir = MV_GPIO_OUT; - else - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + gpio->dir = MV_GPIO_OUT; printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, immr->sysconf.sicrl); mvblm7_init_fpga(); - if (load_fpga) - mvblm7_load_fpga(); + mv_load_fpga(); + + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ clk->occr = 0xc0000000; diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 867e8e0..0c228cb 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -67,7 +67,7 @@ #define MV_CI mvBlueCOUGAR-P #define MV_VCI mvBlueCOUGAR-P #define MV_FPGA_DATA 0xff860000 -#define MV_FPGA_SIZE 0x0003c886 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xffd00000 #define MV_INITRD_ADDR 0xff900000 #define MV_INITRD_LENGTH 0x00400000 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index aa91805..80334bd 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -46,10 +46,9 @@ #define CONFIG_MPC8XXX_SPI #define CONFIG_HARD_SPI #define MVBLM7_MMC_CS 0x04000000 +#define CONFIG_MISC_INIT_R /* I2C */ -#undef CONFIG_SOFT_I2C - #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_OFFSET 0x3000 @@ -61,44 +60,36 @@ /* * DDR Setup */ +#undef CONFIG_SPD_EEPROM + #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 1 #define CONFIG_SYS_MEMTEST_START (60<<20) #define CONFIG_SYS_MEMTEST_END (70<<20) +#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 256 +#define CONFIG_SYS_DDRCDR 0x22000001 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -/* HC, 75Ohm, DDR-II, DRQ */ -#define CONFIG_SYS_DDRCDR 0x80000001 -/* EN, ODT_WR, 3BA, 14row, 10col */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x0 +#define CONFIG_SYS_DDR_SIZE 512 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0 -#define CONFIG_SYS_DDR_CS3_BNDS 0x0 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x2625b221 -#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 +#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* ~MEM_EN, SREN, DDR-II, 32_BE */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 +#define CONFIG_SYS_DDR_INTERVAL 0x02000100 -#define CONFIG_SYS_DDR_MODE 0x078e0232 +#define CONFIG_SYS_DDR_MODE 0x04040242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 /* Flash */ #define CONFIG_SYS_FLASH_CFI @@ -404,8 +395,8 @@ #define MV_CI mvBL-M7 #define MV_VCI mvBL-M7 -#define MV_FPGA_DATA 0xfff80000 -#define MV_FPGA_SIZE 0x00076ca2 +#define MV_FPGA_DATA 0xfff40000 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 #define MV_SOURCE_ADDR 0xff804000 @@ -452,7 +443,7 @@ "static_ipaddr=192.168.90.10\0" \ "static_netmask=255.255.255.0\0" \ "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "initrd_name=uInitrd.mvBL-M7-rfs\0" \ "zcip=no\0" \ "netboot=yes\0" \ "mvtest=Ff\0" \ MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

2 3

[U-Boot] [PATCH 1/7] eSPI: add the eSPI register support
by Mingkai Hu 27 Aug '09

27 Aug '09

Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> --- include/asm-ppc/immap_85xx.h | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 094fb9c..f3ab750 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -258,6 +258,21 @@ typedef struct ccsr_lbc { } ccsr_lbc_t; /* + * eSPI Registers(0x7000-0x8000) + */ +typedef struct ccsr_espi { + uint mode; /* 0x00 - eSPI mode register */ + uint event; /* 0x04 - eSPI event register */ + uint mask; /* 0x08 - eSPI mask register */ + uint com; /* 0x0c - eSPI command register */ + uint tx; /* 0x10 - eSPI transmit FIFO access register */ + uint rx; /* 0x14 - eSPI receive FIFO access register */ + char res1[8]; /* reserved */ + uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ + char res2[4048]; /* fill up to 0x1000 */ +} ccsr_espi_t; + +/* * PCI Registers(0x8000-0x9000) */ typedef struct ccsr_pcix { @@ -1682,6 +1697,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) -- 1.5.4

7 35

[U-Boot] [PATCH] Add some second source legacy flash chips 256x8
by Niklaus Giger 27 Aug '09

27 Aug '09

Signed-off-by: Niklaus Giger <niklaus.giger(a)member.fsf.org> --- We tested some boot flashes as possible second source. As some had ids above 0x7f, we had to implement JEDEC JEP106Z in cfi_flash.c. I now that I just missed the merge window, but the patches are not urgent and I was away for a three week drivers/mtd/cfi_flash.c | 16 +++++++++-- drivers/mtd/jedec_flash.c | 67 +++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 10 ++++++- 3 files changed, 89 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 81ac5d3..4cd0116 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -106,6 +106,8 @@ #define ATM_CMD_SOFTLOCK_START 0x80 #define ATM_CMD_LOCK_SECT 0x40 +#define FLASH_CONTINUATION_CODE 0x7F + #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -1541,13 +1543,21 @@ static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) static void cmdset_amd_read_jedec_ids(flash_info_t *info) { - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + ushort bankId = 0; + uchar manuId; + + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); + /* JEDEC JEP106Z specifies ID codes up to bank 7 */ + while(manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { + bankId += 0x100; + manuId = flash_read_uchar (info, bankId | FLASH_OFFSET_MANUFACTURER_ID); + } + info->manufacturer_id = manuId; switch (info->chipwidth){ case FLASH_CFI_8BIT: diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index e48acec..488bbec 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -68,6 +68,17 @@ #define SST39SF010A 0x00B5 #define SST39SF020A 0x00B6 +/* MXIC */ +#define MX29LV040 0x004F + +/* WINBOND */ +#define W39L040A 0x00D6 + +/* AMIC */ +#define A29L040 0x0092 + +/* EON */ +#define EN29LV040A 0x004F /* * Unlock address sets for AMD command sets. @@ -225,6 +236,62 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x10000,8), } }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = MX29LV040, + .name = "MXIC MX29LV040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = (u16)WINB_MANUFACT, + .dev_id = W39L040A, + .name = "WINBOND W39L040A", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = (u16)AMIC_MANUFACT, + .dev_id = A29L040, + .name = "AMIC A29L040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = (u16)EON_MANUFACT, + .dev_id = EN29LV040A, + .name = "EON EN29LV040A", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, #endif #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { diff --git a/include/flash.h b/include/flash.h index b016162..8feca1b 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,7 +46,7 @@ typedef struct { ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ - uchar manufacturer_id; /* manufacturer id */ + ushort manufacturer_id; /* manufacturer id */ ushort device_id; /* device id */ ushort device_id2; /* extended device id */ ushort ext_addr; /* extended query table address */ @@ -154,6 +154,7 @@ extern flash_info_t *flash_get_info(ulong base); * Device IDs */ +/* Manufacturers inside bank 0 have ids like 0x00xx00xx */ #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define ATM_MANUFACT 0x001F001F /* ATMEL */ @@ -166,6 +167,13 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ +#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ +#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 1 have ids like 0x01xx01xx */ +#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 2 have ids like 0x02xx02xx */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ -- 1.6.3.3

3 2

[U-Boot] [PATCH] Add ability for arch code to make changes before we boot
by Kumar Gala 27 Aug '09

27 Aug '09

Added a arch_preboot() function that cpu specific code can implement to allow for various modifications to the state of the machine right before we boot. This can be useful to setup register state to a specific configuration. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- common/cmd_bootm.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 86c8122..766889a 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -166,6 +166,13 @@ void __arch_lmb_reserve(struct lmb *lmb) } void arch_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__arch_lmb_reserve"))); +/* Allow for arch specific config before we boot */ +void __arch_preboot(void) +{ + /* please define platform specific arch_preboot() */ +} +void arch_preboot(void) __attribute__((weak, alias("__arch_preboot"))); + #if defined(__ARM__) #define IH_INITRD_ARCH IH_ARCH_ARM #elif defined(__avr32__) @@ -543,6 +550,7 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; case BOOTM_STATE_OS_GO: disable_interrupts(); + arch_preboot(); boot_fn(BOOTM_STATE_OS_GO, argc, argv, &images); break; } @@ -673,6 +681,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + arch_preboot(); + boot_fn(0, argc, argv, &images); show_boot_progress (-9); -- 1.6.0.6

3 10

[U-Boot] [PATCH] mpc83xx: mpc8349itx - accommodate larger kernel sizes & unzero the bootdelay
by Kim Phillips 27 Aug '09

27 Aug '09

apparently the ITX was missed last round. Also make bootdelay consistent with other boards, so as to give on the opportunity to fix mistakenly set bootcmd without having checked for an bootdelay zero setting first. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- include/configs/MPC8349ITX.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index fd5ad70..3b4e344 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -515,7 +515,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #ifdef CONFIG_MPC8349ITX #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ @@ -708,7 +708,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_FDTFILE mpc8349emitxgp.dtb #endif -#define CONFIG_BOOTDELAY 0 +#define CONFIG_BOOTDELAY 6 #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) @@ -731,7 +731,7 @@ boards, we say we have two, but don't display a message if we find only one. */ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" #define CONFIG_NFSBOOTCOMMAND \ -- 1.6.4

1 1