August 2009 - U-Boot

[U-Boot] [RESEND][PATCH 3/6]POSEIDON Board Support
by Vivek 26 Aug '09

26 Aug '09

Removed code referring Legacy NAND and did some code cleanup. Signed-off-by: Vivek Dalal <v.dalal(a)samsung.com> --- diff --git a/board/poseidon/Makefile b/board/poseidon/Makefile index e69de29..edbc696 100644 --- a/board/poseidon/Makefile +++ b/board/poseidon/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2009-2010 +# Samsung Electronics, <www.samsung.com> +# Vivek Dalal <v.dalal(a)samsung.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := poseidon.o mem.o sys_info.o +SOBJS := lowlevel_init.o load.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/poseidon/config.mk b/board/poseidon/config.mk index e69de29..f05593c 100644 --- a/board/poseidon/config.mk +++ b/board/poseidon/config.mk @@ -0,0 +1,20 @@ +# +# (C) Copyright 2009-2010 +# Samsung Electronics, <www.samsung.com> +# Vivek Dalal <v.dalal(a)samsung.com> +# +# Poseidon boad uses OMAP2430 (ARM1136) cpu +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x83e80000 + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/poseidon/load.S b/board/poseidon/load.S index e69de29..d38f66a 100644 --- a/board/poseidon/load.S +++ b/board/poseidon/load.S @@ -0,0 +1,14 @@ +.globl jumpto_addr +.globl jumpto_addr_forsave +jumpto_addr: + stmfd sp!, {r0 - r12, lr} + add lr, pc, #2 + mov pc, r0 + ldmfd sp!, {r0 - r12, pc} + +jumpto_addr_forsave: + stmfd sp!, {r0 - r12, lr} + mov r1, #0 + add lr, pc, #2 + mov pc, r0 + ldmfd sp!, {r0 - r12, pc} diff --git a/board/poseidon/lowlevel_init.S b/board/poseidon/lowlevel_init.S index e69de29..9052f71 100644 --- a/board/poseidon/lowlevel_init.S +++ b/board/poseidon/lowlevel_init.S @@ -0,0 +1,199 @@ +/* + * Board specific setup info + * + * (C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * Derived from OMAPZOOM source(board/omap2430sdp/lowlevel_init.S) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/omap24xx.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/***************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = PRCM_CLKCFG_CTRL - addr of valid reg + * R1 = CM_CLKEN_PLL - addr dpll ctlr reg + * R2 = dpll value + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + ******************************************************************************/ +.global go_to_speed + go_to_speed: + sub sp, sp, #0x4 /* get some stack space */ + str r4, [sp] /* save r4's value */ + + /* move into fast relock bypass */ + ldr r8, pll_ctl_add + mov r4, #0x2 + str r4, [r8] + ldr r4, pll_stat +block: + ldr r8, [r4] /* wait for bypass to take effect */ + and r8, r8, #0x3 + cmp r8, #0x1 + bne block + + /* set new dpll dividers _after_ in bypass */ + ldr r4, pll_div_add + ldr r8, pll_div_val + str r8, [r4] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r4, flash_cfg3_addr + ldr r8, flash_cfg3_val + str r8, [r4] + ldr r4, flash_cfg4_addr + ldr r8, flash_cfg4_val + str r8, [r4] + ldr r4, flash_cfg5_addr + ldr r8, flash_cfg5_val + str r8, [r4] + ldr r4, flash_cfg1_addr + ldr r8, [r4] + orr r8, r8, #0x3 /* up gpmc divider */ + str r8, [r4] + + /* setup to 2x loop though code. The first loop pre-loads the + * icache, the 2nd commits the prcm config, and locks the dpll + */ + mov r4, #0x1000 /* spin spin spin */ + mov r8, #0x4 /* first pass condition & set registers */ + cmp r8, #0x4 +2: + ldrne r8, [r3] /* DPLL lock check */ + and r8, r8, #0x7 + cmp r8, #0x2 + beq 4f +3: + subeq r8, r8, #0x1 + streq r8, [r0] /* commit dividers (2nd time) */ + nop +lloop1: + sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop1 + mov r4, #0x40000 + cmp r8, #0x1 + nop + streq r2, [r1] /* lock dpll (2nd time) */ + nop +lloop2: + sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop2 + mov r4, #0x40000 + cmp r8, #0x1 + nop + ldreq r8, [r3] /* get lock condition for dpll */ + cmp r8, #0x4 /* first time though? */ + bne 2b + moveq r8, #0x2 /* set to dpll check condition. */ + beq 3b /* if condition not true branch */ +4: + ldr r4, [sp] + add sp, sp, #0x4 /* return stack space */ + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_stat: + .word CM_IDLEST_CKGEN +pll_div_add: + .word CM_CLKSEL1_PLL +pll_div_val: + .word DPLL_VAL /* DPLL setting (300MHz default) */ + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + diff --git a/board/poseidon/mem.c b/board/poseidon/mem.c index e69de29..8f7dc65 100644 --- a/board/poseidon/mem.c +++ b/board/poseidon/mem.c @@ -0,0 +1,226 @@ +/* + *(C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * Derived from OMAPZOOM source(board/omap2430sdp/mem.c) + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or(at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap24xx.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <environment.h> +#include <command.h> + +/****** DATA STRUCTURES ************/ + +/* Only One NAND allowed on board at a time. +* The GPMC CS Base for the same +*/ + +/* Board CS Organization - Poseidon */ +static const unsigned char chip_sel_sdp[][GPMC_MAX_CS] = { + /* GPMC CS Indices */ + /* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */ + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 7 ON ON ON */ + {PROC_ONENAND, PROC_NAND, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1}, +}; + + +/* Values for each of the chips */ +static u32 gpmc_mpdb[GPMC_MAX_REG] = { + MPDB_GPMC_CONFIG1, + MPDB_GPMC_CONFIG2, + MPDB_GPMC_CONFIG3, + MPDB_GPMC_CONFIG4, + MPDB_GPMC_CONFIG5, + MPDB_GPMC_CONFIG6, 0 +}; +static u32 gpmc_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, 0 +}; + + + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in 12MHz bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile("1 : \n" "subs %0, %1, #1\n" + "bne 1b" : "=r"(loops) : "0"(loops)); +} + +/********************************************************************** + * prcm_init() - inits clocks for PRCM. + * -- called from SRAM, or Flash(using temp SRAM stack). + **********************************************************************/ +void prcm_init(void) +{ + /* Will be Implemented later(Currently IPL code doing imp conf) */ +} + +/*********************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontigious support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + ***********************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in gussing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP24XX_SDRC_CS0; + + __raw_writel(0x0, addr + 0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = __raw_readl(addr + 0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) { /* see if pos A value changed */ + return 0; + } else + return 1; +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ + /* Done in ONENAND IPL */ +} + +/****************************************************************** + * do_sdrc_init(): initialize the SDRAM for use. + *****************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ + /*Done in ONENAND IPL for Bank 0.Bank1 conf will be implemented later */ +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode(SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + + u32 mux = 0, mtype, mwidth, gpmc_base = 0; + u32 size = 0x0; + u32 base = 0x0; + unsigned char *config_sel = NULL; + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ + + /* discover bus connection from sysboot */ + mux = BIT9; + mtype = 0x7; + + mwidth = WIDTH_16BIT; + + /* setup cs0 */ + __raw_writel(0, GPMC_CONFIG7_0); /* disable current map */ + sdelay(1000); + /* GPMC5 is always MPDB.. need to know the chip info */ + gpmc_base = GPMC_CONFIG_CS0 + (5 * GPMC_CONFIG_WIDTH); + gpmc_mpdb[0] |= mux; + base = DEBUG_BASE; + size = DBG_MPDB_SIZE; + + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_mpdb[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_mpdb[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_mpdb[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_mpdb[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_mpdb[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_mpdb[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + + sdelay(2000); + config_sel = (unsigned char *)(chip_sel_sdp[mtype]); + gpmc_base = GPMC_CONFIG_CS0 + (0 * GPMC_CONFIG_WIDTH); + base = 0x0; + size = PROC_ONENAND_SIZE; + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_onenand[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_onenand[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_onenand[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_onenand[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_onenand[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_onenand[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + + sdelay(2000); + +} diff --git a/board/poseidon/poseidon.c b/board/poseidon/poseidon.c index e69de29..34fc203 100644 --- a/board/poseidon/poseidon.c +++ b/board/poseidon/poseidon.c @@ -0,0 +1,594 @@ +/* + *(C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * Derived from OMAPZOOM source(board/omap2430sdp/omap2430sdp.c) + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or(at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap24xx.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/mem.h> +#include <i2c.h> +#include <asm/mach-types.h> + +#define write_config_reg(reg, value) \ +do { \ + writeb(value, reg); \ +} while (0) + +#define mask_config_reg(reg, mask) \ +do { \ + char value = readb(reg) & ~(mask); \ + writeb(value, reg); \ +} while (0) + +void wait_for_command_complete(unsigned int wd_base); + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile("1 : \n" "subs %0, %1, #1\n" + "bne 1b" : "=r"(loops) : "0"(loops)); +} + +void muxSetupUART1(void) +{ + /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); + /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); + /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_TX, 0); + /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_RX, 0); + +} + + + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + + (*(volatile unsigned int*)0x49002030) |= (0x18<<16); + *(volatile unsigned int*)0x49006200 |= (1<<17); + *(volatile unsigned int*)0x49006210 |= (1<<17); + *(volatile unsigned int*)0x490062A0 |= (1<<17); + __raw_writeb(0x1b, 0x4900211a); + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_POSEIDON; + /*add of boot parameters*/ + gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100); + + return 0; + +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + *(GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE(PM_RT)*/ + /* REQ_INFO_PERMISSION_1 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); + /* ADDR_MATCH_1 L*/ + __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); + /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); + /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); + /* ADDR_MATCH_2 L*/ + __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); + + /* IVA Changes */ + /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); + +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ + +void try_unlock_sram(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device-HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock(); + return; + +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with sram stack. + **********************************************************/ +void s_init(void) +{ + int in_sdram = running_in_sdram(); + /* u32 rev = get_cpu_rev(); unused as of now.. */ + + watchdog_init(); + try_unlock_sram();/* Do SRAM availability first*/ + + set_muxconf_regs(); + delay(100); + + if (!in_sdram) + prcm_init(); + + peripheral_enable(); + icache_enable(); + if (!in_sdram) + sdrc_init(); + +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet(done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + ether_init(); /* better done here so timers are init'ed */ + return 0; + +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * The ROM takes care of the secure one. Of the 3 GP ones, + * 1 can reset us directly, the other 2 only generate MPU interrupts + */ + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); + +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); + +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + /* u32 rev = get_cpu_rev(); unused as of now */ + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + +h4reset_err_out: + return; +#endif + +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + u8 data; +#endif +#define NOT_EARLY 0 + +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + select_bus(1, CONFIG_SYS_I2C_SPEED); /* select bus with T2 on it */ +#endif + mtype = get_mem_type(); + display_board_info(btype); + + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) + /* init other chip select and map CS1 right after CS0 */ + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; + +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writeb((VALUE), OMAP24XX_CTRL_BASE + (OFFSET)); + +#ifdef CONFIG_2430 +#define MUX_DEFAULT()\ +/* SDRC */\ +MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */\ +MUX_VAL(0x0055, 0x00) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */\ +MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */\ +MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */\ +MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */\ +/* GPMC */\ +MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */\ +MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */\ +MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */\ +MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */\ +MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */\ +MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */\ +MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */\ +MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */\ +MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */\ +MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */\ +MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */\ +MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */\ +/* GPMC mux for NAND access */\ +MUX_VAL(0x0086, 0x18) /* gpmc_a9 - EN, HI, 0*/\ +MUX_VAL(0x0087, 0x18) /* gpmc_a8 - EN, HI, 0*/\ +MUX_VAL(0x0088, 0x18) /* gpmc_a7 - EN, HI, 0*/\ +MUX_VAL(0x0089, 0x18) /* gpmc_a6 - EN, HI, 0*/\ +MUX_VAL(0x008A, 0x18) /* gpmc_a5 - EN, HI, 0*/\ +MUX_VAL(0x008B, 0x18) /* gpmc_a4 - EN, HI, 0*/\ +MUX_VAL(0x008C, 0x18) /* gpmc_a3 - EN, HI, 0*/\ +MUX_VAL(0x008D, 0x18) /* gpmc_a2 - EN, HI, 0*/\ +MUX_VAL(0x008E, 0x18) /* gpmc_a1 - EN, HI, 0*/\ +MUX_VAL(0x008F, 0x18) /* gpmc_d15 - EN,HI, 0*/\ +MUX_VAL(0x0090, 0x18) /* gpmc_d14 - EN, HI, 0*/\ +MUX_VAL(0x0091, 0x18) /* gpmc_d13 - EN, HI, 0*/\ +MUX_VAL(0x0092, 0x18) /* gpmc_d12 - EN, HI, 0*/\ +MUX_VAL(0x0093, 0x18) /* gpmc_d11 - EN, HI, 0*/\ +MUX_VAL(0x0094, 0x18) /* gpmc_d10 - EN, HI, 0*/\ +MUX_VAL(0x0095, 0x18) /* gpmc_d9 - EN, HI, 0 */\ +MUX_VAL(0x0096, 0x18) /* gpmc_d8 - EN, HI, 0*/\ +/* DSS */\ +MUX_VAL(0x009F, 0x00) /* dss_data0- Dis, 0 */\ +MUX_VAL(0x00A0, 0x00) /* dss_data1- Dis, 0 */\ +MUX_VAL(0x00A1, 0x00) /* dss_data2- Dis, 0 */\ +MUX_VAL(0x00A2, 0x00) /* dss_data3- Dis, 0 */\ +MUX_VAL(0x00A3, 0x00) /* dss_data4- Dis, 0 */\ +MUX_VAL(0x00A4, 0x00) /* dss_data5- Dis, 0 */\ +MUX_VAL(0x00A5, 0x00) /* dss_data6- Dis, 0 */\ +MUX_VAL(0x00A6, 0x00) /* dss_data7- Dis, 0 */\ +MUX_VAL(0x00A7, 0x00) /* dss_data8- Dis, 0 */\ +MUX_VAL(0x00A8, 0x00) /* dss_data9- Dis, 0 */\ +MUX_VAL(0x00A9, 0x00) /* dss_data10- Dis, 0 */\ +MUX_VAL(0x00AA, 0x00) /* dss_data11- Dis, 0 */\ +MUX_VAL(0x00AB, 0x00) /* dss_data12- Dis, 0 */\ +MUX_VAL(0x00AC, 0x00) /* dss_data13- Dis, 0 */\ +MUX_VAL(0x00AD, 0x00) /* dss_data14- Dis, 0 */\ +MUX_VAL(0x00AE, 0x00) /* dss_data15- Dis, 0 */\ +MUX_VAL(0x00AF, 0x00) /* dss_data16- Dis, 0 */\ +MUX_VAL(0x00B0, 0x00) /* dss_data17- Dis, 0 */\ +MUX_VAL(0x00B9, 0x00) /* dss_hsync- Dis, 0 */\ +MUX_VAL(0x00BA, 0x00) /* dss_acbias- Dis, 0 */\ +MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */\ +MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */\ +MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */\ +MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */\ +MUX_VAL(0x00B5, 0x1B) /* mcbsp2_dr- EN, HI, 3, ->gpio_11 */\ +MUX_VAL(0x00B6, 0x1B) /* mcbsp2_clkx- EN, HI, 3, ->gpio_12 */\ +MUX_VAL(0x00B7, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +MUX_VAL(0x00B8, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +MUX_VAL(0x00B9, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +MUX_VAL(0x00BA, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +/* CONTROL */\ +MUX_VAL(0x00BB, 0x00) /* sys_nrespwron- Dis, 0 */\ +MUX_VAL(0x00BC, 0x00) /* sys_nreswarm- Dis, 0 */\ +MUX_VAL(0x00BD, 0x18) /* sys_nirq0- EN, HI, 0 */\ +/*MUX_VAL(0x00BD, 0x1B)*/ /* sys_nirq0- EN, HI, 3, ->gpio_56 */\ +MUX_VAL(0x00BE, 0x18) /* sys_nirq1- EN, HI, 0 */\ +MUX_VAL(0x00C7, 0x00) /* gpio_132- Dis, 0, ->gpio132 */\ +MUX_VAL(0x00CB, 0x00) /* gpio_133- Dis, 0, ->gpio133 */\ +MUX_VAL(0x00C9, 0x18) /* sys_clkout- Dis, 0 */\ +/*MUX_VAL(0x00C9, 0x1B)*/ /* sys_clkout- EN, HI, 3, ->gpio_111 */\ +MUX_VAL(0x00CC, 0x18) /* jtag_emu1- EN, HI, 0 */\ +MUX_VAL(0x00CD, 0x18) /* jtag_emu0- EN, HI, 0 */\ +/* CAMERA */\ +MUX_VAL(0x00DD, 0x02) /* cam_d0- Dis, 2, sti_dout */\ +MUX_VAL(0x00DC, 0x02) /* cam_d1- Dis, 2, sti_din */\ +MUX_VAL(0x00DB, 0x1B) /* cam_d2- EN, HI, 3, ->gpio_129 */\ +MUX_VAL(0x00DA, 0x1B) /* cam_d3- EN, HI, 3, ->gpio_128 */\ +MUX_VAL(0x00D9, 0x00) /* cam_d4- Dis, 0 */\ +MUX_VAL(0x00D8, 0x00) /* cam_d5- Dis, 0 */\ +MUX_VAL(0x00D7, 0x00) /* cam_d6- Dis, 0 */\ +MUX_VAL(0x00D6, 0x00) /* cam_d7- Dis, 0 */\ +MUX_VAL(0x00D5, 0x00) /* cam_d8- Dis, 0 */\ +MUX_VAL(0x00D4, 0x00) /* cam_d9- Dis, 0 */\ +MUX_VAL(0x00E3, 0x00) /* cam_d10- Dis, 0 */\ +MUX_VAL(0x00E2, 0x00) /* cam_d11- Dis, 0 */\ +MUX_VAL(0x00DE, 0x00) /* cam_hs- Dis, 0 */\ +MUX_VAL(0x00DF, 0x00) /* cam_vs- Dis, 0 */\ +MUX_VAL(0x00E0, 0x00) /* cam_lclk- Dis, 0 */\ +MUX_VAL(0x00E1, 0x00) /* cam_xclk- Dis, 0 */\ +MUX_VAL(0x00E4, 0x01) /* gpio_134- Dis, 1, ->ccp_datn */\ +MUX_VAL(0x00E5, 0x01) /* gpio_135- Dis, 1, ->ccp_datp */\ +MUX_VAL(0x00E6, 0x01) /* gpio_136- Dis, 1, ->ccp_clkn */\ +MUX_VAL(0x00E7, 0x01) /* gpio_137- Dis, 1, ->ccp_clkp */\ +MUX_VAL(0x00E8, 0x01) /* gpio_138- Dis, 1, ->spi3_clk */\ +MUX_VAL(0x00E9, 0x01) /* gpio_139- Dis, 1, ->spi3_cs0 */\ +MUX_VAL(0x00EA, 0x01) /* gpio_140- Dis, 1, ->spi3_simo */\ +MUX_VAL(0x00EB, 0x01) /* gpio_141- Dis, 1, ->spi3_somi */\ +MUX_VAL(0x00EC, 0x18) /* gpio_142- EN, HI, 0, ->gpio_142 */\ +MUX_VAL(0x00ED, 0x18) /* gpio_154- EN, HI, 0, ->gpio_154 */\ +MUX_VAL(0x00EE, 0x18) /* gpio_148- EN, HI, 0, ->gpio_148 */\ +MUX_VAL(0x00EF, 0x18) /* gpio_149- EN, HI, 0, ->gpio_149 */\ +MUX_VAL(0x00F0, 0x18) /* gpio_150- EN, HI, 0, ->gpio_150 */\ +MUX_VAL(0x00F1, 0x18) /* gpio_152- EN, HI, 0, ->gpio_152 */\ +MUX_VAL(0x00F2, 0x18) /* gpio_153- EN, HI, 0, ->gpio_153 */\ +/* MMC1 */\ +MUX_VAL(0x00F3, 0x00) /* mmc1_clko- Dis, 0 */\ +MUX_VAL(0x00F4, 0x18) /* mmc1_cmd- EN, HI, 0 */\ +MUX_VAL(0x00F5, 0x18) /* mmc1_dat0- EN, HI, 0 */\ +MUX_VAL(0x00F6, 0x18) /* mmc1_dat1- EN, HI, 0 */\ +MUX_VAL(0x00F7, 0x18) /* mmc1_dat2- EN, HI, 0 */\ +MUX_VAL(0x00F8, 0x18) /* mmc1_dat3- EN, HI, 0 */\ +/* MMC2 */\ +MUX_VAL(0x00F9, 0x00) /* mmc2_clko- Dis, 0 */\ +MUX_VAL(0x00FA, 0x18) /* mmc2_cmd- EN, HI, 0 */\ +MUX_VAL(0x00FB, 0x18) /* mmc2_dat0- EN, HI, 0 */\ +MUX_VAL(0x00FC, 0x18) /* mmc2_dat1- EN, HI, 0 */\ +MUX_VAL(0x00FD, 0x18) /* mmc2_dat2- EN, HI, 0 */\ +MUX_VAL(0x00FE, 0x18) /* mmc2_dat3- EN, HI, 0 */\ +/* UART2 */\ +MUX_VAL(0x00FF, 0x00) /* uart2_cts- Dis, 0 */\ +MUX_VAL(0x0100, 0x1B) /* uart2_rts- Dis, 0 gpio-68 by jhchoi*/\ +MUX_VAL(0x0101, 0x00) /* uart2_tx- Dis, 0 */\ +MUX_VAL(0x0102, 0x1B) /* uart2_rx- Dis, 0 */\ +/* MCBSP3 */\ +MUX_VAL(0x0103, 0x00) /* mcbsp3_clkx- Dis, 0 */\ +MUX_VAL(0x0104, 0x00) /* mcbsp3_fsx- Dis, 0 */\ +MUX_VAL(0x0105, 0x00) /* mcbsp3_dr- Dis, 0 */\ +MUX_VAL(0x0106, 0x00) /* mcbsp3_dx- Dis, 0 */\ +/* SSI1 */\ +MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */\ +MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */\ +MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */\ +MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */\ +MUX_VAL(0x010B, 0x01) /* gpio_63- Dis, 1, ->mcbsp4_clkx */\ +MUX_VAL(0x010C, 0x01) /* ssi1_flag_rx- Dis, 1, ->mcbsp4_dr */\ +MUX_VAL(0x010D, 0x01) /* ssi1_rdy_rx- Dis, 1, ->mcbsp4_dx */\ +MUX_VAL(0x010E, 0x01) /* ssi1_wake- Dis, 1, ->mcbsp4_fsx */\ +/* SPI1 */\ +MUX_VAL(0x010F, 0x00) /* spi1_clk- Dis, 0 */\ +MUX_VAL(0x0110, 0x00) /* spi1_simo- Dis, 0 */\ +MUX_VAL(0x0111, 0x00) /* spi1_somi- Dis, 0 */\ +MUX_VAL(0x0112, 0x00) /* spi1_cs0- Dis, 0 */\ +MUX_VAL(0x0113, 0x00) /* spi1_cs1- Dis, 0 */\ +MUX_VAL(0x0114, 0x00) /* spi1_cs2- Dis, 0 */\ +MUX_VAL(0x0115, 0x00) /* spi1_cs3- Dis, 0 */\ +/* SPI2 */\ +MUX_VAL(0x0116, 0x1B) /* spi2_clk- EN, HI, 3, ->gpio_88 */\ +MUX_VAL(0x0117, 0x1B) /* spi2_simo- EN, HI, 3, ->gpio_89 */\ +MUX_VAL(0x0118, 0x1B) /* spi2_somi- EN, HI, 3, ->gpio_90 */\ +MUX_VAL(0x0119, 0x1B) /* spi2_cs0- EN, HI, 3, ->gpio_91 */\ +/* MCBSP1 */\ +MUX_VAL(0x011A, 0x00) /* mcbsp1_clkr- Dis, 0 */\ +MUX_VAL(0x011B, 0x00) /* mcbsp1_fsr- Dis, 0 */\ +MUX_VAL(0x011C, 0x00) /* mcbsp1_dx- Dis, 0 */\ +MUX_VAL(0x011D, 0x0B) /* mcbsp1_dr- Dis, 0 */\ +MUX_VAL(0x011E, 0x00) /* mcbsp1_clks- Dis, 0 */\ +MUX_VAL(0x011F, 0x00) /* mcbsp1_fsx- Dis, 0 */\ +MUX_VAL(0x0120, 0x00) /* mcbsp1_clkx- Dis, 0 */\ +/* HDQ */\ +MUX_VAL(0x0125, 0x00) /* hdq_sio- Dis, 0 */\ +/* UART3 */\ +MUX_VAL(0x0126, 0x00) /* uart3_cts_rctx- Dis, 0 */\ +MUX_VAL(0x0127, 0x00) /* uart3_rts_sd- Dis, 0 */\ +MUX_VAL(0x0128, 0x00) /* uart3_tx_irtx- Dis, 0 */\ +MUX_VAL(0x0129, 0x00) /* uart3_rx_irrx- Dis, 0 */\ +/* OTHERS */\ +MUX_VAL(0x012B, 0x1B) /* gpio_78- EN, HI, 3, ->gpio_78 */\ +MUX_VAL(0x012C, 0x01) /* gpio_79- Dis, 1, ->secure_indicator */\ +MUX_VAL(0x012D, 0x1B) /* gpio_80- EN, HI, 3, ->gpio_80 */\ +/* MCBSP2 */\ +MUX_VAL(0x012E, 0x01) /* gpio_113- Dis, 1, ->mcbsp2_clkx */\ +MUX_VAL(0x012F, 0x01) /* gpio_114- Dis, 1, ->mcbsp2_fsx */\ +MUX_VAL(0x0130, 0x01) /* gpio_115- Dis, 1, ->mcbsp2_dr */\ +MUX_VAL(0x0131, 0x01) /* gpio_116- Dis, 1, ->mcbsp2_dx */\ +/* GPIO7-AUDIOENVDD */\ +MUX_VAL(0x012A, 0x18) /* gpio_7- EN, HI, 3, ->gpio_7 */\ + +#else +/* For all other platforms */ +#define MUX_DEFAULT()\ + /* SDRC */\ +MUX_VAL(0x0054, 0x08) /* sdrc_a14 - EN, LO, 0 */\ +MUX_VAL(0x0055, 0x08) /* sdrc_a13 - EN, LO, 0 */\ +MUX_VAL(0x0056, 0x08) /* sdrc_a12 - EN, LO, 0 */\ +MUX_VAL(0x0045, 0x18) /* sdrc_ncs1 - EN, HI, 0 */\ +MUX_VAL(0x0046, 0x18) /* sdrc_ncs2 - EN, HI, 0 */\ +/* GPMC */\ +MUX_VAL(0x0030, 0x08) /* gpmc_clk - EN, LO, 0 */\ +MUX_VAL(0x0032, 0x18) /* gpmc_ncs1- EN, HI, 0 */\ +MUX_VAL(0x0033, 0x18) /* gpmc_ncs2- EN, HI, 0 */\ +MUX_VAL(0x0034, 0x18) /* gpmc_ncs3- EN, HI, 0 */\ +/* UART1 */\ +MUX_VAL(0x00B1, 0x18) /* uart1_cts- EN, HI, 0 */\ +MUX_VAL(0x00B2, 0x18) /* uart1_rts- EN, HI, 0 */\ +MUX_VAL(0x00B3, 0x18) /* uart1_tx- EN, HI, 0 */\ +MUX_VAL(0x00B4, 0x18) /* uart1_rx- EN, HI, 0 */\ +/* UART2 */\ +MUX_VAL(0x00FF, 0x18) /* uart2_cts- EN, HI, 0 */\ +MUX_VAL(0x0100, 0x18) /* uart2_rts- EN, HI, 0 */\ +MUX_VAL(0x0101, 0x18) /* uart2_tx- EN, HI, 0 */\ +MUX_VAL(0x0102, 0x18) /* uart2_rx- EN, HI, 0 */\ +/* UART3 */\ +MUX_VAL(0x0126, 0x18) /* uart3_cts_rctx- EN, HI, 0 */\ +MUX_VAL(0x0127, 0x18) /* uart3_rts_sd- EN, HI, 0 */\ +MUX_VAL(0x0127, 0x18) /* uart3_tx_irtx- EN, HI, 0 */\ +MUX_VAL(0x0127, 0x18) /* uart3_rx_irrx- EN, HI, 0 */\ +/* I2C1 */\ +MUX_VAL(0x0111, 0x00) /* i2c1_scl - DIS, NA, 0 */\ +MUX_VAL(0x0112, 0x00) /* i2c1_sda - DIS, NA, 0 */\ + +#endif /* End of Mux Mapping */ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + u32 cpu; + cpu = get_cpu_type(); + /*Incase we have to handle multiple processors such as 2430 and 2430C */ + if (cpu == CPU_2430) { + MUX_DEFAULT(); + } else + return; + +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs(GPT2, UART1,...) + ******************************************************************/ +void peripheral_enable(void) +{ + unsigned int v, if_clks1 = 0, func_clks1 = 0; + unsigned int if_clks2 = 0, func_clks2 = 0; + /* ALERT STATUS 10000 */ + /* Enable GP2 timer. */ + if_clks1 |= BIT4; + func_clks1 |= BIT4; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;/* Sys_clk input OMAP24XX_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CONFIG_SYS_NS16550 + /* Enable UART1 clock */ + func_clks1 |= BIT21; + if_clks1 |= BIT21; +#endif +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + /* 2430 requires only the hs clock */ + func_clks2 |= BIT20|BIT19; /* i2c1 and 2 96 meg clock input */ + if_clks1 |= BIT20|BIT19; +#endif + + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks1;/* Interface clocks on */ + __raw_writel(v, CM_ICLKEN1_CORE); + v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2;/* Interface clocks on */ + __raw_writel(v, CM_ICLKEN2_CORE); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks1;/* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2;/* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN2_CORE); + delay(1000); +} + +/***************************************************************************** + * Routine: update_mux() + * Description: Update balls which are different beween boards. All should be + * updated to match functionaly. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} diff --git a/board/poseidon/sys_info.c b/board/poseidon/sys_info.c index e69de29..c64f442 100644 --- a/board/poseidon/sys_info.c +++ b/board/poseidon/sys_info.c @@ -0,0 +1,380 @@ +/* + *(C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or(at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap24xx.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> /* get mem tables */ +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <i2c.h> + +/**************************************************************************** + * check_fpga_revision number: the rev number should be a or b 0xA203/5 + * variant did not have it, but the B101 variant has EEPROM update facility + ***************************************************************************/ +static inline u16 check_fpga_rev(void) +{ + return __raw_readw(FPGA_REV_REGISTER); +} + +/**************************************************************************** + * check_eeprom_avail: Check FPGA Availability + * OnBoard DEBUG FPGA registers need to be ready for us to proceed + * Required to retrieve the bootmode also. + ***************************************************************************/ +int check_eeprom_avail(u32 offset) +{ + return 0; +} + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + if (!check_fpga_rev()) + /* we dont have an DEBUG FPGA??? */ + /* Depend on #defines!! default to strata boot return param */ + return 0x0; + cs = (u8) __raw_readw(DIP_SWITCH_INPUT_REG2); + /* The bits are inverted- S8 0-2 define the CS0 select */ + return (~cs) & 0x07; +} + +/************************************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + * - just looking to say if this is a 2422 or 2420 or ... + * - to start with we will look at switch settings.. + * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics + * (mux for 2420, non-mux for 2422). + ***************************************************************************/ +u32 get_cpu_type(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v &= CPU_24XX_ID_MASK; + + if (v == CPU_2430_CHIPID) { + return CPU_2430; + } else + return -1; /* don't know,return invalid val */ +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return v + 1; +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == H4_2420_SDRC_MR_0_SDR) + return 1; + return 0; +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + * 2422 uses stacked DDR, 2 parts CS0/CS1. + * 2420 may have 1 or 2, no good way to know...only init 1... + * when eeprom data is up we can select 1 more. + *************************************************************/ +u32 get_mem_type(void) +{ + return DDR_DISCRETE; +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return size; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings(dip switch on h4) + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return 0x00000FFF & __raw_readl(CONTROL_STATUS); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return b; +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16(mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + u32 width; + width = get_sysboot_value(); + if ((width & 0xF) == (BIT3 | BIT2)) { + return WIDTH_8BIT; + } else + return WIDTH_16BIT; + +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} + +/***************************************************************** + * is_gpmc_muxed() - tells if address/data lines are multiplexed + *****************************************************************/ +u32 is_gpmc_muxed(void) +{ + u32 mux; + mux = get_sysboot_value(); + if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) + return GPMC_MUXED; /* NAND Boot mode */ + if (mux & BIT1) {/* if mux'ed */ + return GPMC_MUXED; + } else + return GPMC_NONMUXED; +} + +/************************************************************************* + * get_board_rev () - setup to pass board revision information + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Default Value as per now Poseidon Board have only one Revision */ + return 0x01; +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "ONND", + "SIB1", + "SIB0", + "NAND", + "SIB1", + "SIB0", + "NOR", + "OneNAND", + }; + u32 brev = get_board_rev(); + char cpu_2430s[] = "2430C"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + char t_poseidon[] = "POSEIDON"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(PRCM_CONFIG_I) + char prcm[] = "I"; +#elif defined(PRCM_CONFIG_II) + char prcm[] = "II"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s, *sdp; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) { + mem_s = mem_sdr; + } else + mem_s = mem_ddr; + + cpu_s = cpu_2430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + sdp = t_poseidon; + + printf("OMAP%s-%s revision %d, PRCM %s\n", cpu_s, sec_s, rev, prcm); + printf("SAMSUNG %s %s Version + %s(Boot %s)\n", sdp, db_s, + mem_s, bootmode[get_gpmc0_type()]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 2430C GP#5A NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, prcm, + bootmode[get_gpmc0_type()]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r"(val) : : "memory"); + val &= 0xF0000000; + val >>= 28; + return val; +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return 1; /* in flash */ + return 0; /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return 1; /* in SRAM */ + return 0; /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return 1; /* in sdram */ + return 0; /* running in SRAM or FLASH */ +} + +/************************************************************* + * running_from_internal_boot() - am I boot through mask rom. + *************************************************************/ +u32 running_from_internal_boot(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT2 | BIT1 | BIT0); + /* external boot settings bit1 == bit2 */ + if (((v & BIT1) && (v & BIT2)) || (!(v & BIT1) && !(v & BIT2))) { + v = 0; + } else /* all other defined combos are internal */ + v = 1; + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return mode >>= 8; +} diff --git a/board/poseidon/u-boot.lds b/board/poseidon/u-boot.lds index e69de29..13f1971 100644 --- a/board/poseidon/u-boot.lds +++ b/board/poseidon/u-boot.lds @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +}

2 2

[U-Boot] Continuos reboot in u-boot 1.3.4
by Virupax.SS＠Lntemsys.com 26 Aug '09

26 Aug '09

Hi I am using u-boot 1.3.4 ( got from atmel) on AT91SAM9G20 , If enable the ethernet related code in the u-boot ( drivers etc) the board starts resetting again and again continuously without giving any error message. Please somebody tell me what type of mistakes ( coding errors ) make the board to reset in u-boot. Or it is because of writing some wrong values in the controller resisters. Thanks

1 0

[U-Boot] Hush - reading value from memory and setup variable
by Michal Simek 26 Aug '09

26 Aug '09

Hi all, I have in memory string/values whatever and I would like to setup some u-boot variables based on it directly from HUSH I mean for example to have there unique MAC addr and I would like to setup it in preboot. I am trying to find out any U-BOOT commands which could help me. But I am not sure if is even possible to do it directly from hush. Writing any specific C code is easy. Any ideas? Thanks, Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian

1 0

[U-Boot] [PATCH 1/2] drivers/mmc/atmel_mci.c: port to the new CONFIG_GENERIC_MMC API
by Albin Tonnerre 26 Aug '09

26 Aug '09

This patch updates (well, pretty much rewrites, actually) the atmel_mci driver so that it can be used with the new mmc API. Currently, the driver only supports what the previous driver supported, that is: - assumes that the MMC slot was configured in the cpu/board code, no slot-switching - doesn't support writing, only reading Support for these features will come in a later patch. Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- drivers/mmc/atmel_mci.c | 604 +++++++++++++++++++---------------------------- 1 files changed, 240 insertions(+), 364 deletions(-) diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c index 3946ffe..b07deba 100644 --- a/drivers/mmc/atmel_mci.c +++ b/drivers/mmc/atmel_mci.c @@ -1,6 +1,9 @@ /* * Copyright (C) 2004-2006 Atmel Corporation * + * Copyright (C) 2009 + * Albin Tonnerre, Free-Electrons <albin.tonnerre(a)free-electrons.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -38,40 +41,43 @@ #define pr_debug(...) do { } while(0) #endif -#ifndef CONFIG_SYS_MMC_CLK_OD -#define CONFIG_SYS_MMC_CLK_OD 150000 -#endif - -#ifndef CONFIG_SYS_MMC_CLK_PP -#define CONFIG_SYS_MMC_CLK_PP 5000000 -#endif - -#ifndef CONFIG_SYS_MMC_OP_COND -#define CONFIG_SYS_MMC_OP_COND 0x00100000 -#endif - -#define MMC_DEFAULT_BLKLEN 512 -#define MMC_DEFAULT_RCA 1 +#define RESP_NO_CRC 1 +#define RESP_48BITS MMCI_BF(RSPTYP, 1) +#define RESP_136BITS MMCI_BF(RSPTYP, 2) +#define RESP_48BITS_NOCRC (RESP_48BITS | RESP_NO_CRC) +#define NID MMCI_BF(MAXLAT, 0) +#define NCR MMCI_BF(MAXLAT, 1) +#define TRCMD_START MMCI_BF(TRCMD, 1) +#define TRCMD_STOP MMCI_BF(TRCMD, 2) +#define TRDIR_READ MMCI_BF(TRDIR, 1) +#define TRTYP_BLOCK MMCI_BF(TRTYP, 0) + +#define ERROR_FLAGS (MMCI_BIT(DCRCE) \ + | MMCI_BIT(RDIRE) \ + | MMCI_BIT(RENDE) \ + | MMCI_BIT(RINDE) \ + | MMCI_BIT(RTOE)) -static unsigned int mmc_rca; -static int mmc_card_is_sd; -static block_dev_desc_t mmc_blkdev; +struct atmel_mci_host { + struct mmc *mmc; + struct mmc_cmd *cmd; + struct mmc_data *data; + u32 dtor; +}; -block_dev_desc_t *mmc_get_dev(int dev) -{ - return &mmc_blkdev; -} +static struct atmel_mci_host atmel_mci_host; +static struct atmel_mci_host *host = &atmel_mci_host; -static void mci_set_mode(unsigned long hz, unsigned long blklen) +static void atmel_mci_set_clk_rate(unsigned long hz) { unsigned long bus_hz; unsigned long clkdiv; + u32 mr; bus_hz = get_mci_clk_rate(); clkdiv = (bus_hz / hz) / 2 - 1; - pr_debug("mmc: setting clock %lu Hz, block size %lu\n", - hz, blklen); + pr_debug("mmc: setting clock %lu Hz\n", hz); if (clkdiv & ~255UL) { clkdiv = 255; @@ -79,34 +85,22 @@ static void mci_set_mode(unsigned long hz, unsigned long blklen) hz); } - blklen &= 0xfffc; - mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) - | MMCI_BF(BLKLEN, blklen) - | MMCI_BIT(RDPROOF) - | MMCI_BIT(WRPROOF))); + mr = mmci_readl(MR); + mmci_writel(MR, MMCI_BFINS(CLKDIV, clkdiv, mr)); } -#define RESP_NO_CRC 1 -#define R1 MMCI_BF(RSPTYP, 1) -#define R2 MMCI_BF(RSPTYP, 2) -#define R3 (R1 | RESP_NO_CRC) -#define R6 R1 -#define NID MMCI_BF(MAXLAT, 0) -#define NCR MMCI_BF(MAXLAT, 1) -#define TRCMD_START MMCI_BF(TRCMD, 1) -#define TRDIR_READ MMCI_BF(TRDIR, 1) -#define TRTYP_BLOCK MMCI_BF(TRTYP, 0) -#define INIT_CMD MMCI_BF(SPCMD, 1) -#define OPEN_DRAIN MMCI_BF(OPDCMD, 1) - -#define ERROR_FLAGS (MMCI_BIT(DTOE) \ - | MMCI_BIT(RDIRE) \ - | MMCI_BIT(RENDE) \ - | MMCI_BIT(RINDE) \ - | MMCI_BIT(RTOE)) + +static void atmel_mci_set_blklen(unsigned long blklen) +{ + u32 mr; + + blklen &= 0xfffc; + mr = mmci_readl(MR); + mmci_writel(MR, MMCI_BFINS(BLKLEN, blklen, mr)); +} static int -mmc_cmd(unsigned long cmd, unsigned long arg, +atmel_mci_mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) { unsigned long *response = resp; @@ -140,7 +134,7 @@ mmc_cmd(unsigned long cmd, unsigned long arg, if (status & error_flags) { printf("mmc: command %lu failed (status: 0x%08x)\n", cmd, status); - return -EIO; + return status; } if (response_words) @@ -155,379 +149,261 @@ mmc_cmd(unsigned long cmd, unsigned long arg, return 0; } -static int mmc_acmd(unsigned long cmd, unsigned long arg, - void *resp, unsigned long flags) -{ - unsigned long aresp[4]; - int ret; - - /* - * Seems like the APP_CMD part of an ACMD has 64 cycles max - * latency even though the ACMD part doesn't. This isn't - * entirely clear in the SD Card spec, but some cards refuse - * to work if we attempt to use 5 cycles max latency here... - */ - ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp, - R1 | NCR | (flags & OPEN_DRAIN)); - if (ret) - return ret; - if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD) - return -ENODEV; - - ret = mmc_cmd(cmd, arg, resp, flags); - return ret; -} - -static unsigned long -mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, - void *buffer) +/* + * Trying to set the timeout in DTOR is useless here. On AT91, a hardware + * issue prevents the DTOE flag from being raised. On AT32P, DTOE won't + * raise for blocks smaller than 5 bytes, which might be an issue when + * doing writes. Just using a software timeout in all cases looks like + * the most reasonable solution. + */ +static u32 atmel_mci_calc_data_timeout(struct mmc *mmc) { - int ret, i = 0; - unsigned long resp[4]; - unsigned long card_status, data; - unsigned long wordcount; - u32 *p = buffer; - u32 status; - - if (blkcnt == 0) - return 0; + struct mmc_csd *csd = (struct mmc_csd *) mmc->csd; - pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n", - dev, start, blkcnt); - - /* Put the device into Transfer state */ - ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); - if (ret) goto out; - - /* Set block length */ - ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); - if (ret) goto out; + static const unsigned int dtomul_to_shift[] = { + 0, 4, 7, 8, 10, 12, 16, 20, + }; + static const unsigned int taac_exp[] = { + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, + }; + static const unsigned int taac_mant[] = { + 0, 10, 12, 13, 15, 60, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80, + }; + unsigned int timeout_ns, timeout_clks; + unsigned int e, m; + unsigned int dtocyc, dtomul; + unsigned int shift; - pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + e = csd->taac & 0x07; + m = (csd->taac >> 3) & 0x0f; - for (i = 0; i < blkcnt; i++, start++) { - ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, - start * mmc_blkdev.blksz, resp, - (R1 | NCR | TRCMD_START | TRDIR_READ - | TRTYP_BLOCK)); - if (ret) goto out; + timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; + timeout_clks = csd->nsac * 100; - ret = -EIO; - wordcount = 0; - do { - do { - status = mmci_readl(SR); - if (status & (ERROR_FLAGS | MMCI_BIT(OVRE))) - goto read_error; - } while (!(status & MMCI_BIT(RXRDY))); - - if (status & MMCI_BIT(RXRDY)) { - data = mmci_readl(RDR); - /* pr_debug("%x\n", data); */ - *p++ = data; - wordcount++; - } - } while(wordcount < (mmc_blkdev.blksz / 4)); - - pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount); + timeout_clks += (((timeout_ns + 9) / 10) + * ((mmc->clock + 99999) / 100000) + 9999) / 10000; + if (IS_SD(mmc)) + timeout_clks *= 10; + else + timeout_clks *= 100; - do { - status = mmci_readl(SR); - } while (!(status & MMCI_BIT(BLKE))); + dtocyc = timeout_clks; + dtomul = 0; + shift = 0; + while (dtocyc > 15 && dtomul < 8) { + dtomul++; + shift = dtomul_to_shift[dtomul]; + dtocyc = (timeout_clks + (1 << shift) - 1) >> shift; + } - putc('.'); + if (dtomul >= 8) { + dtomul = 7; + dtocyc = 15; + puts("Warning: Using maximum data timeout\n"); } -out: - /* Put the device back into Standby state */ - mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); - return i; + pr_debug("mmc: Using %u cycles data timeout\n", dtocyc); -read_error: - mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); - printf("mmc: bread failed, status = %08x, card status = %08lx\n", - status, card_status); - goto out; + return dtomul * (dtocyc << shift); } -static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) +static void atmel_mci_finish_request(struct atmel_mci_host *host, + struct mmc_cmd *cmd, struct mmc_data *data) { - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = resp[2] >> 24; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 16; - cid->psn = (resp[2] << 16) | (resp[3] >> 16); - cid->mdt = resp[3] >> 8; + host->cmd = NULL; + host->data = NULL; } -static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) +static int atmel_mci_finish_data(struct atmel_mci_host *host, unsigned int stat) { - cid->mid = resp[0] >> 24; - cid->oid = (resp[0] >> 8) & 0xffff; - cid->pnm[0] = resp[0]; - cid->pnm[1] = resp[1] >> 24; - cid->pnm[2] = resp[1] >> 16; - cid->pnm[3] = resp[1] >> 8; - cid->pnm[4] = resp[1]; - cid->pnm[5] = 0; - cid->pnm[6] = 0; - cid->prv = resp[2] >> 24; - cid->psn = (resp[2] << 8) | (resp[3] >> 24); - cid->mdt = (resp[3] >> 8) & 0x0fff; -} + int data_error = 0; + if (stat & ERROR_FLAGS) { + printf("request failed. status: 0x%08x\n", + stat); + if (stat & MMCI_BIT(DCRCE)) { + data_error = -EILSEQ; + } else if (stat & MMCI_BIT(DTOE)) { + data_error = TIMEOUT; + } else { + data_error = -EIO; + } + } -static void mmc_dump_cid(const struct mmc_cid *cid) -{ - printf("Manufacturer ID: %02X\n", cid->mid); - printf("OEM/Application ID: %04X\n", cid->oid); - printf("Product name: %s\n", cid->pnm); - printf("Product Revision: %u.%u\n", - cid->prv >> 4, cid->prv & 0x0f); - printf("Product Serial Number: %lu\n", cid->psn); - printf("Manufacturing Date: %02u/%02u\n", - cid->mdt >> 4, cid->mdt & 0x0f); + host->data = NULL; + return data_error; } -static void mmc_dump_csd(const struct mmc_csd *csd) +static int atmel_mci_pull(struct atmel_mci_host *host, void *_buf, int bytes) { - unsigned long *csd_raw = (unsigned long *)csd; - printf("CSD data: %08lx %08lx %08lx %08lx\n", - csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); - printf("CSD structure version: 1.%u\n", csd->csd_structure); - printf("MMC System Spec version: %u\n", csd->spec_vers); - printf("Card command classes: %03x\n", csd->ccc); - printf("Read block length: %u\n", 1 << csd->read_bl_len); - if (csd->read_bl_partial) - puts("Supports partial reads\n"); - else - puts("Does not support partial reads\n"); - printf("Write block length: %u\n", 1 << csd->write_bl_len); - if (csd->write_bl_partial) - puts("Supports partial writes\n"); - else - puts("Does not support partial writes\n"); - if (csd->wp_grp_enable) - printf("Supports group WP: %u\n", csd->wp_grp_size + 1); - else - puts("Does not support group WP\n"); - printf("Card capacity: %u bytes\n", - (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) * - (1 << csd->read_bl_len)); - printf("File format: %u/%u\n", - csd->file_format_grp, csd->file_format); - puts("Write protection: "); - if (csd->perm_write_protect) - puts(" permanent"); - if (csd->tmp_write_protect) - puts(" temporary"); - putc('\n'); + unsigned int stat; + u32 timeout = 0; + u32 delay, status; + u32 *buf = _buf; + + delay = host->dtor / (get_mci_clk_rate() / 1000000); + while (bytes > 3) { + do { + status = mmci_readl(SR); + if (status & MMCI_BIT(RXRDY)) + break; + udelay(delay / 1000); + timeout += delay / 1000; + } while (timeout < delay); + if(timeout > delay) + return MMCI_BIT(DTOE); + *buf++ = mmci_readl(RDR); + bytes -= 4; + } + + while(mmci_readl(SR) & MMCI_BIT(DTIP)); + return 0; } -static int mmc_idle_cards(void) +static int atmel_mci_transfer_data(struct atmel_mci_host *host) { - int ret; + struct mmc_data *data = host->data; + int stat; + unsigned long length; - /* Reset and initialize all cards */ - ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); - if (ret) - return ret; + length = data->blocks * data->blocksize; - /* Keep the bus idle for 74 clock cycles */ - return mmc_cmd(0, 0, NULL, INIT_CMD); + if (data->flags & MMC_DATA_READ) { + stat = atmel_mci_pull(host, data->dest, length); + if (stat) + return stat; + } + else + return -EINVAL; + return 0; } -static int sd_init_card(struct mmc_cid *cid, int verbose) +static int atmel_mci_cmd_done(struct atmel_mci_host *host, unsigned int stat) { - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; i++) { - ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, - resp, R3 | NID); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; - } + int datastat; + int ret; - if (ret) - return ret; + if(stat & MMCI_BIT(RTOE)) + ret = TIMEOUT; + else + ret = stat; - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID); - if (ret) + if (ret) { + atmel_mci_finish_request(host, host->cmd, host->data); return ret; - sd_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); + } - /* Get RCA of the card that responded */ - ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); - if (ret) - return ret; + if (!host->data) { + atmel_mci_finish_request(host, host->cmd, host->data); + return 0; + } - mmc_rca = resp[0] >> 16; - if (verbose) - printf("SD Card detected (RCA %u)\n", mmc_rca); - mmc_card_is_sd = 1; - return 0; + datastat = atmel_mci_transfer_data(host); + ret = atmel_mci_finish_data(host, datastat); + atmel_mci_finish_request(host, host->cmd, host->data); + return ret; } -static int mmc_init_card(struct mmc_cid *cid, int verbose) +static void atmel_mci_setup_data(struct atmel_mci_host *host, struct mmc_data *data) { - unsigned long resp[4]; - int i, ret = 0; - - mmc_idle_cards(); - for (i = 0; i < 1000; i++) { - ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp, - R3 | NID | OPEN_DRAIN); - if (ret || (resp[0] & 0x80000000)) - break; - ret = -ETIMEDOUT; - } - - if (ret) - return ret; + host->data = data; + atmel_mci_set_blklen(data->blocksize); +} - /* Get CID of all cards. FIXME: Support more than one card */ - ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); - if (ret) - return ret; - mmc_parse_cid(cid, resp); - if (verbose) - mmc_dump_cid(cid); +static int atmel_mci_request(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + u32 flags = 0; + int ret; + struct atmel_mci_host *host = mmc->priv; + + host->cmd = cmd; + host->mmc = mmc; + + /* Only set the timeout once, when we know we have read the CSD */ + if(!host->dtor && mmc->capacity) + host->dtor = atmel_mci_calc_data_timeout(mmc); + + switch (cmd->resp_type) { + case MMC_RSP_R1: /* short CRC, OPCODE */ + case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */ + flags |= RESP_48BITS; + break; + case MMC_RSP_R2: /* long 136 bit + CRC */ + flags |= RESP_136BITS; + break; + case MMC_RSP_R3: /* short */ + flags |= RESP_48BITS_NOCRC; + break; + case MMC_RSP_NONE: + break; + default: + printf("atmel_mci: unhandled response type 0x%x\n", + cmd->resp_type); + return -EINVAL; + } + flags |= NCR; - /* Set Relative Address of the card that responded */ - ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, - R1 | NCR | OPEN_DRAIN); - return ret; + if(data) { + atmel_mci_setup_data(host, data); + flags |= TRCMD_START | TRDIR_READ | TRTYP_BLOCK; + } + ret = atmel_mci_mmc_cmd(cmd->cmdidx, cmd->cmdarg, cmd->response, cmd->flags | flags); + return atmel_mci_cmd_done(host, ret); } -static void mci_set_data_timeout(struct mmc_csd *csd) +static void atmel_mci_set_ios(struct mmc *mmc) { - static const unsigned int dtomul_to_shift[] = { - 0, 4, 7, 8, 10, 12, 16, 20, - }; - static const unsigned int taac_exp[] = { - 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, - }; - static const unsigned int taac_mant[] = { - 0, 10, 12, 13, 15, 60, 25, 30, - 35, 40, 45, 50, 55, 60, 70, 80, - }; - unsigned int timeout_ns, timeout_clks; - unsigned int e, m; - unsigned int dtocyc, dtomul; - unsigned int shift; - u32 dtor; + u32 sdcr; + struct atmel_mci_host *host = mmc->priv; - e = csd->taac & 0x07; - m = (csd->taac >> 3) & 0x0f; + if(mmc->clock) + atmel_mci_set_clk_rate(mmc->clock); + sdcr = mmci_readl(SDCR); - timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; - timeout_clks = csd->nsac * 100; - - timeout_clks += (((timeout_ns + 9) / 10) - * ((CONFIG_SYS_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; - if (!mmc_card_is_sd) - timeout_clks *= 10; + if(mmc->bus_width == 4) + sdcr |= MMCI_BIT(SCDBUS); else - timeout_clks *= 100; - - dtocyc = timeout_clks; - dtomul = 0; - shift = 0; - while (dtocyc > 15 && dtomul < 8) { - dtomul++; - shift = dtomul_to_shift[dtomul]; - dtocyc = (timeout_clks + (1 << shift) - 1) >> shift; - } + sdcr &= ~MMCI_BIT(SCDBUS); - if (dtomul >= 8) { - dtomul = 7; - dtocyc = 15; - puts("Warning: Using maximum data timeout\n"); - } + mmci_writel(SDCR, sdcr); +} - dtor = (MMCI_BF(DTOMUL, dtomul) - | MMCI_BF(DTOCYC, dtocyc)); - mmci_writel(DTOR, dtor); +static int atmel_mci_mmc_init(struct mmc *mmc) +{ + mmci_writel(CR, MMCI_BIT(SWRST)); + mmci_writel(MR, MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF)); + atmel_mci_set_clk_rate(mmc->f_min); - printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n", - dtocyc << shift, dtor); + return 0; } -int mmc_legacy_init(int verbose) +int atmel_mci_init(bd_t *bis) { - struct mmc_cid cid; - struct mmc_csd csd; - unsigned int max_blksz; - int ret; + struct mmc *mmc = NULL; + + mmc = calloc(1, sizeof(struct mmc)); + if (!mmc) + return -ENOMEM; - /* Initialize controller */ - mmci_writel(CR, MMCI_BIT(SWRST)); mmci_writel(CR, MMCI_BIT(MCIEN)); mmci_writel(DTOR, 0x5f); mmci_writel(IDR, ~0UL); - mci_set_mode(CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); - - mmc_card_is_sd = 0; - ret = sd_init_card(&cid, verbose); - if (ret) { - mmc_rca = MMC_DEFAULT_RCA; - ret = mmc_init_card(&cid, verbose); - } - if (ret) - return ret; + sprintf(mmc->name, "ATMEL MCI"); + mmc->send_cmd = atmel_mci_request; + mmc->set_ios = atmel_mci_set_ios; + mmc->init = atmel_mci_mmc_init; + mmc->host_caps = MMC_MODE_4BIT; - /* Get CSD from the card */ - ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR); - if (ret) - return ret; - if (verbose) - mmc_dump_csd(&csd); - - mci_set_data_timeout(&csd); - - /* Initialize the blockdev structure */ - mmc_blkdev.if_type = IF_TYPE_MMC; - mmc_blkdev.part_type = PART_TYPE_DOS; - mmc_blkdev.block_read = mmc_bread; - sprintf((char *)mmc_blkdev.vendor, - "Man %02x%04x Snr %08lx", - cid.mid, cid.oid, cid.psn); - strncpy((char *)mmc_blkdev.product, cid.pnm, - sizeof(mmc_blkdev.product)); - sprintf((char *)mmc_blkdev.revision, "%x %x", - cid.prv >> 4, cid.prv & 0x0f); - - /* - * If we can't use 512 byte blocks, refuse to deal with the - * card. Tons of code elsewhere seems to depend on this. - */ - max_blksz = 1 << csd.read_bl_len; - if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) { - printf("Card does not support 512 byte reads, aborting.\n"); - return -ENODEV; - } - mmc_blkdev.blksz = 512; - mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2)); + mmc->voltages = MMC_VDD_32_33; - mci_set_mode(CONFIG_SYS_MMC_CLK_PP, mmc_blkdev.blksz); + mmc->f_min = 150000; + mmc->f_max = 5000000; -#if 0 - if (fat_register_device(&mmc_blkdev, 1)) - printf("Could not register MMC fat device\n"); -#else - init_part(&mmc_blkdev); -#endif + mmc->priv = host; + host->mmc = mmc; + mmc_register(mmc); return 0; } -- 1.6.0.4

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[U-Boot] [PATCH:v3] Support up to 7 banks for ids as specified in JEDEC JEP106Z
by Niklaus Giger 26 Aug '09

26 Aug '09

see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger <niklaus.giger(a)member.fsf.org> --- drivers/mtd/cfi_flash.c | 15 +++++++++- drivers/mtd/jedec_flash.c | 67 +++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 10 ++++++- 3 files changed, 89 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 81ac5d3..8f750cb 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -106,6 +106,8 @@ #define ATM_CMD_SOFTLOCK_START 0x80 #define ATM_CMD_LOCK_SECT 0x40 +#define FLASH_CONTINUATION_CODE 0x7F + #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -1541,13 +1543,22 @@ static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) static void cmdset_amd_read_jedec_ids(flash_info_t *info) { + ushort bankId = 0; + uchar manuId; + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); + /* JEDEC JEP106Z specifies ID codes up to bank 7 */ + while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { + bankId += 0x100; + manuId = flash_read_uchar (info, + bankId | FLASH_OFFSET_MANUFACTURER_ID); + } + info->manufacturer_id = manuId; switch (info->chipwidth){ case FLASH_CFI_8BIT: diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index e48acec..223fb71 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -68,6 +68,17 @@ #define SST39SF010A 0x00B5 #define SST39SF020A 0x00B6 +/* MXIC */ +#define MX29LV040 0x004F + +/* WINBOND */ +#define W39L040A 0x00D6 + +/* AMIC */ +#define A29L040 0x0092 + +/* EON */ +#define EN29LV040A 0x004F /* * Unlock address sets for AMD command sets. @@ -225,6 +236,62 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x10000,8), } }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = MX29LV040, + .name = "MXIC MX29LV040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)WINB_MANUFACT, + .dev_id = W39L040A, + .name = "WINBOND W39L040A", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)AMIC_MANUFACT, + .dev_id = A29L040, + .name = "AMIC A29L040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)EON_MANUFACT, + .dev_id = EN29LV040A, + .name = "EON EN29LV040A", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, #endif #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { diff --git a/include/flash.h b/include/flash.h index b016162..8feca1b 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,7 +46,7 @@ typedef struct { ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ - uchar manufacturer_id; /* manufacturer id */ + ushort manufacturer_id; /* manufacturer id */ ushort device_id; /* device id */ ushort device_id2; /* extended device id */ ushort ext_addr; /* extended query table address */ @@ -154,6 +154,7 @@ extern flash_info_t *flash_get_info(ulong base); * Device IDs */ +/* Manufacturers inside bank 0 have ids like 0x00xx00xx */ #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define ATM_MANUFACT 0x001F001F /* ATMEL */ @@ -166,6 +167,13 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ +#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ +#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 1 have ids like 0x01xx01xx */ +#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 2 have ids like 0x02xx02xx */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ -- 1.6.3.3

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[U-Boot] Please pull u-boot-ppc4xx/master
by Stefan Roese 26 Aug '09

26 Aug '09

Hi Wolfgang, please pull this fix into master. Thanks. The following changes since commit a794f59a75bf9fd4a44f1ad2349cae903c42b89c: Jean-Christophe PLAGNIOL-VILLARD (1): sh/rsk7203: add missing include net.h are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Feng Kan (1): ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driver drivers/mtd/nand/ndfc.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)

2 2

[U-Boot] Pull request - net/next
by Ben Warren 25 Aug '09

25 Aug '09

Wolfgang, The following changes since commit 307ecb6db04eebdc06b8c87d48bf48d3cbd5e9d7: Eric Millbrandt (1): Add support for USB on PSC3 for the mpc5200 are available in the git repository at: git://git.denx.de/u-boot-net.git next Alessandro Rubini (4): net: defragment IP packets tftp: get the tftp block size from config file and from the environment nfs: accept CONFIG_NFS_READ_SIZE from config file arm nomadik: activate defrag choose 4k transfer block size Ben Warren (1): Convert CS8900 Ethernet driver to CONFIG_NET_MULTI API Kim Phillips (1): net: tsec - handle user interrupt while waiting for PHY auto negotiation to complete Robin Getz (2): Add debug message for Blackfin Ethernet Rx function. Add Transfer Size Option to tftp board/altera/dk1c20/dk1c20.c | 12 ++ board/altera/dk1s10/dk1s10.c | 12 ++ board/armadillo/armadillo.c | 12 ++ board/csb226/csb226.c | 12 ++ board/ep7312/ep7312.c | 12 ++ board/freescale/mx31ads/mx31ads.c | 12 ++ board/impa7/impa7.c | 12 ++ board/lart/lart.c | 12 ++ board/mpl/vcma9/cmd_vcma9.c | 28 +++-- board/mpl/vcma9/vcma9.c | 12 ++ board/mx1ads/mx1ads.c | 12 ++ board/samsung/smdk2400/smdk2400.c | 12 ++ board/samsung/smdk2410/smdk2410.c | 12 ++ board/samsung/smdk6400/smdk6400.c | 12 ++ board/sbc2410x/sbc2410x.c | 12 ++ board/ssv/adnpesc1/adnpesc1.c | 12 ++ board/trab/trab.c | 12 ++ drivers/net/Makefile | 2 +- drivers/net/bfin_mac.c | 3 + drivers/net/cs8900.c | 276 ++++++++++++++++++++++--------------- drivers/net/cs8900.h | 41 ++++--- drivers/net/tsec.c | 7 + include/configs/ADNPESC1.h | 14 +- include/configs/DK1C20.h | 14 +- include/configs/DK1S10.h | 14 +- include/configs/VCMA9.h | 7 +- include/configs/armadillo.h | 9 +- include/configs/csb226.h | 7 +- include/configs/ep7312.h | 9 +- include/configs/impa7.h | 7 +- include/configs/lart.h | 7 +- include/configs/mx1ads.h | 7 +- include/configs/mx31ads.h | 7 +- include/configs/nhk8815.h | 4 + include/configs/sbc2410x.h | 7 +- include/configs/smdk2400.h | 7 +- include/configs/smdk2410.h | 7 +- include/configs/smdk6400.h | 7 +- include/configs/trab.h | 7 +- include/netdev.h | 1 + lib_arm/board.c | 9 -- net/net.c | 188 ++++++++++++++++++++++++- net/nfs.h | 10 +- net/tftp.c | 51 +++++++- 44 files changed, 728 insertions(+), 221 deletions(-) regards, Ben

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[U-Boot] Pull request u-boot-blackfin.git
by Mike Frysinger 25 Aug '09

25 Aug '09

The following changes since commit a794f59a75bf9fd4a44f1ad2349cae903c42b89c: Jean-Christophe PLAGNIOL-VILLARD (1): sh/rsk7203: add missing include net.h are available in the git repository at: git://www.denx.de/git/u-boot-blackfin.git master Harald Krapfenbauer (1): Blackfin: cm-bf527/cm-bf537: increase flash sectors Mike Frysinger (1): Blackfin: fix typos in gpio comments board/cm-bf527/gpio_cfi_flash.c | 6 +++--- board/cm-bf537e/gpio_cfi_flash.c | 6 +++--- board/tcm-bf537/gpio_cfi_flash.c | 6 +++--- include/configs/cm-bf527.h | 2 +- include/configs/cm-bf537e.h | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-)

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[U-Boot] [PATCH] include/s3c24x0.h: fix S3C24X0_SPI_CHANNEL declaration
by Wolfgang Denk 25 Aug '09

25 Aug '09

The SPI controller on the S3C24X0 has 8 bit registers, not 32 bit. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- include/s3c24x0.h | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-) diff --git a/include/s3c24x0.h b/include/s3c24x0.h index 71f35a5..4fa8000 100644 --- a/include/s3c24x0.h +++ b/include/s3c24x0.h @@ -550,14 +550,20 @@ typedef struct { /* SPI (see manual chapter 22) */ typedef struct { - S3C24X0_REG32 SPCON; - S3C24X0_REG32 SPSTA; - S3C24X0_REG32 SPPIN; - S3C24X0_REG32 SPPRE; - S3C24X0_REG32 SPTDAT; - S3C24X0_REG32 SPRDAT; - S3C24X0_REG32 res[2]; -} __attribute__((__packed__)) S3C24X0_SPI_CHANNEL; + S3C24X0_REG8 SPCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 SPSTA; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 SPPIN; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 SPPRE; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 SPTDAT; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 SPRDAT; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 res7[16]; +} /*__attribute__((__packed__))*/ S3C24X0_SPI_CHANNEL; typedef struct { S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS]; -- 1.6.0.6

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[U-Boot] [PATCH] net: tsec - handle user interrupt while waiting for PHY auto negotiation to complete
by Kim Phillips 25 Aug '09

25 Aug '09

if you don't have firmware installed for the PHY to come to life, this wait can be painful - let's give the option to avoid it if we want. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- drivers/net/tsec.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9c9fd37..5c3d261 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -17,6 +17,7 @@ #include <net.h> #include <command.h> #include <tsec.h> +#include <asm/errno.h> #include "miiphy.h" @@ -380,6 +381,12 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) return 0; } + if (ctrlc()) { + puts("user interrupt!\n"); + priv->link = 0; + return -EINTR; + } + if ((i++ % 1000) == 0) { putc('.'); } -- 1.6.4

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