August 2009 - U-Boot

[U-Boot] [PATCH] Support for Embedtronics/MRFSA board.
by Sami Kantoluoto 30 Aug '09

30 Aug '09

Adds support for Embedtronics Oy's MRFSA board. Board features AT91SAM9G20 controller, 64 MB of SDRAM, two 64 Mbit data flashses (AT45DB321), SD card slot, GSM modem, GPS receiver, ZigBee (CC2420), USB host ports, USB device port, two RS232 and one RS422/RS485 port, two opto isolated inputs, two relays and bunch of leds. This patch supports booting (e.g. Linux kernel) from following media/interface: - dataflash - ethernet - debug serial port - SD/MMC Signed-off-by: Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> --- Makefile | 13 + board/embedtronics/mrfsa/Makefile | 60 +++++ board/embedtronics/mrfsa/config.mk | 1 + board/embedtronics/mrfsa/iopins.h | 36 +++ board/embedtronics/mrfsa/ks8995ma.h | 255 ++++++++++++++++++ board/embedtronics/mrfsa/mrfsa.c | 481 ++++++++++++++++++++++++++++++++++ board/embedtronics/mrfsa/partition.c | 44 +++ board/embedtronics/mrfsa/watchdog.c | 62 +++++ common/console.c | 6 + cpu/arm926ejs/at91/timer.c | 7 +- drivers/net/macb.c | 4 + include/asm-arm/mach-types.h | 13 + include/configs/mrfsa.h | 197 ++++++++++++++ lib_arm/bootm.c | 13 + 14 files changed, 1191 insertions(+), 1 deletions(-) create mode 100644 board/embedtronics/mrfsa/Makefile create mode 100644 board/embedtronics/mrfsa/config.mk create mode 100644 board/embedtronics/mrfsa/iopins.h create mode 100644 board/embedtronics/mrfsa/ks8995ma.h create mode 100644 board/embedtronics/mrfsa/mrfsa.c create mode 100644 board/embedtronics/mrfsa/partition.c create mode 100644 board/embedtronics/mrfsa/watchdog.c create mode 100644 include/configs/mrfsa.h diff --git a/Makefile b/Makefile index 02393b6..b66421c 100644 --- a/Makefile +++ b/Makefile @@ -2751,6 +2751,19 @@ at91sam9g20ek_config : unconfig fi; @$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91 +mrfsa_dataflash_cs0_config \ +mrfsa_dataflash_cs1_config \ +mrfsa_config : unconfig + @mkdir -p $(obj)include + @if [ "$(findstring dataflash_cs1,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \ + else \ + echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \ + fi; + @$(MKCONFIG) -a mrfsa arm arm926ejs mrfsa embedtronics at91 + at91sam9xeek_nandflash_config \ at91sam9xeek_dataflash_cs0_config \ at91sam9xeek_dataflash_cs1_config \ diff --git a/board/embedtronics/mrfsa/Makefile b/board/embedtronics/mrfsa/Makefile new file mode 100644 index 0000000..9875638 --- /dev/null +++ b/board/embedtronics/mrfsa/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2009 +# Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> +# Embedtronics Oy <www.embedtronics.fi> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += mrfsa.o +COBJS-y += partition.o +COBJS-y += watchdog.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/embedtronics/mrfsa/config.mk b/board/embedtronics/mrfsa/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/embedtronics/mrfsa/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/embedtronics/mrfsa/iopins.h b/board/embedtronics/mrfsa/iopins.h new file mode 100644 index 0000000..e7824dd --- /dev/null +++ b/board/embedtronics/mrfsa/iopins.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _mrfsa_iopins_h +#define _mrfsa_iopins_h + +/* some output pins: */ +#define PIN_SPI0_CSZB AT91_PIN_PB31 /* ZigBee slave select */ +#define PIN_SPI0_CSETH AT91_PIN_PB30 /* ethernet switch slave select */ +#define PIN_SPI0_CSSR AT91_PIN_PB17 /* shift register slave select */ +#define PIN_RESET_OUT AT91_PIN_PC14 /* resets switch, active low */ +#define PIN_NICEDOG AT91_PIN_PC4 /* wathcdog pin, must be pulsed + * periodically */ + +#endif /* !_mrfsa_iopins_h */ diff --git a/board/embedtronics/mrfsa/ks8995ma.h b/board/embedtronics/mrfsa/ks8995ma.h new file mode 100644 index 0000000..bfc7bad --- /dev/null +++ b/board/embedtronics/mrfsa/ks8995ma.h @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _dev_spi_ks8995ma_h_ +#define _dev_spi_ks8995ma_h_ 1 + +#define KS_OK 0 +#define KS_ERROR -1 + +#define KS_RD_DATA 0x03 +#define KS_WR_DATA 0x02 + +enum { + KS_ID0 = 0, + KS_ID1, + KS_GC0, + KS_GC1, + KS_GC2, + KS_GC3, + KS_GC4, + KS_GC5, + KS_GC6, + KS_GC7, + KS_GC8, + KS_GC9, + + KS_P_CR0 = 0, + KS_P_CR1, + KS_P_CR2, + KS_P_CR3, + KS_P_CR4, + KS_P_CR5, + KS_P_CR6, + KS_P_CR7, + KS_P_CR8, + KS_P_CR9, + KS_P_CR10, + KS_P_CR11, + KS_P_CR12, + KS_P_CR13, + KS_P_SR0, + KS_P_CR14, + + KS_P1 = 16, + KS_P2 = 32, + KS_P3 = 48, + KS_P4 = 64, + KS_P5 = 80, + + KS_TOS_PCR0 = 96, + KS_TOS_PCR1, + KS_TOS_PCR2, + KS_TOS_PCR3, + KS_TOS_PCR4, + KS_TOS_PCR5, + KS_TOS_PCR6, + KS_TOS_PCR7, + + KS_TOS_MAC0, + KS_TOS_MAC1, + KS_TOS_MAC2, + KS_TOS_MAC3, + KS_TOS_MAC4, + KS_TOS_MAC5, + + KS_IAC0, + KS_IAC1, + KS_IDR8, + KS_IDR7, + KS_IDR6, + KS_IDR5, + KS_IDR4, + KS_IDR3, + KS_IDR2, + KS_IDR1, + KS_IDR0, + + KS_DTS0, + KS_DTS1, + KS_DTC0, + KS_DTC1, + KS_ATC0, + KS_ATC1, + KS_ATS, +}; + +#define KS_ID0_FAMILY_ID 0xFF + +#define KS_ID1_CHIP_ID 0xF0 +#define KS_ID1_CHIP_ID_B 4 +#define KS_ID1_REV_ID 0x0E +#define KS_ID1_START_SWITCH 0x01 + +#define KS_GC0_802_1P_PRIO 0x70 +#define KS_GC0_802_1P_PRIO_B 4 +#define KS_GC0_ENABLE_PHY_MII 0x08 +#define KS_GC0_SHARED_BUFFER 0x04 +#define KS_GC0_UNH_MODE 0x02 +#define KS_GC0_LINK_CHANGE_AGE 0x01 + +#define KS_GC1_PASS_ALL 0x80 +#define KS_GC1_PROMISCUOUS GC1_PASS_ALL +#define KS_GC1_TX_FLOW_CTL_DISABLE 0x20 +#define KS_GC1_RX_FLOW_CTL_DISABLE 0x10 +#define KS_GC1_FRAME_LENGTH_CHK 0x08 +#define KS_GC1_AGING 0x04 +#define KS_GC1_FAST_AGING 0x02 +#define KS_GC1_AGGRESSIVE_BACK_OFF 0x01 + +#define KS_GC2_UNICAST_VLAN_DISC 0x80 +#define KS_GC2_MULTICAST_STORM_DIS 0x40 +#define KS_GC2_BACK_PRESSURE_MODE 0x20 +#define KS_GC2_FAIR_MODE 0x10 +#define KS_GC2_NO_EXCESSIVE_DROP 0x08 +#define KS_GC2_HUGE_PACKET 0x04 +#define KS_GC2_DISABLE_LENGTH_CHK 0x02 +#define KS_GC2_PRIORITY_BUF 0x01 + +#define KS_GC3_802_1Q_VLAN 0x80 +#define KS_GC3_IGMP_SNOOP 0x40 +#define KS_GC3_MII_DIRECT_MODE 0x20 +#define KS_GC3_MII_PRE_TAG 0x10 +#define KS_GC3_PRIO_SCHEME_SEL 0x0C +#define KS_GC3_PRIO_SCHEME_HIGH 0x00 +#define KS_GC3_PRIO_SCHEME_10_1 0x04 +#define KS_GC3_PRIO_SCHEME_5_1 0x08 +#define KS_GC3_PRIO_SCHEME_2_1 0x0C +#define KS_GC3_TAG_MASK 0x02 +#define KS_GC3_RX_AND_TX_SNIFF 0x01 + +#define KS_GC4_MII_BACK_PRESSURE 0x80 +#define KS_GC4_MII_HALF_DUPLEX 0x40 +#define KS_GC4_MII_FLOW_ENA 0x20 +#define KS_GC4_MII_10_MBPS 0x10 +#define KS_GC4_NULL_VID_REPLACE 0x08 +#define KS_GC4_BCAST_STORM_PROT 0x07 +#define KS_GC4_BCAST_STORM_PROT_B 0 + +#define KS_GC5_BCAST_STORM_PROT 0xFF +#define KS_GC5_BCAST_STORM_PROT_B 0 + +#define KS_GC9_PHY_PWR_SAVE 0x08 +#define KS_GC9_PHY_LED_MODE 0x02 +#define KS_GC9_TPID_MODE 0x01 + +#define KS_P_CR0_BCAST_STORM_PROT_ENA 0x80 +#define KS_P_CR0_DIFFSERV_PRIO_ENA 0x40 +#define KS_P_CR0_802_1P_PRIO_ENA 0x20 +#define KS_P_CR0_CLASSIFICATION_ENA 0x10 +#define KS_P_CR0_TAG_INSERTION 0x04 +#define KS_P_CR0_TAG_REMOVAL 0x02 +#define KS_P_CR0_PRIO_ENA 0x01 + +#define KS_P_CR1_SNIFFER_PORT 0x80 +#define KS_P_CR1_RECEIVE_SNIFF 0x40 +#define KS_P_CR1_TRANSMIT_SNIFF 0x20 +#define KS_P_CR1_PORT_VLAN_MASK 0x1F + +#define KS_P_CR2_VLAN_FILTERING 0x40 +#define KS_P_CR2_DISCARD_NON_PVID 0x20 +#define KS_P_CR2_FORCE_FLOW_CTL 0x10 +#define KS_P_CR2_BACK_PRESURE_ENA 0x08 +#define KS_P_CR2_TRANSMIT_ENA 0x04 +#define KS_P_CR2_RECEIVE_ENA 0x02 +#define KS_P_CR2_LEARNING_DIS 0x01 + +#define KS_P_CR7_TX_LOW_PRIO_RATE 0xF0 +#define KS_P_CR7_TX_HIGH_PRIO_RATE 0x0F + +#define KS_P_CR10_RX_LOW_PRIO_RATE 0xF0 +#define KS_P_CR10_RX_HIGH_PRIO_RATE 0x0F + +#define KS_P_CR11_RX_DIFF_PRIO_ENA 0x80 +#define KS_P_CR11_RX_LOW_PRIO_RATE_ENA 0x40 +#define KS_P_CR11_RX_HIGH_PRIO_RATE_ENA 0x20 +#define KS_P_CR11_RX_LOW_PRIO_RATE_FLOW 0x10 +#define KS_P_CR11_RX_HIGH_PRIO_RATE_FLOW 0x08 +#define KS_P_CR11_TX_DIFF_PRIO_ENA 0x04 +#define KS_P_CR11_TX_LOW_PRIO_RATE_ENA 0x02 +#define KS_P_CR11_TX_HIGH_PRIO_RATE_ENA 0x01 + +#define KS_P_CR12_AUTO_NEG_DIS 0x80 +#define KS_P_CR12_100_MBPS 0x40 +#define KS_P_CR12_FULL_DUPLEX 0x20 +#define KS_P_CR12_ADVERTISED_FLOW_CTL 0x10 +#define KS_P_CR12_ADVERTISED_100_FD 0x08 +#define KS_P_CR12_ADVERTISED_100_HD 0x04 +#define KS_P_CR12_ADVERTISED_10_FD 0x02 +#define KS_P_CR12_ADVERTISED_10_HD 0x01 + +#define KS_P_CR13_LED_OFF 0x80 +#define KS_P_CR13_TX_DIS 0x40 +#define KS_P_CR13_RESTART_AN 0x20 +#define KS_P_CR13_FAR_END_DIS 0x10 +#define KS_P_CR13_PWR_DOWN 0x08 +#define KS_P_CR13_AUTO_MDI_MDI_X_DIS 0x04 +#define KS_P_CR13_FORCED_MDI 0x02 +#define KS_P_CR13_MAC_LOOPBACK 0x01 + +#define KS_P_PS0_MDI 0x80 +#define KS_P_PS0_AN_DONE 0x40 +#define KS_P_PS0_LINK_GOOD 0x20 +#define KS_P_PS0_PARTNER_FLOW_CTL_CAP 0x10 +#define KS_P_PS0_PARTNER_100BT_FD_CAP 0x08 +#define KS_P_PS0_PARTNER_100BT_HD_CAP 0x04 +#define KS_P_PS0_PARTNER_10BT_FD_CAP 0x02 +#define KS_P_PS0_PARTNER_10BT_HD_CAP 0x01 + +#define KS_P_CR14_PHY_LOOPBACK 0x80 +#define KS_P_CR14_REMOTE_LOOPBACK 0x40 +#define KS_P_CR14_PHY_ISOLATE 0x20 +#define KS_P_CR14_SOFT_RESET 0x10 +#define KS_P_CR14_FORCE_LINK 0x08 +#define KS_P_CR14_FAR_END_FAULT 0x01 + +#define KS_IAC0_RD 0x10 +#define KS_IAC0_TBL 0x0C +#define KS_IAC0_TBL_STATIC_MAC 0x00 +#define KS_IAC0_TBL_VLAN 0x04 +#define KS_IAC0_TBL_DYNAMIC_MAC 0x08 +#define KS_IAC0_TBL_MIB_COUNTER 0x0C +#define KS_IAC0_ADDR_HIGH 0x03 + +typedef union ks_ind_data { + u_int8_t Buf[9]; + struct { + u_int8_t _reserved[(72 - 21) / 8]; + u_int8_t Membership; +#define KS_MEMB_VALID 0x20 + u_int16_t VID; + } __attribute__ ((packed)) VLAN; +} ks_ind_data_t; + +#endif /* !_dev_spi_ks8995ma_h_ */ diff --git a/board/embedtronics/mrfsa/mrfsa.c b/board/embedtronics/mrfsa/mrfsa.c new file mode 100644 index 0000000..6420c4b --- /dev/null +++ b/board/embedtronics/mrfsa/mrfsa.c @@ -0,0 +1,481 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#if defined(CONFIG_RESET_PHY_R) || defined(CONFIG_MACB) +#include <net.h> +#include <netdev.h> +#endif + +#include "ks8995ma.h" +#include "iopins.h" + +#ifndef CONFIG_NO_VLANS +#define CONFIG_NO_VLANS 1 +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void mrfsa_serial_hw_init (void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph (AT91_PIN_PB4, 1); /* TXD0 */ + at91_set_A_periph (AT91_PIN_PB5, 0); /* RXD0 */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph (AT91_PIN_PB6, 1); /* TXD1 */ + at91_set_A_periph (AT91_PIN_PB7, 0); /* RXD1 */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph (AT91_PIN_PB8, 1); /* TXD2 */ + at91_set_A_periph (AT91_PIN_PB9, 0); /* RXD2 */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph (AT91_PIN_PB14, 0); /* DRXD */ + at91_set_A_periph (AT91_PIN_PB15, 1); /* DTXD */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +static void mrfsa_spi_hw_init (void) +{ + unsigned long mode; + + /* Enable clock for SPI */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); + + at91_set_A_periph (AT91_PIN_PA3, 1); /* SPI0_NPCS0 */ + at91_set_B_periph (AT91_PIN_PC11, 1); /* SPI0_NPCS1 */ + at91_set_gpio_output (PIN_SPI0_CSETH, 1); /* CSETH */ + at91_set_gpio_output (PIN_SPI0_CSSR, 1); /* CSSR */ + at91_set_gpio_output (PIN_SPI0_CSZB, 1); /* CSZB */ + + at91_set_A_periph (AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph (AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph (AT91_PIN_PA2, 0); /* SPI0_SPCK */ +} + +static int spi_transfer (unsigned csr, unsigned cspin, const void *src, + void *dst, int len) +{ + unsigned long mode; + unsigned int timeout; + + /* make sure SPI is not clocking data */ + writel (AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, + AT91_BASE_SPI + AT91_SPI_PTCR); + + /* select slave parameters */ + mode = readl (AT91_BASE_SPI + AT91_SPI_MR); + mode &= 0xfff0ffff; + writel (mode | (((0xf & ~(1 << csr)) << 16) & AT91_SPI_PCS), + AT91_BASE_SPI + AT91_SPI_MR); + + /* Initialize the Transmit and Receive Pointer */ + writel ((unsigned int)dst, AT91_BASE_SPI + AT91_SPI_RPR); + writel ((unsigned int)src, AT91_BASE_SPI + AT91_SPI_TPR); + + /* Initialize the Transmit and Receive Counters */ + writel (len, AT91_BASE_SPI + AT91_SPI_RCR); + writel (len, AT91_BASE_SPI + AT91_SPI_TCR); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + timeout = 0; + + /* select slave */ + at91_set_gpio_value (cspin, 0); + + /* transmit data */ + writel (AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); + while (!(readl (AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && + ((timeout = get_timer_masked ()) < CONFIG_SYS_SPI_WRITE_TOUT)) ; + writel (AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, + AT91_BASE_SPI + AT91_SPI_PTCR); + + /* deselect slave */ + at91_set_gpio_value (cspin, 1); + + /* return error on failure */ + if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) { + printf ("Error Timeout\n\r"); + return -1; + } + + /* success! */ + return 0; +} + +static int shreg_wr (unsigned sh1, unsigned sh2) +{ + unsigned char buf[2] = { sh1, sh2 }; + return spi_transfer (3, PIN_SPI0_CSSR, buf, buf, 2); +} + +#ifdef CONFIG_MACB +static void mrfsa_macb_hw_init (void) +{ + /* Enable clock */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write (AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); + + at91_sys_write (AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read (AT91_RSTC_SR) & AT91_RSTC_NRSTL)) ; + + /* Restore NRST value */ + at91_sys_write (AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | AT91_RSTC_URSTEN); + + at91_set_A_periph (AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ + at91_set_A_periph (AT91_PIN_PA17, 0); /* ERXDV */ + at91_set_A_periph (AT91_PIN_PA14, 0); /* ERX0 */ + at91_set_A_periph (AT91_PIN_PA15, 0); /* ERX1 */ + at91_set_A_periph (AT91_PIN_PA18, 0); /* ERXER */ + at91_set_A_periph (AT91_PIN_PA16, 0); /* ETXEN */ + at91_set_A_periph (AT91_PIN_PA12, 0); /* ETX0 */ + at91_set_A_periph (AT91_PIN_PA13, 0); /* ETX1 */ + at91_set_A_periph (AT91_PIN_PA21, 0); /* EMDIO */ + at91_set_A_periph (AT91_PIN_PA20, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_B_periph (AT91_PIN_PA28, 0); /* ECRS */ + at91_set_B_periph (AT91_PIN_PA29, 0); /* ECOL */ + at91_set_B_periph (AT91_PIN_PA25, 0); /* ERX2 */ + at91_set_B_periph (AT91_PIN_PA26, 0); /* ERX3 */ + at91_set_B_periph (AT91_PIN_PA27, 0); /* ERXCK */ + at91_set_B_periph (AT91_PIN_PA23, 0); /* ETX2 */ + at91_set_B_periph (AT91_PIN_PA24, 0); /* ETX3 */ + at91_set_B_periph (AT91_PIN_PA22, 0); /* ETXER */ +#endif + at91_macb_hw_init (); +} +#endif + +#ifdef CONFIG_ATMEL_MCI +static void mrfsa_mci_hw_init (void) +{ + /* Enable clock */ + at91_sys_write (AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + + /* configure I/O */ + at91_set_A_periph (AT91_PIN_PA6, 1); + at91_set_A_periph (AT91_PIN_PA7, 1); + at91_set_A_periph (AT91_PIN_PA8, 1); + at91_set_A_periph (AT91_PIN_PA9, 1); + at91_set_A_periph (AT91_PIN_PA10, 1); + at91_set_A_periph (AT91_PIN_PA11, 1); +} +#endif /* CONFIG_ATMEL_MCI */ + +void mrfsa_wdt_init (void); + +int board_init (void) +{ + at91_set_gpio_output (PIN_RESET_OUT, 1); /* reset output */ + + /* Enable Ctrlc */ + console_init_f (); + + /* arch number of MRFSA-Board */ + gd->bd->bi_arch_number = MACH_TYPE_MRFSA; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + mrfsa_serial_hw_init (); + +#ifdef CONFIG_HW_WATCHDOG + mrfsa_wdt_init (); +#endif + +#ifdef CONFIG_ATMEL_MCI + mrfsa_mci_hw_init (); +#endif + + mrfsa_spi_hw_init (); + +#ifdef CONFIG_MACB + mrfsa_macb_hw_init (); +#endif + + return 0; +} + +int board_late_init (void) +{ + /* prepare CSR(3) for shift registers */ + writel (AT91_SPI_NCPHA + | AT91_SPI_BITS_8 + | ((AT91C_MASTER_CLOCK / 10000000) << 8), + AT91_BASE_SPI + AT91_SPI_CSR (3)); + + /* set shift registers */ + shreg_wr(0xfe, 0x30); +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +static unsigned int ks_cmd (unsigned rdwr, unsigned reg, unsigned value, + unsigned *retvalue) +{ + unsigned char cmd[4] = { rdwr, reg, value }, rsp[4]; + int ret; + + ret = spi_transfer (2, PIN_SPI0_CSETH, cmd, rsp, 4); + + if (ret != 0) { + return KS_ERROR; + } + + if (retvalue) { + *retvalue = rsp[2]; + } + + return KS_OK; +} + +static unsigned int ks_write_reg (unsigned reg, unsigned value) +{ + /*printf("%s: reg=%02x, value=%02x\n", __FUNCTION__, reg, value); */ + return ks_cmd (KS_WR_DATA, reg, value, 0); +} + +static unsigned int ks_read_reg (unsigned reg, unsigned *value) +{ + int ret = ks_cmd (KS_RD_DATA, reg, 0, value); + /*printf("%s: reg=%02x, value=%02x, ret=%d\n", __FUNCTION__, reg, *value, ret); */ + return ret; +} + +#ifndef CONFIG_NO_VLANS +static unsigned int ks_ind_wr (unsigned table, unsigned addr, + const unsigned char *data, int dlen) +{ + int i, ret; + + for (ret = KS_OK, i = 9 - dlen; ret == KS_OK && (i <= 8); i++) { + ret = ks_write_reg (KS_IDR8 + i, *data++); + } + + if (ret == KS_OK) { + ret = + ks_write_reg (KS_IAC0, + (table & KS_IAC0_TBL) | ((addr >> 8) & + KS_IAC0_ADDR_HIGH)); + } + + if (ret == KS_OK) { + ret = ks_write_reg (KS_IAC1, addr & 0xff); + } + + return ret; +} + +static int ks_write_vtab (unsigned ndx, unsigned vid, unsigned fid, + unsigned members) +{ + unsigned char buf[3] = { + 0x20 | (members & 0x1F), + (fid << 4) | ((vid >> 8) & 0xF), + vid & 0xFF + }; + return ks_ind_wr (KS_IAC0_TBL_VLAN, ndx, buf, 3); +} +#endif /* !CONFIG_NO_VLANS */ + +static int ks_reset (void) +{ + static const struct { + unsigned char reg, value; + } table[] = { +#ifndef CONFIG_NO_VLANS + { + KS_GC3, KS_GC3_802_1Q_VLAN}, { + KS_GC4, KS_GC4_MII_FLOW_ENA}, { + -1, 1}, { + -1, 2}, { + -1, 3}, { + -1, 4}, { + KS_GC9, 0}, { + KS_P1 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, { + KS_P1 + KS_P_CR1, 0x10}, { + KS_P1 + KS_P_CR2, + KS_P_CR2_VLAN_FILTERING | + KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, { + KS_P1 + KS_P_CR3, 0}, { + KS_P1 + KS_P_CR4, 1}, { + KS_P2 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, { + KS_P2 + KS_P_CR1, 0x10}, { + KS_P2 + KS_P_CR2, + KS_P_CR2_VLAN_FILTERING | + KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, { + KS_P2 + KS_P_CR3, 0}, { + KS_P2 + KS_P_CR4, 2}, { + KS_P3 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, { + KS_P3 + KS_P_CR1, 0x10}, { + KS_P3 + KS_P_CR2, + KS_P_CR2_VLAN_FILTERING | + KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, { + KS_P3 + KS_P_CR3, 0}, { + KS_P3 + KS_P_CR4, 3}, { + KS_P4 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, { + KS_P4 + KS_P_CR1, 0x10}, { + KS_P4 + KS_P_CR2, + KS_P_CR2_VLAN_FILTERING | + KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, { + KS_P4 + KS_P_CR3, 0}, { + KS_P4 + KS_P_CR4, 4}, { + KS_P5 + KS_P_CR0, KS_P_CR0_TAG_INSERTION}, { + KS_P5 + KS_P_CR1, 0x0F}, { + KS_P5 + KS_P_CR2, + KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, +#else /* CONFIG_NO_VLANS */ + { + KS_GC3, 0}, { + KS_GC4, KS_GC4_MII_FLOW_ENA}, { + KS_GC9, 0}, +#if 0 /* defaults are good enough (normal switch) */ + { + KS_P1 + KS_P_CR1, 0x1F}, { + KS_P1 + KS_P_CR2, KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, + { + KS_P2 + KS_P_CR2, KS_P_CR2_LEARNING_DIS}, { + KS_P3 + KS_P_CR2, KS_P_CR2_LEARNING_DIS}, { + KS_P4 + KS_P_CR2, KS_P_CR2_LEARNING_DIS}, { + KS_P5 + KS_P_CR1, 0x01}, { + KS_P5 + KS_P_CR2, + KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, +#endif +#endif /* CONFIG_NO_VLANS */ + }; + unsigned long mode; + unsigned id0, id1; + int ret, i; + + /* Reset switch */ + at91_set_gpio_value (PIN_RESET_OUT, 0); /* enable /RESET_OUT */ + udelay (1000); /* wait a bit */ + at91_set_gpio_value (PIN_RESET_OUT, 1); /* disable /RESET_OUT */ + udelay (20000); /* wait until switch is ready */ + + /* prepare CSR(2) for ethernet switch */ + writel (AT91_SPI_NCPHA + | AT91_SPI_BITS_8 + | ((AT91C_MASTER_CLOCK / 5000000) << 8), + AT91_BASE_SPI + AT91_SPI_CSR (2)); + + /* start configuring the switch */ + if ((ret = ks_read_reg (KS_ID0, &id0)) == KS_OK + && (ret = ks_read_reg (KS_ID1, &id1)) == KS_OK) { + if (id0 == 0x95 && !(id1 & 0xF0)) { + printf ("KS8995MA detected\n"); + } else { + printf ("KS8995MA NOT detected, id0=%02x, id1=%02x\n", + id0, id1); + } + } + + /* configure.. */ + for (i = 0; ret == KS_OK && i < (sizeof (table) / sizeof (table[0])); + i++) { + if (table[i].reg != (unsigned char)-1) { + ret = ks_write_reg (table[i].reg, table[i].value); +#ifndef CONFIG_NO_VLANS + } else { + ret = + ks_write_vtab (table[i].value - 1, table[i].value, + table[i].value, + 0x10 | (1 << (table[i].value - 1))); +#endif /* !CONFIG_NO_VLANS */ + } + } + + /* and finally start the switch: */ + if (ret == KS_OK) { + ret = ks_write_reg (KS_ID1, KS_ID1_START_SWITCH); + } + + return ret; +} + +void reset_phy (void) +{ + /* configure switch */ + ks_reset (); + +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init (gd->bd); +#endif +} +#endif /* !CONFIG_NO_VLANS */ + +int board_eth_init (bd_t * bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize (0, (void *)AT91SAM9260_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/embedtronics/mrfsa/partition.c b/board/embedtronics/mrfsa/partition.c new file mode 100644 index 0000000..1f88f1b --- /dev/null +++ b/board/embedtronics/mrfsa/partition.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson <ulf(a)atmel.com> + * + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1} +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR /*SET*/, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR /*SET*/, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; diff --git a/board/embedtronics/mrfsa/watchdog.c b/board/embedtronics/mrfsa/watchdog.c new file mode 100644 index 0000000..95f5ac3 --- /dev/null +++ b/board/embedtronics/mrfsa/watchdog.c @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtroncs Oy <www.embedtronics.fi> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MRFSA board level hardware watchdog. + */ +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_wdt.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#include "iopins.h" + +static void at91_wdt_reset (void) +{ + at91_sys_write (AT91_WDT + AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); +} + +void hw_watchdog_reset (void) +{ + at91_set_gpio_value (PIN_NICEDOG, 1); + at91_wdt_reset (); + at91_set_gpio_value (PIN_NICEDOG, 0); +} + +void mrfsa_wdt_init (void) +{ + at91_wdt_reset (); + at91_sys_write (AT91_WDT + AT91_WDT_MR, + AT91_WDT_WDD | AT91_WDT_WDV | AT91_WDT_WDRSTEN | + AT91_WDT_WDRPROC | AT91_WDT_WDDBGHLT); + at91_set_gpio_output (PIN_NICEDOG, 0); + + hw_watchdog_reset (); +} + +#endif /* CONFIG_HW_WATCHDOG */ diff --git a/common/console.c b/common/console.c index 867c12c..fb6e409 100644 --- a/common/console.c +++ b/common/console.c @@ -311,6 +311,12 @@ int getc(void) int tstc(void) { +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_reset(); +#endif +#ifdef CONFIG_WATCHDOG + watchdog_reset(); +#endif #ifdef CONFIG_DISABLE_CONSOLE if (gd->flags & GD_FLG_DISABLE_CONSOLE) return 0; diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index 811bb3c..03fce54 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -83,7 +83,12 @@ int timer_init(void) unsigned long long get_ticks(void) { ulong now = READ_TIMER; - +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_reset(); +#endif +#ifdef CONFIG_WATCHDOG + watchdog_reset(); +#endif if (now >= lastinc) /* normal mode (non roll) */ /* move stamp forward with absolut diff ticks */ timestamp += (now - lastinc); diff --git a/drivers/net/macb.c b/drivers/net/macb.c index c184353..9e2e771 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -291,6 +291,7 @@ static int macb_recv(struct eth_device *netdev) return 0; } +#ifndef CONFIG_NO_PHY static void macb_phy_reset(struct macb_device *macb) { struct eth_device *netdev = &macb->netdev; @@ -403,6 +404,7 @@ static int macb_phy_init(struct macb_device *macb) return 1; } } +#endif /* CONFIG_NO_PHY */ static int macb_init(struct eth_device *netdev, bd_t *bd) { @@ -463,8 +465,10 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #endif #endif /* CONFIG_RMII */ +#ifndef CONFIG_NO_PHY if (!macb_phy_init(macb)) return -1; +#endif /* CONFIG_NO_PHY */ /* Enable TX and RX */ macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 5293d67..316c05e 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -2241,6 +2241,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP3_WL_FF 2258 #define MACH_TYPE_SIMCOM 2259 #define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_MRFSA 2295 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -28990,6 +28991,18 @@ extern unsigned int __machine_arch_type; # define machine_is_mcwebio() (0) #endif +#ifdef CONFIG_MACH_MRFSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRFSA +# endif +# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) +#else +# define machine_is_mrfsa() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/configs/mrfsa.h b/include/configs/mrfsa.h new file mode 100644 index 0000000..83ad18b --- /dev/null +++ b/include/configs/mrfsa.h @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2009 + * Sami Kantoluoto <sami.kantoluoto(a)embedtronics.fi> + * Embedtronics Oy <www.embedtronics.fi> + * + * Configuation settings for the MRFSA board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 20000000 /* 20.000 MHz crystal */ +#define AT91C_MASTER_CLOCK 133333333 /* peripheral clock */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ + +#define AT91_CPU_NAME "AT91SAM9G20" +#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC */ + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LED */ +#undef CONFIG_AT91_LED + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_MMC 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_EXT2 1 + +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CONFIG_DOS_PARTITION 1 /* support DOS partition table */ + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ +#define AT91_SPI_CLK 15000000 + +#define DATAFLASH_TCSS (0x22 << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash - no nand flash on this board */ +#ifdef CONFIG_CMD_NAND +#error No NAND FLASH +#endif +#define CONFIG_SYS_NO_NAND 1 + +/* NOR flash - no real flash on this board */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_NO_PHY 1 +#undef CONFIG_RMII +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mmcblk0p1 rootwait rw" + +#elif CONFIG_SYS_USE_DATAFLASH_CS1 + +/* bootstrap + u-boot + env + linux in dataflash on CS1 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mmcblk0p1 rootwait rw" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#define CONFIG_HW_WATCHDOG 1 /* we've hardware watchdog */ + +#define BOARD_LATE_INIT 1 +#define MMCI_BASE AT91SAM9260_BASE_MCI + +#endif diff --git a/lib_arm/bootm.c b/lib_arm/bootm.c index 128b7e3..e882d9b 100644 --- a/lib_arm/bootm.c +++ b/lib_arm/bootm.c @@ -27,6 +27,11 @@ #include <u-boot/zlib.h> #include <asm/byteorder.h> +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#include <watchdog.h> +#endif + + DECLARE_GLOBAL_DATA_PTR; #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ @@ -123,8 +128,16 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) } #endif +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + cleanup_before_linux (); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif + theKernel (0, machid, bd->bi_boot_params); /* does not return */ -- 1.6.0.4

3 5

[U-Boot] [PATCH v2] fsl: simplify the "mac id" command, improve boot-time informational message
by Timur Tabi 29 Aug '09

29 Aug '09

The "mac id" command took a 4-character parameter as the identifier string. However, for any given board, only one kind of identifier is acceptable, so it makes no sense to ask the user to type it in. Instead, if the user enters "mac id", the identifier (and also the version, if it's NXID) will automatically be set to the correct value. Improve the message that is displayed when EEPROM is read during boot. It now displays "EEPROM:" and then either an error message or the EEPROM identifier if successful. If the identifier in EEPROM is valid, then always reject a bad CRC, even if the CRC field has not been initialized. Don't force the MAC address count to MAX_NUM_PORTS or less. Forcing the value to be changed resulting in an in-memory copy that does not match what's in hardware, even though the user did not request that change. Finally, always update the CRC value in the in-memory copy after any field is changed, so that the CRC is always correct. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/common/sys_eeprom.c | 81 +++++++++++++++++++++-------------- 1 files changed, 49 insertions(+), 32 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3e1e332..c0fff68 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -186,12 +186,25 @@ static int read_eeprom(void) } /** + * update_crc - update the CRC + * + * This function should be called after each update to the EEPROM structure, + * to make sure the CRC is always correct. + */ +static void update_crc(void) +{ + u32 crc; + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + e.crc = cpu_to_be32(crc); +} + +/** * prog_eeprom - write the EEPROM from memory */ static int prog_eeprom(void) { - int ret, i, length; - unsigned int crc; + int ret, i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus; @@ -204,19 +217,16 @@ static int prog_eeprom(void) #else memset(e.res_0, 0xFF, sizeof(e.res_0)); #endif - - length = sizeof(e); - crc = crc32(0, (void *)&e, length - 4); - e.crc = cpu_to_be32(crc); + update_crc(); #ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif - for (i = 0, p = &e; i < length; i += 8, p += 8) { + for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - p, min((length - i), 8)); + p, min((sizeof(e) - i), 8)); if (ret) break; udelay(5000); /* 5ms write cycle timing */ @@ -273,6 +283,8 @@ static void set_date(const char *string) for (i = 0; i < 6; i++) e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); + + update_crc(); } /** @@ -297,11 +309,12 @@ static void set_mac_address(unsigned int index, const char *string) if (*p == ':') p++; } + + update_crc(); } int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - int i; char cmd; if (argc == 1) { @@ -316,9 +329,13 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } - if ((cmd == 'i') && (argc > 2)) { - for (i = 0; i < 4; i++) - e.id[i] = argv[2][i]; + if (cmd == 'i') { +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + memcpy(e.id, "NXID", sizeof(e.id)); + e.version = 0; +#else + memcpy(e.id, "CCID", sizeof(e.id)); +#endif return 0; } @@ -346,6 +363,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 'n': /* serial number */ memset(e.sn, 0, sizeof(e.sn)); strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); + update_crc(); break; case 'e': /* errata */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID @@ -355,12 +373,14 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) e.errata[0] = argv[2][0]; e.errata[1] = argv[2][1]; #endif + update_crc(); break; case 'd': /* date BCD format YYMMDDhhmmss */ set_date(argv[2]); break; case 'p': /* MAC table size */ e.mac_count = simple_strtoul(argv[2], NULL, 16); + update_crc(); break; case '0' ... '7': /* "mac 0" through "mac 7" */ set_mac_address(cmd - '0', argv[2]); @@ -388,6 +408,9 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int mac_read_from_eeprom(void) { unsigned int i; + u32 crc; + + puts("EEPROM: "); if (read_eeprom()) { printf("Read failed.\n"); @@ -395,31 +418,18 @@ int mac_read_from_eeprom(void) } if (!is_valid) { - printf("Invalid ID (%02x %02x %02x %02x)\n", e.id[0], e.id[1], e.id[2], e.id[3]); + printf("Invalid ID (%02x %02x %02x %02x)\n", + e.id[0], e.id[1], e.id[2], e.id[3]); return -1; } - if (be32_to_cpu(e.crc) != 0xFFFFFFFF) { - u32 crc = crc32(0, (void *)&e, sizeof(e) - 4); - - if (crc != be32_to_cpu(e.crc)) { - printf("CRC mismatch (%08x != %08x).\n", crc, - be32_to_cpu(e.crc)); - return -1; - } - } - - /* Check the number of MAC addresses which is limited to - * MAX_NUM_PORTS. - */ - if (e.mac_count > MAX_NUM_PORTS) { - printf("Warning: The number of MAC addresses is greater" - " than %u, force it to %u.\n", MAX_NUM_PORTS, - MAX_NUM_PORTS); - e.mac_count = MAX_NUM_PORTS; + crc = crc32(0, (void *)&e, sizeof(e) - 4); + if (crc != be32_to_cpu(e.crc)) { + printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc)); + return -1; } - for (i = 0; i < e.mac_count; i++) { + for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) { if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) && memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { char ethaddr[18]; @@ -441,6 +451,13 @@ int mac_read_from_eeprom(void) } } +#ifdef CONFIG_SYS_I2C_EEPROM_NXID + printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], + be32_to_cpu(e.version)); +#else + printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); +#endif + return 0; } -- 1.6.0.6

2 1

[U-Boot] Failure (read/write) in mtest
by Gurumurthy Gowdar 28 Aug '09

28 Aug '09

hi all, when i enable CFG_ALT_MEMTEST...i got following error as below. 1st Iteration:- U-Boot 1.3.1 (Jul 27 2009 - 17:27:10) MPC8260 Reset Status: External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 4, 60x Bus Freq 16-50 , Core Freq 50-150 - dfbrg 1, corecnf 0x10, busdf 4, cpmdf 1, plldf 0, pllmf 4, pcidf 3 - vco_out 500000000, scc_clk 125000000, brg_clk 31250000 - cpu_clk 300000000, cpm_clk 250000000, bus_clk 100000000 CPU: MPC8260 (HiP7 Rev 14, Mask 1.0 1K49M) at 300 MHz Board: MPC8280 Based Remote IO CARD.SLN Technologies Pvt Ltd. I2C: ready DRAM: 512 MB FLASH: 256.5 MB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: FCC2 ETHERNET RIO->mtest 0x40000 0x4ffff Testing 00040000 0004ffff Iterration: 12511 FAILURE (read/write): @0x0004e3d0: expected 0xffffc70a, actual 0xffffc72e 2nd Test Error:- RIO->mtest 0x40000 0x4ffff Testing 00040000 0004ffff Iterration: 11537 FAILURE (read/write): @0x0004e258: expected 0xffffc768, actual 0xffffc72e 3rd TEst Error:- RIO->mtest 0x40000 0x4ffff Testing 00040000 0004ffff Iterration: 11469 FAILURE (read/write): @0x0004d5c0: expected 0xffffca8e, actual 0xffffca2e after this it hangs in all above conducted test, so let me know what is the issue. this test will do integrity of the memory device as explained in the cmd_mem.c file...what does it mean. With thanks & Regards, gurumurthy On Thu, 30 Jul 2009 18:23:20 +0530 wrote > > > On Thu, 30 Jul 2009 17:50:47 +0530 wrote > >Hello GurumurthyGowdar, > > > >GurumurthyGowdar wrote: > >> On Thu, 30 Jul 2009 16:14:30 +0530 wrote > >>> Hello GurumurthyGowdar, > >>> > >>> GurumurthyGowdar wrote: > >>>> On Thu, 30 Jul 2009 12:54:31 +0530 wrote > >>>>> Hello GurumurthyGowdar, > >>>>> > >>>>> GurumurthyGowdar wrote: > >>>>>> i am using MPC8280 in our board which has 512MB of SDRAM i.e. from micron. > >>>>> Is this board in mainline, so I can look in the Source Code? > >>>> yes this board is in mainline.only one board. > >>> And which board is it? means ? it is MPC8280 based board called remote I/O board > > > >How do you compile it? > > > >make xxx_config > > > >What is xxx for you? > >I looked in code but couldn;t find a "SLN Technologies" string ... > > > >>> As I saw in your log, it uses the "normal" mtest. Try to use > >>> > >>> CONFIG_SYS_ALT_MEMTEST > >> how to use this...where to add...command for this test?? > > > >You just have to add this define in your board config file. > >I looked in 1.3.1, so you should add a > > > >#define CFG_ALT_MEMTEST 1 > i have added this line. after adding this which command i have to give..same mtest or any other command for CFG_ALT_MEMTEST ?? > > > >>> instead. (Hopefully, this is available in 1.3.1 ...) > >>> > >>>>> Which u-boot version? > >>>> U-boot version is 1.3.1. > >>> Hmm.. this is very old ... > >> which is the latest version of u-boot ,can i upgrade the current version of u-boot to latest version i.e. from u-boot 1.3.1 to latest u-boot without reinstalling ELDK > > > >http://git.denx.de/?p=u-boot.git;a=summary > > > >>>>> Which SDRAMs? > >>>> SDRAM is MT48LC32M16A2 from Micron. > >>>>>> when i give command mtest only for 1MB to check memory test from U-boot, machine check and program exception is coming after 40 - 60mins later it hangs giving program check exception > >>>>> Hmm... maybe problems with your SDRAMs? > >>>> if it is SDRAM problem it should not work for 1hour also i think. > >>> Why not? > >> ok > >>>>> Is this error shown always after 40-60 mins, not sometimes also earlier? > >>>> maximum i am able to run mtest for 1hr 30 mins. sometimes it hangs with 45mins also. > >>> Not earlier? > >> sometimes earlier but rare > >>> Hmm... > >>> > >>>>> Can you boot a Linux Kernel for example? > >>>> No. our job is to only give the board with U-boot boot loader, Linux booting is done by our client. > >>> But you can try it ... > >>> This would help here, to stress more the SDRAMs ... also you > >>> can do better memtests there/with it. > >> > >> i got one new error which is below :- > >> U-Boot 1.3.1 (Jul 27 2009 - 17:27:10) > >> > >[...] > >> DRAM: 512 MB > >> > >> it hangs here only if i press manual hardware reset many times also. > >> > >> if i power off & switch on then it reboots in normal way again. > > > >Hmm... nothing spring to my mind, just the "standard" things: > > > >check your > >- HRCW > >- clocks > >- SDRAM > >settings > > > >bye, > >Heiko > >-- > >DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > >HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > >

1 0

[U-Boot] [PATCH] Add chip select region to galaxy5200
by Eric Millbrandt 28 Aug '09

28 Aug '09

Add chip select region for an Epson S1D15313. Signed-off-by: Eric Millbrandt <emillbrandt(a)dekaresearch.com> --- include/configs/galaxy5200.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index eb2cae6..54c6b80 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -212,6 +212,11 @@ #define CONFIG_SYS_CS1_SIZE 0x90000 #define CONFIG_SYS_CS1_CFG 0x0002d900 +/* Chip Select configuration for Epson S1D13513 */ +#define CONFIG_SYS_CS3_START 0x10000000 +#define CONFIG_SYS_CS3_SIZE 0x103fffff +#define CONFIG_SYS_CS3_CFG 0xffff3d10 + /* * Ethernet configuration */ -- 1.6.3.1 http://openwebmail.org - eem

3 3

[U-Boot] RTC value corruption on QIL-A9G20 startup
by Stephen Caudle 28 Aug '09

28 Aug '09

Hello Albin, I tried using your patches for the TNY-A9G20 on my QIL-A9G20 board from Calao. Everything seems to work properly except the RTC. They use the same M41T94 part and the CS is the same on both boards (PA3). I can set the RTC using the "date" command and read back the value okay. However, when I power cycle the board, the value is getting corrupted at startup due to some erroneous SPI write. I don't believe the code you submitted is causing this problem because the RTC is getting corrupted even if I compile out SPI and RTC support completely. I was just wondering if you have seen this problem on your board? I probed the CS line with an oscilloscope and I am definitely seeing it go low on U-Boot startup for a short time, but the clock line seems to be floating. I believe the activation of the CS at startup is causing junk data to be written to the RTC, which is corrupting it. Any idea why this might be happenning? Regards, Stephen

4 8

[U-Boot] Please pull u-boot-mpc83xx.git
by Kim Phillips 28 Aug '09

28 Aug '09

Hi Wolfgang Denk, Please pull a couple of minor fix patches for the upcoming release: The following changes since commit 85f9823cd74bd2d9a7854ca0b2244e43b5214e5a: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx are available in the git repository at: git://git.denx.de/u-boot-mpc83xx.git master Kim Phillips (2): mpc83xx: match dtb filename references to their dts equivalents in the linux kernel mpc83xx: mpc8349itx - accommodate larger kernel sizes & unzero the bootdelay include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 6 +++--- include/configs/MPC8360ERDK.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) Thanks, Kim

2 1

[U-Boot] Pull request: nand flash next
by Scott Wood 28 Aug '09

28 Aug '09

The following changes since commit d7f4d14a8b317857163ccf3d97e3b1a46ba2282e: Wolfgang Denk (1): Merge branch 'next' of git://www.denx.de/git/u-boot-coldfire into next are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git next Heiko Schocher (1): 83xx, kmeter1: added NAND support Ilya Yanok (1): mxc_nand: add nand driver for MX2/MX3 Kyungmin Park (1): OneNAND: Remove unused read_spareram Matthias Kaehlcke (1): KB9202: Add NAND support Sandeep Paulraj (3): NAND: ADD page Parameter to all read_page/read_page_raw API's MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST NAND: DaVinci: V2 Adding 4 BIT ECC support drivers/mtd/nand/Makefile | 3 + drivers/mtd/nand/davinci_nand.c | 284 ++++++++++- drivers/mtd/nand/fsl_elbc_nand.c | 2 +- drivers/mtd/nand/kb9202_nand.c | 150 +++++ drivers/mtd/nand/kmeter1_nand.c | 135 +++++ drivers/mtd/nand/mxc_nand.c | 880 ++++++++++++++++++++++++++++++ drivers/mtd/nand/nand_base.c | 75 +++- drivers/mtd/onenand/onenand_base.c | 4 +- include/asm-arm/arch-davinci/emif_defs.h | 10 + include/configs/kmeter1.h | 6 + include/linux/mtd/nand.h | 5 +- include/linux/mtd/onenand.h | 3 +- 12 files changed, 1540 insertions(+), 17 deletions(-) create mode 100644 drivers/mtd/nand/kb9202_nand.c create mode 100644 drivers/mtd/nand/kmeter1_nand.c create mode 100644 drivers/mtd/nand/mxc_nand.c

2 1

Re: [U-Boot] R: R: USB EHCI driver
by Mike Timmons 27 Aug '09

27 Aug '09

All, I'm having trouble resetting my USB (virtual) root port hub following high speed handshake on the 5121e using USB0+UTMI on the mpc5121e. If anyone has any idea why root port hub reset typically fails, please advise. Thanks! Francesco, Thank you for your efforts on usb for the 5121e! I took your patch last week and applied it to u-boot-2009.06 the patch wasn't a perfect fit for some reason, but it was easy enough for me to extract the code from your patch file. What version did you intend the patch for, if not u-boot-2009.06? Regardless, I'm using a custom board based off the the ADS512101 board. I complete your initialization step and it appears I get the 5121e registers mapped correctly. "USB start" looks for devices, and I do see debug output to the console when I have a USB memory stick plugged in. I also have a USB analyzer, so I can see some action on the bus. However... It appears I am failing to reset the root port hub after the high-speed handshake between host and device (memory stick). My degree of USB ignorance is a painful limitation at this point. I'm tripping-through specs, the register set, and getting somewhat familiar with the sequencing, but I'm grinding my gears at this point. I attach a console log dump. A snippet of the log appears below, showing where/why the reset fails. I also attach a screen snap of my USB analyzer showing that some action is occurring on the wire between the host and the device (memory stick). This root port hub reset issue appears to be killing any subsequent device discovery efforts. I DID try the hack of ignoring the reset failure to see what happens. In this case I do see "2 devices" detected in the console log (root hub plus my stick I presume), but I see no additional bus traffic on the analyzer so I figure the reset failure is my smoking gun. Any ideas? console log snippet (see attached full console log dump) hub_port_reset: resetting port 0... usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 req=3 (0x3), type=35 (0x23), value=4, index=1 Len is 0 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 req=0 (0x0), type=163 (0xa3), value=0, index=1 portstatus 101, change 13, 12 Mb/s STAT_C_CONNECTION = 1 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 0 cannot reset port 1!? port 1 reset change usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 0x 0 req=1 (0x1), type=35 (0x23), value=20, index=1 Len is 0 1 USB Device(s) found scanning bus for storage devices... i=0 i=1 0 Storage Device(s) found => > On Wed, Jun 24, 2009 at 4:08 AM, Rendine Francesco <Francesco.Rendine(a)valueteam.com> wrote: >> >> Hi, >> >> thanks for your compliments, but I think that there is some work to do about this driver to support OTG mode and gadget mode. >> For now I enabled support to host mode, and from my test does it work. >> >> I'm preparing the patch, and this will carry away some days because usb u-boot source code is been re-organized.. >> I developed my patch on u-boot 2009.03, so I have to port my job on last u-boot version. >> >> Regards, >> Francesco >> >> -----Messaggio originale----- >> Da: Detlev Zundel [mailto:dzu@denx.de] >> Inviato: mer 6/24/2009 10:51 >> A: Rendine Francesco >> Cc: Michael Trimarchi; Gupta Maneesh-B18878; u-boot(a)lists.denx.de >> Oggetto: Re: [U-Boot] R: USB EHCI driver >> >> Hi Francesco, >> >> > I'm successful in provide a preliminary support to EHCI USB Freescale >> > controller integrated on ADS5121 platform. I'm preparing a patch to >> > submit to u-boot mailing list. >> >> Congratulations - I'm also looking forward to see and test the patch on >> our ads5121. >> >> Cheers >> Detlev >> >> -- >> More than any other time in history, mankind faces a crossroads. One >> path leads to despair and utter hopelessness. The other to total >> extinction. Let us pray, we have the wisdom to choose correctly. >> -- Woody Allen >> -- >> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel >> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany >> Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu(a)denx.de >> >> >> _______________________________________________ >> U-Boot mailing list >> U-Boot(a)lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot >> >

2 2

[U-Boot] problem with read only nanad
by alex889 27 Aug '09

27 Aug '09

Hi, I'm working on a system having 2 NAND chips, the first one has the U-Boot and a basic firmware, and is read only, and the second has a new firmware. when the second chip is empty, the system should boot from the first chip. but it gives me many errors, probably related to the fact that it's readonly, does the u-boot tries to write something to the nand during startup? how can i solve this issue? thanks in advance Alex -- View this message in context: http://www.nabble.com/-U-Boot--problem-with-read-only-nanad-tp25167230p2516… Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot] [RFC] OMAP3: make TWL4030 optional for MMC driver
by Matthias Ludwig 27 Aug '09

27 Aug '09

Upcoming boards may power MMC card themself without using TWL4030, so make it optional by using define CONFIG_TWL4030_MMC. Enable this for all existing OMAP3 boards. Signed-off-by: Matthias Ludwig <mludwig(a)ultratronik.de> --- Current OMAP3 MMC driver does require TWL4030 support to be enabled as all OMAP3 boards are using this chip. I'd like to push patches for a new board which does not has a TWL4030 and is caring about MMC power by itself. So, my suggestion is to make the TWL4030 dependency optional. Are there better ways to to this can using a new define CONFIG_TWL4030_MMC? drivers/mmc/omap3_mmc.c | 4 ++++ include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/omap3_pandora.h | 1 + include/configs/omap3_zoom1.h | 1 + include/configs/omap3_zoom2.h | 1 + 7 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 9e09434..0ed88cb 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -27,8 +27,10 @@ #include <fat.h> #include <mmc.h> #include <part.h> +#ifdef CONFIG_TWL4030_MMC #include <i2c.h> #include <twl4030.h> +#endif #include <asm/io.h> #include <asm/arch/mmc.h> @@ -63,7 +65,9 @@ unsigned char mmc_board_init(void) { t2_t *t2_base = (t2_t *)T2_BASE; +#ifdef CONFIG_TWL4030_MMC twl4030_power_mmc_init(); +#endif writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 61629f8..e1cb759 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -132,6 +132,7 @@ /* * TWL4030 */ +#define CONFIG_TWL4030_MMC 1 #define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 9f0f34b..b3c64a8 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -130,6 +130,7 @@ /* * TWL4030 */ +#define CONFIG_TWL4030_MMC 1 #define CONFIG_TWL4030_POWER 1 /* diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 07a031b..983832d 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -118,6 +118,7 @@ /* * TWL4030 */ +#define CONFIG_TWL4030_MMC 1 #define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 1cfd7e9..0d87c71 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -121,6 +121,7 @@ /* * TWL4030 */ +#define CONFIG_TWL4030_MMC 1 #define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 61a41e7..1140052 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -128,6 +128,7 @@ /* * TWL4030 */ +#define CONFIG_TWL4030_MMC 1 #define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 03f92f5..40add99 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -149,6 +149,7 @@ /* * TWL4030 */ +#define CONFIG_TWL4030_MMC 1 #define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 -- 1.6.2.5

3 5