August 2009 - U-Boot

[U-Boot] [PATCH v6 2/2] arm: A320: Add support for Faraday A320 evaluation board
by ratbert.chuang＠gmail.com 01 Sep '09

01 Sep '09

From: Po-Yu Chuang <ratbert(a)faraday-tech.com> This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/faraday/a320evb/Makefile | 51 ++++++++ board/faraday/a320evb/a320evb.c | 73 +++++++++++ board/faraday/a320evb/config.mk | 35 +++++ board/faraday/a320evb/lowlevel_init.S | 118 +++++++++++++++++ cpu/arm920t/a320/Makefile | 47 +++++++ cpu/arm920t/a320/ftsmc020.c | 51 ++++++++ cpu/arm920t/a320/reset.S | 22 ++++ cpu/arm920t/a320/timer.c | 193 ++++++++++++++++++++++++++++ include/asm-arm/arch-a320/a320.h | 35 +++++ include/asm-arm/arch-a320/ftpmu010.h | 190 ++++++++++++++++++++++++++++ include/asm-arm/arch-a320/ftsdmc020.h | 103 +++++++++++++++ include/asm-arm/arch-a320/ftsmc020.h | 79 ++++++++++++ include/asm-arm/arch-a320/fttmr010.h | 73 +++++++++++ include/configs/a320evb.h | 222 +++++++++++++++++++++++++++++++++ 17 files changed, 1300 insertions(+), 0 deletions(-) create mode 100644 board/faraday/a320evb/Makefile create mode 100644 board/faraday/a320evb/a320evb.c create mode 100644 board/faraday/a320evb/config.mk create mode 100644 board/faraday/a320evb/lowlevel_init.S create mode 100644 cpu/arm920t/a320/Makefile create mode 100644 cpu/arm920t/a320/ftsmc020.c create mode 100644 cpu/arm920t/a320/reset.S create mode 100644 cpu/arm920t/a320/timer.c create mode 100644 include/asm-arm/arch-a320/a320.h create mode 100644 include/asm-arm/arch-a320/ftpmu010.h create mode 100644 include/asm-arm/arch-a320/ftsdmc020.h create mode 100644 include/asm-arm/arch-a320/ftsmc020.h create mode 100644 include/asm-arm/arch-a320/fttmr010.h create mode 100644 include/configs/a320evb.h diff --git a/MAINTAINERS b/MAINTAINERS index 79873f3..aa54bdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -533,6 +533,10 @@ Rick Bronson <rick(a)efn.org> AT91RM9200DK at91rm9200 +Po-Yu Chuang <ratbert(a)faraday-tech.com> + + a320evb FA526 (ARM920T-like) (a320 SoC) + George G. Davis <gdavis(a)mvista.com> assabet SA1100 diff --git a/MAKEALL b/MAKEALL index 5882ceb..7c742b6 100755 --- a/MAKEALL +++ b/MAKEALL @@ -505,6 +505,7 @@ LIST_ARM7=" \ ######################################################################### LIST_ARM9=" \ + a320evb \ ap920t \ ap922_XA10 \ ap926ejs \ diff --git a/Makefile b/Makefile index c9d315a..a3fb0b8 100644 --- a/Makefile +++ b/Makefile @@ -2661,6 +2661,9 @@ shannon_config : unconfig ## ARM92xT Systems ######################################################################### +a320evb_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t a320evb faraday a320 + ######################################################################### ## Atmel AT91RM9200 Systems ######################################################################### diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile new file mode 100644 index 0000000..74f660d --- /dev/null +++ b/board/faraday/a320evb/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := a320evb.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c new file mode 100644 index 0000000..2aaa7a7 --- /dev/null +++ b/board/faraday/a320evb/a320evb.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <asm/arch/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + ftsmc020_init (); /* initialize Flash */ + return 0; +} + +int dram_init (void) +{ + void *sdram_base = PHYS_SDRAM_1; + unsigned long expected_size = PHYS_SDRAM_1_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size(sdram_base, expected_size); + + gd->bd->bi_dram[0].start = sdram_base; + gd->bd->bi_dram[0].size = actual_size; + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return 0; +} + +int board_eth_init (bd_t *bd) +{ + return ftmac100_initialize (bd); +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/faraday/a320evb/config.mk b/board/faraday/a320evb/config.mk new file mode 100644 index 0000000..aa25b98 --- /dev/null +++ b/board/faraday/a320evb/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2009 Faraday Technology +# Po-Yu Chuang <ratbert(a)faraday-tech.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information + +# A320 has 1 bank of 64 MB DRAM +# +# 1000'0000 to 1400'0000 +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# +# we load ourself to 13f8'0000 +# +# download area is 1200'0000 + +TEXT_BASE = 0x13f80000 diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S new file mode 100644 index 0000000..97718c0 --- /dev/null +++ b/board/faraday/a320evb/lowlevel_init.S @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <version.h> + +#include <asm/macro.h> +#include <asm/arch/ftsdmc020.h> + +/* + * parameters for the SDRAM controller + */ +#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0) +#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1) +#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR) +#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR) +#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR) + +#define TP0_D CONFIG_SYS_FTSDMC020_TP0 +#define TP1_D CONFIG_SYS_FTSDMC020_TP1 +#define CR_D1 FTSDMC020_CR_IPREC +#define CR_D2 FTSDMC020_CR_ISMR +#define CR_D3 FTSDMC020_CR_IREF + +#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(PHYS_SDRAM_1)) +#define ACR_D FTSDMC020_ACR_TOC(0x18) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + ldr r0, =CONFIG_FTSDMC020_BASE +1: + ldr r1, [r0, #FTSDMC020_OFFSET_CR] + cmp r1, #0 + bne 1b +.endm + +.globl lowlevel_init +lowlevel_init: + mov r11, lr + + led 0x0 + + bl init_sdmc + + led 0x1 + + /* everything is fine now */ + mov lr, r11 + mov pc, lr + +/* + * memory initialization + */ +init_sdmc: + led 0x10 + + /* set SDRAM register */ + + write32 TP0_A, TP0_D + led 0x11 + + write32 TP1_A, TP1_D + led 0x12 + + /* set to precharge */ + write32 CR_A, CR_D1 + led 0x13 + + wait_sdram + led 0x14 + + /* set mode register */ + write32 CR_A, CR_D2 + led 0x15 + + wait_sdram + led 0x16 + + /* set to refresh */ + write32 CR_A, CR_D3 + led 0x17 + + wait_sdram + led 0x18 + + write32 B0_BSR_A, B0_BSR_D + led 0x19 + + write32 ACR_A, ACR_D + led 0x1a + + mov pc, lr diff --git a/cpu/arm920t/a320/Makefile b/cpu/arm920t/a320/Makefile new file mode 100644 index 0000000..f030c53 --- /dev/null +++ b/cpu/arm920t/a320/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS += reset.o +COBJS += timer.o +COBJS += ftsmc020.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/a320/ftsmc020.c b/cpu/arm920t/a320/ftsmc020.c new file mode 100644 index 0000000..3d00fa8 --- /dev/null +++ b/cpu/arm920t/a320/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftsmc020.h> + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE; + +static void ftsmc020_setup_bank (unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf ("bank # %u invalid\n", bank); + return; + } + + writel (cfg->config, &smc->bank[bank].cr); + writel (cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init (void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE (config); i++) + ftsmc020_setup_bank (i, &config[i]); +} diff --git a/cpu/arm920t/a320/reset.S b/cpu/arm920t/a320/reset.S new file mode 100644 index 0000000..12ca527 --- /dev/null +++ b/cpu/arm920t/a320/reset.S @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +.global reset_cpu +reset_cpu: + b reset_cpu diff --git a/cpu/arm920t/a320/timer.c b/cpu/arm920t/a320/timer.c new file mode 100644 index 0000000..bc134b6 --- /dev/null +++ b/cpu/arm920t/a320/timer.c @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftpmu010.h> +#include <asm/arch/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; + +#define TIMER_CLOCK 32768 +#define TIMER_LOAD_VAL 0xffffffff + +int timer_init (void) +{ + unsigned int oscc; + unsigned int cr; + + debug ("%s()\n", __func__); + + /* disable timers */ + writel (0, &tmr->cr); + + /* + * use 32768Hz oscillator for RTC, WDT, TIMER + */ + + /* enable the 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel (oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl (&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc |= FTPMU010_OSCC_RTCLSEL; + writel (oscc, &pmu->OSCC); + + /* setup timer */ + writel (TIMER_LOAD_VAL, &tmr->timer3_load); + writel (TIMER_LOAD_VAL, &tmr->timer3_counter); + writel (0, &tmr->timer3_match1); + writel (0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel (FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl (&tmr->cr); + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ + cr |= FTTMR010_TM3_ENABLE; + writel (cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked (); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked (void) +{ + /* capure current decrementer value time */ + lastdec = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug ("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer (void) +{ + debug ("%s()\n", __func__); + reset_timer_masked (); +} + +/* + * return timer ticks + */ +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + debug ("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug ("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer (ulong base) +{ + debug ("%s(%lx)\n", __func__, base); + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + debug ("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&tmr->timer3_counter); + + debug ("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks (void) +{ + debug ("%s()\n", __func__); + return get_timer (0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + debug ("%s()\n", __func__); + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-a320/a320.h b/include/asm-arm/arch-a320/a320.h new file mode 100644 index 0000000..5c0a097 --- /dev/null +++ b/include/asm-arm/arch-a320/a320.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __A320_H +#define __A320_H + +/* + * Hardware register bases + */ +#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ +#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ +#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ +#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ +#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ +#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ +#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ + +#endif /* __A320_H */ + diff --git a/include/asm-arm/arch-a320/ftpmu010.h b/include/asm-arm/arch-a320/ftpmu010.h new file mode 100644 index 0000000..7044131 --- /dev/null +++ b/include/asm-arm/arch-a320/ftpmu010.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#define FTPMU010_OFFSET_IDNMBR0 0x00 +#define FTPMU010_OFFSET_OSCC 0x08 +#define FTPMU010_OFFSET_PMODE 0x0C +#define FTPMU010_OFFSET_PMCR 0x10 +#define FTPMU010_OFFSET_PED 0x14 +#define FTPMU010_OFFSET_PEDSR 0x18 +#define FTPMU010_OFFSET_PMSR 0x20 +#define FTPMU010_OFFSET_PGSR 0x24 +#define FTPMU010_OFFSET_MFPSR 0x28 +#define FTPMU010_OFFSET_MISC 0x2C +#define FTPMU010_OFFSET_PDLLCR0 0x30 +#define FTPMU010_OFFSET_PDLLCR1 0x34 +#define FTPMU010_OFFSET_AHBMCLKOFF 0x38 +#define FTPMU010_OFFSET_APBMCLKOFF 0x3C +#define FTPMU010_OFFSET_DCSRCR0 0x40 +#define FTPMU010_OFFSET_DCSRCR1 0x44 +#define FTPMU010_OFFSET_DCSRCR2 0x48 +#define FTPMU010_OFFSET_SDRAMHTC 0x4C +#define FTPMU010_OFFSET_PSPR0 0x50 +#define FTPMU010_OFFSET_PSPR1 0x54 +#define FTPMU010_OFFSET_PSPR2 0x58 +#define FTPMU010_OFFSET_PSPR3 0x5C +#define FTPMU010_OFFSET_PSPR4 0x60 +#define FTPMU010_OFFSET_PSPR5 0x64 +#define FTPMU010_OFFSET_PSPR6 0x68 +#define FTPMU010_OFFSET_PSPR7 0x6C +#define FTPMU010_OFFSET_PSPR8 0x70 +#define FTPMU010_OFFSET_PSPR9 0x74 +#define FTPMU010_OFFSET_PSPR10 0x78 +#define FTPMU010_OFFSET_PSPR11 0x7C +#define FTPMU010_OFFSET_PSPR12 0x80 +#define FTPMU010_OFFSET_PSPR13 0x84 +#define FTPMU010_OFFSET_PSPR14 0x88 +#define FTPMU010_OFFSET_PSPR15 0x8C +#define FTPMU010_OFFSET_AHBDMA_RACCS 0x90 +#define FTPMU010_OFFSET_JSS 0x9C +#define FTPMU010_OFFSET_CFC_RACC 0xA0 +#define FTPMU010_OFFSET_SSP1_RACC 0xA4 +#define FTPMU010_OFFSET_UART1TX_RACC 0xA8 +#define FTPMU010_OFFSET_UART1RX_RACC 0xAC +#define FTPMU010_OFFSET_UART2TX_RACC 0xB0 +#define FTPMU010_OFFSET_UART2RX_RACC 0xB4 +#define FTPMU010_OFFSET_SDC_RACC 0xB8 +#define FTPMU010_OFFSET_I2SAC97_RACC 0xBC +#define FTPMU010_OFFSET_IRDATX_RACC 0xC0 +#define FTPMU010_OFFSET_USBD_RACC 0xC8 +#define FTPMU010_OFFSET_IRDARX_RACC 0xCC +#define FTPMU010_OFFSET_IRDA_RACC 0xD0 +#define FTPMU010_OFFSET_ED0_RACC 0xD4 +#define FTPMU010_OFFSET_ED1_RACC 0xD8 + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_OSCC_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_PLL1NS(x) (((x) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1NS_VALUEOF(reg) (((reg) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-a320/ftsdmc020.h b/include/asm-arm/arch-a320/ftsdmc020.h new file mode 100644 index 0000000..0699772 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-a320/ftsmc020.h b/include/asm-arm/arch-a320/ftsmc020.h new file mode 100644 index 0000000..43dfa61 --- /dev/null +++ b/include/asm-arm/arch-a320/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init (void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-a320/fttmr010.h b/include/asm-arm/arch-a320/fttmr010.h new file mode 100644 index 0000000..72abcb3 --- /dev/null +++ b/include/asm-arm/arch-a320/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h new file mode 100644 index 0000000..fcc5563 --- /dev/null +++ b/include/configs/a320evb.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * Configuation settings for the Faraday A320 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/a320.h> + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ + +/*----------------------------------------------------------------------- + * Real Time Clock + */ +#define CONFIG_RTC_FTRTC010 + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x98200000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 18432000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_FTMAC100 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x12000000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x13F00000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include <asm/arch/ftsmc020.h> + +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_1M | \ + FTSMC020_BANK_MBW_8) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +/* support JEDEC */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + +#define PHYS_FLASH_1 0x00000000 +#define PHYS_FLASH_2 0x00400000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_EMPTY_INFO + +/* environments */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR 0x00060000 +#define CONFIG_ENV_SIZE 0x20000 + +#endif /* __CONFIG_H */ -- 1.6.3.3

3 3

Re: [U-Boot] [PATCH] MCI support for AT91 family processors.
by Sami Kantoluoto 01 Sep '09

01 Sep '09

On Sun, Aug 30, 2009 at 01:08:27AM +0200, Albin Tonnerre wrote: > On Sat, Aug 29, 2009 at 08:18:32PM +0300, Sami Kantoluoto wrote : > > Fixed to parse CSD correctly on little endian processors as gcc orders > > bitfields differently between big and little endian ones. > > Please also see this patch, which will fix those bugs as weel, while switching > to the new GENRIC_MMC API: > http://lists.denx.de/pipermail/u-boot/2009-August/059456.html > I'd highly appreciate if you could test it, to get some feedback Thanks, I'll test when I get some time later this week but I think (by reading the patch so I probably missed something) it won't solve the CSD problem. The real reason of the "CSD problem" of course is that how the mmc_csd structure is defined (host byte order not taken in account or at least how gcc handles bitfields). [snip] > the configuration for the MCI controller, which should be done in the > at91sam*_devices.c files. See the attached patch (relying on the patch > mentionned above) that adds such support. It's not complete yet either: it > partially lacks support for models which have 2 MCI controllers, but > that's not the case of the 9G20 anyway (that's just a matter of putting > proper ifdefs before defining AT91_BASE_MCI). > If what I've done in this patch is not the way to go, I'd appreciate > guidance on how to do it correctly. It seems ok to me except one comment about the interface: > diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h > > +void at91_mci0_hw_init(int); > +void at91_mci1_hw_init(int); I'm just wondering if the bus width should be configurable. It's probably quite unusual to use just one data bit but not impossible though. So maybe the interface call could be: void at91_mci0_hw_init(int bwForSlotA, bwForSlotB) Where the bwForSlot<X> is either 0 (which means slot is not used), 1 or 4. -sk

2 3

[U-Boot] ARM preprocessor error generating assembly dependencies
by Dirk Behme 01 Sep '09

01 Sep '09

Hi, for ARM I'm including include/asm-arm/assembler.h in an assembly file. Doing this, I get preprocessor error message include/asm/assembler.h:17:2: error: #error "Only include this from assembly code" This is due to __ASSEMBLY__ not defined, but It seems to me that this message comes from *dependency* generation, not from compilation. For compilation, -D__ASSEMBLY__ is set and it compiles fine. Doing #define __ASSEMBLY__ #include <asm/assembler.h> in assembly file fixes the error while generating dependencies, but results in __ASSEMBLY__ redefined message while compilation. Any expert here could have look to which options are taken for ARM's assembly dependency generation? It seems to me that -D__ASSEMBLY__ is missing there? Many thanks and best regards Dirk

2 8

[U-Boot] [PATCH] Add common code dir for Matrix Vision boards.
by Andre Schwarz 01 Sep '09

01 Sep '09

This fixes current build failure. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- board/matrix_vision/common/Makefile | 54 ++++++++++++++ board/matrix_vision/common/mv_common.c | 126 ++++++++++++++++++++++++++++++++ board/matrix_vision/common/mv_common.h | 25 ++++++ 3 files changed, 205 insertions(+), 0 deletions(-) create mode 100644 board/matrix_vision/common/Makefile create mode 100644 board/matrix_vision/common/mv_common.c create mode 100644 board/matrix_vision/common/mv_common.h diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile new file mode 100644 index 0000000..b496258 --- /dev/null +++ b/board/matrix_vision/common/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-y = mv_common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c new file mode 100644 index 0000000..ed23e56 --- /dev/null +++ b/board/matrix_vision/common/mv_common.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz(a)matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <environment.h> +#include <fpga.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +static char* entries_to_keep[] = { + "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt", + "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr", + "static_ipaddr", "static_netmask", "static_gateway", + "syslog", "watchdog", "netboot", "evo8serialnumber" }; + +#define MV_MAX_ENV_ENTRY_LENGTH 64 +#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) + +void mv_reset_environment(void) +{ + int i; + char *s[MV_KEEP_ENTRIES]; + char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH]; + + printf("\n*** RESET ENVIRONMENT ***\n"); + + memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH); + for (i = 0; i < MV_KEEP_ENTRIES; i++) { + s[i] = getenv(entries_to_keep[i]); + if (s[i]) { + printf("save '%s' : %s\n", entries_to_keep[i], s[i]); + strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH); + } + } + + gd->env_valid = 0; + env_relocate(); + + for (i = 0; i < MV_KEEP_ENTRIES; i++) { + if (s[i]) { + printf("restore '%s' : %s\n", entries_to_keep[i], s[i]); + setenv(entries_to_keep[i], s[i]); + } + } + + saveenv(); +} + +int mv_load_fpga(void) +{ + int result; + size_t data_size = 0; + void *fpga_data = NULL; + char *datastr = getenv("fpgadata"); + char *sizestr = getenv("fpgadatasize"); + + if (getenv("skip_fpga")) { + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); + return -1; + } + printf("loading FPGA\n"); + + if (datastr) + fpga_data = (void *)simple_strtoul(datastr, NULL, 16); + if (sizestr) + data_size = (size_t)simple_strtoul(sizestr, NULL, 16); + if (!data_size) { + printf("fpgadatasize invalid -> FPGA _not_ loaded !\n"); + return -1; + } + + result = fpga_load(0, fpga_data, data_size); + if (!result) + show_boot_progress(0); + + return result; +} + +u8 *dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + if ((ptr = getenv("dhcp_vendor-class-identifier"))) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv("dhcp_client_id"))) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} diff --git a/board/matrix_vision/common/mv_common.h b/board/matrix_vision/common/mv_common.h new file mode 100644 index 0000000..046c038 --- /dev/null +++ b/board/matrix_vision/common/mv_common.h @@ -0,0 +1,25 @@ +/* + * Copyright 2008 Matrix Vision GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +extern int mv_load_fpga(void); +extern void mv_reset_environment(void); -- 1.6.0.4 MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

3 2

[U-Boot] [PATCH] fix broken matrix vision boards
by Andre Schwarz 01 Sep '09

01 Sep '09

boards are currently broken due to missing common dir inside board dir. MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

3 9

[U-Boot] Writing files to filesystem
by Ricardo Martínez 31 Aug '09

31 Aug '09

Hi, I would like to write text files to JFFS2 filesystem from an application launched by u-boot. I mean something similar to C library functions fopen and fprintf. The purpose is programming a simple logger. I've been taking a look at the sources and I think fopen and fprintf or similars do not exist in u-boot, only printf and fprintf for stdeer, stdout & stdin. I've also found logbuff_printk, which writes string to global vector buf[1024]. Maybe this is the best approach to my requirements, not writing to filesystem, just memory storing and printing when required. Any piece of advice in order to implement that kind of easy logger would be really appreciated. Thank you very much Ricardo

2 1

[U-Boot] [STATUS] U-Boot 2009.08 Release
by Wolfgang Denk 31 Aug '09

31 Aug '09

Hi everybody, U-Boot v2009.08 has been released and is available from the git repository and the FTP server. The "next" branch has been pulled into mainline ("master" branch) and will be removed soon. The Merge Window for the next release is open until Monday, September 21, 2009, i. e. 21 days remaining. The next release is scheduled for November 18, 2009. See http://www.denx.de/wiki/U-Boot/ReleaseCycle for details, including guestimates for thenext releases after that. A little statistics [1] - changes since release v2009.06: Processed 724 csets from 96 developers 34 employers found A total of 83512 lines added, 52725 removed (delta 30787) Compare v2009.06: Processed 470 csets from 74 developers 27 employers found A total of 51824 lines added, 17041 removed (delta 34783) Developers with the most changesets Wolfgang Denk 75 (10.4%) Peter Tyser 69 (9.5%) Jean-Christophe PLAGNIOL-VILLARD 57 (7.9%) Mike Frysinger 56 (7.7%) Stefan Roese 40 (5.5%) Prafulla Wadaskar 23 (3.2%) Tom Rix 22 (3.0%) David Brownell 17 (2.3%) Kumar Gala 16 (2.2%) Matthias Fuchs 16 (2.2%) ... Developers with the most changed lines Wolfgang Denk 14835 (12.9%) Jean-Christophe PLAGNIOL-VILLARD 10512 (9.2%) Matthias Fuchs 8471 (7.4%) Mike Frysinger 6553 (5.7%) Scott Wood 5620 (4.9%) Prafulla Wadaskar 5290 (4.6%) Giuseppe Condorelli 4937 (4.3%) Stefan Roese 3988 (3.5%) Roy Zang 3515 (3.1%) Peter Tyser 2954 (2.6%) ... Developers with the most lines removed Matthias Fuchs 6924 (13.1%) Scott Wood 5607 (10.6%) Jean-Christophe PLAGNIOL-VILLARD 3606 (6.8%) Michal Simek 1024 (1.9%) Kim Phillips 927 (1.8%) Sandeep Paulraj 70 (0.1%) galak 62 (0.1%) Timur Tabi 51 (0.1%) Matthias Ludwig 29 (0.1%) Grazvydas Ignotas 16 (0.0%) ... Developers with the most signoffs (total 1047) Stefan Roese 139 (13.3%) Kumar Gala 103 (9.8%) Ben Warren 81 (7.7%) Mike Frysinger 77 (7.4%) Peter Tyser 72 (6.9%) Jean-Christophe PLAGNIOL-VILLARD 71 (6.8%) Scott Wood 45 (4.3%) Kim Phillips 39 (3.7%) Remy Bohmer 29 (2.8%) Prafulla Wadaskar 23 (2.2%) ... Developers with the most reviews (total 14) Ronen Shitrit 6 (42.9%) Angelo Castello 4 (28.6%) Alessandro Rubini 2 (14.3%) Ira W. Snyder 2 (14.3%) Developers with the most test credits (total 24) Jean-Christophe PLAGNIOL-VILLARD 4 (16.7%) Wolfgang Denk 4 (16.7%) Ira W. Snyder 2 (8.3%) Mike Frysinger 2 (8.3%) Tom Rix 2 (8.3%) Dirk Behme 2 (8.3%) Heiko Schocher 2 (8.3%) Magnus Lilja 2 (8.3%) Andrzej Wolski 2 (8.3%) Gaye Abdoulaye Walsimou 2 (8.3%) Developers who gave the most tested-by credits (total 24) Wolfgang Denk 18 (75.0%) Ben Warren 1 (4.2%) Peter Tyser 1 (4.2%) Kim Phillips 1 (4.2%) David Brownell 1 (4.2%) Bernhard Weirich 1 (4.2%) Dieter Kiermaier 1 (4.2%) Developers with the most report credits (total 2) Andrzej Wolski 2 (100.0%) Developers who gave the most report credits (total 2) Wolfgang Denk 1 (50.0%) Mike Frysinger 1 (50.0%) Top changeset contributors by employer DENX Software Engineering 140 (19.3%) (Unknown) 102 (14.1%) Extreme Engineering Solutions 70 (9.7%) Freescale 63 (8.7%) Analog Devices 62 (8.6%) jcrosoft 57 (7.9%) Wind River 25 (3.5%) Marvell 23 (3.2%) ESD Electronics 20 (2.8%) EmCraft Systems 8 (1.1%) ... Top lines changed by employer DENX Software Engineering 21436 (18.7%) jcrosoft 14682 (12.8%) Freescale 13641 (11.9%) ESD Electronics 12184 (10.6%) (Unknown) 10998 (9.6%) Analog Devices 9980 (8.7%) Marvell 5290 (4.6%) ST Microelectronics 4937 (4.3%) Extreme Engineering Solutions 4350 (3.8%) EmCraft Systems 2851 (2.5%) ... Employers with the most signoffs (total 1047) Freescale 222 (21.2%) DENX Software Engineering 185 (17.7%) (Unknown) 180 (17.2%) Analog Devices 82 (7.8%) Extreme Engineering Solutions 75 (7.2%) jcrosoft 71 (6.8%) Oce Technologies 29 (2.8%) Marvell 25 (2.4%) Wind River 25 (2.4%) ESD Electronics 20 (1.9%) ... [1] See http://www.denx.de/wiki/U-Boot/UbootStat_2009_08 for full statistics, and http://www.denx.de/wiki/UBoot/ReleaseCycle for links to statistics for earlier releases. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de There is a biblical analogy I'd like to draw here. Casts are to C++ Programmers what the apple was to Eve. - Scott Douglas Meyers

1 0

[U-Boot] mx27 ethernet support
by Johann Steinbrecher 31 Aug '09

31 Aug '09

Hello, is there aan ethernet support for the imx27 processor. Where can I get the required patches? Greetings Johann

2 1

[U-Boot] [PATCH 2/3] Reset interrupted i2c slaves (galaxy5200)
by Eric Millbrandt 31 Aug '09

31 Aug '09

Reset any i2c devices that may have been interrupted by a system reset. Normally this would be accomplished by clocking the line until SCL and SDA are released and then sending a start condtiion (From an Atmel datasheet). But since there is only write access to these lines on the MPC5200 we can only attempt to reset any slave devices by sending more start commands than bits the slave is attempting to transmit. Signed-off-by: Eric Millbrandt <emillbrandt(a)dekaresearch.com> --- Some whitespace cleanup and typos are included in this patch board/galaxy5200/galaxy5200.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/configs/galaxy5200.h | 9 +++++---- 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c index 5aa9d3a..c38e7de 100644 --- a/board/galaxy5200/galaxy5200.c +++ b/board/galaxy5200/galaxy5200.c @@ -155,6 +155,47 @@ phys_size_t initdram(int board_type) return dramsize + dramsize2; } +/* + * Reset any i2c devices that may have been interrupted by a system reset. + * Normally this would be accomplished by clocking the line until SCL and SDA + * are released and then sending a start condtiion (From an Atmel datasheet). + * But since there is only write access to these lines on the MPC5200 we can + * only attempt to reset any slave devices by sending more start commands than + * bits the slave is attempting to transmit. + */ +int misc_init_f(void) +{ + volatile struct mpc5xxx_gpio *gpio = + (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + int i; + u16 state; + + state = gpio->outo_gpioe; + + /* Enable gpio on i2c1 and i2c2 */ + gpio->outo_gpioe |= 0xf; + + /* + * Send an i2c start command 16 times to reset the state machines on + * any slave devices transmitting on the bus. + */ + for (i = 0; i < 16; i++) { + gpio->outo_dvo = 0x5; + udelay(5); + gpio->outo_dvo |= 0xa; + udelay(5); + gpio->outo_dvo &= 0xa; + udelay(5); + gpio->outo_dvo = 0x0; + udelay(5); + } + + /* Return control of i2c1 and i2c2 */ + gpio->outo_gpioe = state; + + return 0; +} + int checkboard(void) { puts("Board: galaxy5200\n"); diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index e9a4569..eb2cae6 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -81,8 +81,8 @@ #endif /* RAMBOOT will be defined automatically in memory section */ -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" /* @@ -94,7 +94,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_PREBOOT "echo;" \ - "echo Welcome to U-Boot"\ + "echo Welcome to U-Boot;"\ "echo" /* @@ -110,6 +110,7 @@ #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_MISC_INIT_F 1 /* Reset i2c busses */ /* * EEPROM CAT24WC32 configuration @@ -376,7 +377,7 @@ #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 /* * USB settings -- 1.6.3.1

4 5

[U-Boot] [Fwd: Re: mpc8315 DDR2 controller]
by Marcos Cunha 31 Aug '09

31 Aug '09

Dears, I found the problem. The reference board (MPC8315ERDB) has 128MB DDR2. The new design has 256MB DDR2. I chanced the size macros in \incluce\configs\MPC8315E.h #define CFG_DDR_SIZE 256 /* MB */ #define CFG_DDR_CS0_BNDS 0x0000000F But I forgot change MMU configurations. Below the correct configuration. #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M| BATU_VS | BATU_VP) Thanks, Marcos Cunha Electrical Engineer Wolfgang Denk wrote: > Dear Marcos Cunha, > > In message <4A944EE0.1000700(a)atlantico.com.br> you wrote: > >> I am using u-boot 1.2.0 for mpc8315e processor with BDI2000 debugger in >> a new design based on MPC8315ERDB. Our board has a different DDR2 and >> Flash memory. The flash memory works fine. The problem could be DDR2. >> > > U-Boot 1.2.0 is more than 2 years old. > > You really should not use such ancient stuff for a new design. > > You get the expected reply: please update, use current code and try > again. If the problem still persists, please report back. > > Best regards, > > Wolfgang Denk > > -- cid:image002.gif@01C8B04F.DE139770 *Marcos Aurélio pinto cunha, PMP Engenheiro eletricista / electrical engineer *** cid:image002.gif@01C8B04F.DE139770 cid:image003.gif@01C8B04F.DE139770 Fone: +55 (85) 3216.7934 Fax: +55 (85) 3216.7864 Skype: marcos.cunha.ufc *ISO 9001 : 2000 - CMMI3*** *www.atlantico.com.br <http://www.atlantico.com.br>*** -- cid:image002.gif@01C8B04F.DE139770 *Marcos Aurélio pinto cunha, PMP Engenheiro eletricista / electrical engineer *** cid:image002.gif@01C8B04F.DE139770 cid:image003.gif@01C8B04F.DE139770 Fone: +55 (85) 3216.7934 Fax: +55 (85) 3216.7864 Skype: marcos.cunha.ufc *ISO 9001 : 2000 - CMMI3*** *www.atlantico.com.br <http://www.atlantico.com.br>***

1 0