October 2007 - U-Boot

[U-Boot-Users] [PATCH] ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite
by Stefan Roese 15 Oct '07

15 Oct '07

The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/sequoia/sequoia.c | 7 ++++--- board/amcc/yosemite/yosemite.c | 7 +++++-- include/configs/sequoia.h | 2 ++ include/configs/yosemite.h | 2 ++ 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index f823117..4e47ab3 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * (C) Copyright 2006 @@ -24,6 +24,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <ppc440.h> DECLARE_GLOBAL_DATA_PTR; @@ -362,8 +363,8 @@ int checkboard(void) printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif - rev = in8(CFG_BCSR_BASE + 0); - val = in8(CFG_BCSR_BASE + 5) & 0x01; + rev = in_8((void *)(CFG_BCSR_BASE + 0)); + val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 912f09e..6ec922a 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -22,6 +24,7 @@ #include <common.h> #include <ppc4xx.h> #include <asm/processor.h> +#include <asm/io.h> #include <spd_sdram.h> DECLARE_GLOBAL_DATA_PTR; @@ -181,8 +184,8 @@ int checkboard(void) printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); #endif - rev = *(u8 *)(CFG_CPLD + 0); - val = *(u8 *)(CFG_CPLD + 5) & 0x01; + rev = in_8((void *)(CFG_BCSR_BASE + 0)); + val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index c2e1386..600f98c 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -450,6 +450,8 @@ #define CFG_EBC_PB2AP 0x24814580 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) +#define CFG_BCSR5_PCI66EN 0x80 + /*----------------------------------------------------------------------- * NAND FLASH *----------------------------------------------------------------------*/ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 6a5b7f1..35bce4a 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -359,6 +359,8 @@ #define CFG_EBC_PB2AP 0x04814500 #define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) +#define CFG_BCSR5_PCI66EN 0x80 + /*----------------------------------------------------------------------- * Cache Configuration */ -- 1.5.3.4

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[U-Boot-Users] USB OHCI issue
by Matthias Fuchs 15 Oct '07

15 Oct '07

Hi everybody, I am currently playing around with U-Boot's (PCI) OHCI driver on a 405 board. U-Boot's USB stuff is running fine on this board. I can read files from an USB stick without any problems. But when I start Linux with a (rather old) 2.4.21 kernel, the still connected USB stick is not detected as storage device. I have two ways to get USB working under this Linux kernel: a) I do not start the USB subsystem at the U-Boot prompt ('usb start') b) I disconnect and reconnect the USB stick when Linux is running. Both options are not really what I want. Calling 'usb stop' before booting Linux does not help. I am not sure if this is a Linux or U-Boot issue. Perhaps a newer kernel does not show this issue, but upgrading is currently not an option:-) Can anybody verify this behavior with other 2.4.x kernels? Regards Matthias

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[U-Boot-Users] U-Boot-1.1.6-How to enable Disk On Chip?
by Binay Kumar 15 Oct '07

15 Oct '07

Hi, I cross-compiled u-boot-1.1.6 with patch for BMW board(MPC-8245) as well as Montavista Kernel(linux 2.6.10_mv1401).Both running fine on board. Now I want to "Enable DiskOn Chip" ,because according to documents stating that It's having 2MB SHADOW FLASH,so where I can make change so that it will display "DiskOnChip". NOTE:Presentally showing No DiskOnChip found. ----------------Message------------------- U-Boot 1.1.6 (Oct 4 2007 - 17:24:54) CPU: MPC8245 Revision 1.4 at 198.002 MHz: 16 kB I-Cache 16 kB D-Cache Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B) HELLO BINAY........ Built: Oct 4 2007 at 17:24:57 Local Bus at 99.001 MHz DRAM: 256 MB FLASH: 512 kB In: serial Out: serial Err: serial DOC: No DiskOnChip found Thanks In Advance Binay

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[U-Boot-Users] Unexpected bahavior with Intel Strata flashes
by Matthias Fuchs 15 Oct '07

15 Oct '07

Hi, I ran into an issue with some ugly Intel Strata J3 flashes. The U-boot target has two of those flash chips onboard. U-boot uses the CFI driver with CFG_FLASH_PROTECTION enabled. These ugly flashes support setting single lock bits per sector, but only completely clearing them for the whole chip. With U-boot's protect command I can protect single sectors as expected. But clearing the protection also works per sector as it can be seen through the flinfo command. I did not expect this! Does U-Boot unprotect the complete chip and then 're-'protect all sectors that should be kept protected? This would make sense, but is this really what is done? Regards Matthias

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[U-Boot-Users] hipments
by Ange PREST 15 Oct '07

15 Oct '07

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[U-Boot-Users] difference between _f and _r init functions
by Mike Frysinger 15 Oct '07

15 Oct '07

cant seem to find any explicit mention of the difference between _f and _r functions ... looks like _f funcs are called "early" and _r funcs are the later stuff which do more. what's the letter stand for and generally what should these be doing ? -mike

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[U-Boot-Users] [PATCH 2/2] fix pxa255_idp board
by Marcel Ziswiler 15 Oct '07

15 Oct '07

Yes, I know it's big, but that's mainly to do with the rename of memsetup to lowlevel_init adding 14 KB twice. Shouldn't there be a smarter way for renames in patches? Signed-off-by: Marcel Ziswiler <marcel <at> ziswiler.com> --- diff --git a/board/pxa255_idp/memsetup.S b/board/pxa255_idp/memsetup.S deleted file mode 100644 index 7e485a2..0000000 --- a/board/pxa255_idp/memsetup.S +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/memsetup.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/pxa-regs.h> - -DRAM_SIZE: .long CFG_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -/* - * Memory setup - */ -.globl memsetup -memsetup: - - mov r10, lr - -#ifdef DEBUG_BLINK_ENABLE - /* 3rd blink */ - bl blink -#endif - - /* Set up GPIO pins first ----------------------------------------- */ - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - -#ifdef DEBUG_BLINK_ENABLE - /* 4th debug blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - -#ifdef DEBUG_BLINK_ENABLE - /* 5th blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* set MDREFR according to user define with exception of a few bits */ - - ldr r4, =CFG_MDREFR_VAL - orr r4, r4, #(MDREFR_SLFRSH) - bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ - - ldr r4, =CFG_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - ldr r3, =CFG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CFG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ -#if 0 - /* FIXME turn on serial ports */ - /* look into moving this to board_init() */ - ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) - mov r3, #0x13 - str r3, [r2] -#endif - -#ifdef DEBUG_BLINK_ENABLE - /* 6th blink */ - bl blink -#endif - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ -#if 0 - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - -#endif - -#ifdef RTC - /* enable the 32Khz oscillator for RTC and PowerManager */ - - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b -#endif - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#define NODEBUG -#ifdef NODEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End memsetup */ - /* ---------------------------------------------------------------- */ - -#ifdef DEBUG_BLINK_ENABLE - /* 7th blink */ - bl blink -#endif - -endmemsetup: - - mov pc, r10 - - -#ifdef DEBUG_BLINK_ENABLE - -/* debug LED code */ - -/* delay about 200ms */ -delay: - - /* reset OSCR to 0 */ - ldr r8, =OSCR - mov r9, #0 - str r9, [r8] - - /* make sure new value has stuck */ -1: - ldr r8, =OSCR - ldr r9, [r8] - mov r8, #0x10000 - cmp r9, r8 - bgt 1b - - /* now, wait for delay to expire */ -1: - ldr r8, =OSCR - ldr r9, [r8] - mov r8, #0xd4000 - cmp r8, r9 - bgt 1b - - mov pc, lr - -/* blink code -- trashes r7, r8, r9 */ - -.globl blink -blink: - - mov r7, lr - - /* set GPIO10 as outout */ - ldr r8, =GPDR0 - ldr r9, [r8] - orr r9, r9, #(1<<10) - str r9, [r8] - - /* turn LED off */ - mov r9, #(1<<10) - ldr r8, =GPCR0 - str r9, [r8] - bl delay - - /* turn LED on */ - mov r9, #(1<<10) - ldr r8, =GPSR0 - str r9, [r8] - bl delay - - /* turn LED off */ - mov r9, #(1<<10) - ldr r8, =GPCR0 - str r9, [r8] - - mov pc, r7 - -#endif diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds index 20ce108..2facd83 100644 --- a/board/pxa255_idp/u-boot.lds +++ b/board/pxa255_idp/u-boot.lds @@ -44,6 +44,7 @@ SECTIONS . = ALIGN(4); .got : { *(.got) } + . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index fb810ca..f0b86b7 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -25,8 +25,7 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ -msoft-float -#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 -PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale +PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale # ========================================================================= # # Supply options according to compiler version diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index 51e7f65..9ba457e 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -35,17 +35,17 @@ DECLARE_GLOBAL_DATA_PTR; -#define FFUART 0 -#define BTUART 1 -#define STUART 2 +#define FFUART_INDEX 0 +#define BTUART_INDEX 1 +#define STUART_INDEX 2 #ifndef CONFIG_SERIAL_MULTI #if defined (CONFIG_FFUART) -#define UART_INDEX FFUART +#define UART_INDEX FFUART_INDEX #elif defined (CONFIG_BTUART) -#define UART_INDEX BTUART +#define UART_INDEX BTUART_INDEX #elif defined (CONFIG_STUART) -#define UART_INDEX STUART +#define UART_INDEX STUART_INDEX #else #error "Bad: you didn't configure serial ..." #endif @@ -71,7 +71,7 @@ void pxa_setbrg_dev (unsigned int uart_index) hang (); switch (uart_index) { - case FFUART: + case FFUART_INDEX: #ifdef CONFIG_CPU_MONAHANS CKENA |= CKENA_22_FFUART; #else @@ -90,7 +90,7 @@ void pxa_setbrg_dev (unsigned int uart_index) FFIER = IER_UUE; /* Enable FFUART */ break; - case BTUART: + case BTUART_INDEX: #ifdef CONFIG_CPU_MONAHANS CKENA |= CKENA_21_BTUART; #else @@ -110,7 +110,7 @@ void pxa_setbrg_dev (unsigned int uart_index) break; - case STUART: + case STUART_INDEX: #ifdef CONFIG_CPU_MONAHANS CKENA |= CKENA_23_STUART; #else @@ -154,20 +154,20 @@ int pxa_init_dev (unsigned int uart_index) void pxa_putc_dev (unsigned int uart_index,const char c) { switch (uart_index) { - case FFUART: + case FFUART_INDEX: /* wait for room in the tx FIFO on FFUART */ while ((FFLSR & LSR_TEMT) == 0) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ FFTHR = c; break; - case BTUART: + case BTUART_INDEX: while ((BTLSR & LSR_TEMT ) == 0 ) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ BTTHR = c; break; - case STUART: + case STUART_INDEX: while ((STLSR & LSR_TEMT ) == 0 ) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ STTHR = c; @@ -187,11 +187,11 @@ void pxa_putc_dev (unsigned int uart_index,const char c) int pxa_tstc_dev (unsigned int uart_index) { switch (uart_index) { - case FFUART: + case FFUART_INDEX: return FFLSR & LSR_DR; - case BTUART: + case BTUART_INDEX: return BTLSR & LSR_DR; - case STUART: + case STUART_INDEX: return STLSR & LSR_DR; } return -1; @@ -205,16 +205,16 @@ int pxa_tstc_dev (unsigned int uart_index) int pxa_getc_dev (unsigned int uart_index) { switch (uart_index) { - case FFUART: + case FFUART_INDEX: while (!(FFLSR & LSR_DR)) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ return (char) FFRBR & 0xff; - case BTUART: + case BTUART_INDEX: while (!(BTLSR & LSR_DR)) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ return (char) BTRBR & 0xff; - case STUART: + case STUART_INDEX: while (!(STLSR & LSR_DR)) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ return (char) STRBR & 0xff; @@ -233,32 +233,32 @@ pxa_puts_dev (unsigned int uart_index,const char *s) #if defined (CONFIG_FFUART) static int ffuart_init(void) { - return pxa_init_dev(FFUART); + return pxa_init_dev(FFUART_INDEX); } static void ffuart_setbrg(void) { - return pxa_setbrg_dev(FFUART); + return pxa_setbrg_dev(FFUART_INDEX); } static void ffuart_putc(const char c) { - return pxa_putc_dev(FFUART,c); + return pxa_putc_dev(FFUART_INDEX,c); } static void ffuart_puts(const char *s) { - return pxa_puts_dev(FFUART,s); + return pxa_puts_dev(FFUART_INDEX,s); } static int ffuart_getc(void) { - return pxa_getc_dev(FFUART); + return pxa_getc_dev(FFUART_INDEX); } static int ffuart_tstc(void) { - return pxa_tstc_dev(FFUART); + return pxa_tstc_dev(FFUART_INDEX); } struct serial_device serial_ffuart_device = @@ -277,32 +277,32 @@ struct serial_device serial_ffuart_device = #if defined (CONFIG_BTUART) static int btuart_init(void) { - return pxa_init_dev(BTUART); + return pxa_init_dev(BTUART_INDEX); } static void btuart_setbrg(void) { - return pxa_setbrg_dev(BTUART); + return pxa_setbrg_dev(BTUART_INDEX); } static void btuart_putc(const char c) { - return pxa_putc_dev(BTUART,c); + return pxa_putc_dev(BTUART_INDEX,c); } static void btuart_puts(const char *s) { - return pxa_puts_dev(BTUART,s); + return pxa_puts_dev(BTUART_INDEX,s); } static int btuart_getc(void) { - return pxa_getc_dev(BTUART); + return pxa_getc_dev(BTUART_INDEX); } static int btuart_tstc(void) { - return pxa_tstc_dev(BTUART); + return pxa_tstc_dev(BTUART_INDEX); } struct serial_device serial_btuart_device = @@ -321,32 +321,32 @@ struct serial_device serial_btuart_device = #if defined (CONFIG_STUART) static int stuart_init(void) { - return pxa_init_dev(STUART); + return pxa_init_dev(STUART_INDEX); } static void stuart_setbrg(void) { - return pxa_setbrg_dev(STUART); + return pxa_setbrg_dev(STUART_INDEX); } static void stuart_putc(const char c) { - return pxa_putc_dev(STUART,c); + return pxa_putc_dev(STUART_INDEX,c); } static void stuart_puts(const char *s) { - return pxa_puts_dev(STUART,s); + return pxa_puts_dev(STUART_INDEX,s); } static int stuart_getc(void) { - return pxa_getc_dev(STUART); + return pxa_getc_dev(STUART_INDEX); } static int stuart_tstc(void) { - return pxa_tstc_dev(STUART); + return pxa_tstc_dev(STUART_INDEX); } struct serial_device serial_stuart_device = diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index ffaa30f..b922485 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -166,13 +166,17 @@ _start_armboot: .word start_armboot /* */ /****************************************************************************/ /* mk@tbd: Fix this! */ -#ifdef CONFIG_CPU_MONAHANS +#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS) #undef ICMR #undef OSMR3 #undef OSCR #undef OWER #undef OIER #endif +#ifdef CONFIG_PXA250 +#undef RCSR +#undef CCCR +#endif /* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 0e884fc..4a9cadb 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -38,10 +38,11 @@ #include <asm/arch/pxa-regs.h> /* - * If we are developing, we might want to start armboot from ram + * If we are developing, we might want to start U-Boot from RAM * so we MUST NOT initialize critical regs like mem-timing ... */ -#define CONFIG_INIT_CRITICAL /* undef for developing */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ +#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */ /* * define the following to enable debug blinks. A debug blink function @@ -62,6 +63,7 @@ #endif #define CONFIG_MMC 1 +#define CONFIG_DOS_PARTITION 1 #define BOARD_LATE_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -121,7 +123,6 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_DHCP - #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "bootm 40000" #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" @@ -332,7 +333,7 @@ #define CFG_FLASH_CFI_DRIVER 1 #define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN 0x40000 +#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ @@ -347,7 +348,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* Addr of Environment Sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) -#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 +#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16) #endif /* __CONFIG_H */ diff --git a/include/part.h b/include/part.h index 29c0320..37b2b68 100644 --- a/include/part.h +++ b/include/part.h @@ -38,9 +38,9 @@ typedef struct block_dev_desc { #endif lbaint_t lba; /* number of blocks */ unsigned long blksz; /* block size */ - unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */ - unsigned char product[20+1]; /* IDE Serial no, SCSI product */ - unsigned char revision[8+1]; /* firmware revision */ + char vendor [40+1]; /* IDE model, SCSI Vendor */ + char product[20+1]; /* IDE Serial no, SCSI product */ + char revision[8+1]; /* firmware revision */ unsigned long (*block_read)(int dev, unsigned long start, lbaint_t blkcnt, --

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[U-Boot-Users] [PATCH 1/2] fix pxa255_idp board
by Marcel Ziswiler 15 Oct '07

15 Oct '07

The pxa255_idp being an old unmaintained board showed several issues: 1. CONFIG_INIT_CRITICAL was still defined. 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. 3. Symbol flash_addr was undeclared. 4. The boards lowlevel_init function was still called memsetup. 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. 6. Using -march=armv5 instead of -march=armv5te resulted in lots of 'target CPU does not support interworking' warnings on recent compilers. 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as indexes rather than the register definitions from the pxa-regs header file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to avoid any ambiguities. 8. There were several redefinition warnings concerning ICMR, OSMR3, OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. 9. The board configuration file was rather outdated. 10. The part header file defined the vendor, product and revision arrays as unsigned chars instead of just chars in the block_dev_desc_t structure. Signed-off-by: Marcel Ziswiler <marcel <at> ziswiler.com> --- board/pxa255_idp/Makefile | 2 +- board/pxa255_idp/config.mk | 2 +- board/pxa255_idp/lowlevel_init.S | 496 ++++++++++++++++++++++++++++++++++++++ board/pxa255_idp/memsetup.S | 496 -------------------------------------- board/pxa255_idp/u-boot.lds | 1 + cpu/pxa/config.mk | 3 +- cpu/pxa/serial.c | 72 +++--- cpu/pxa/start.S | 6 +- include/configs/pxa255_idp.h | 13 +- include/part.h | 6 +- 10 files changed, 551 insertions(+), 546 deletions(-) diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile index a957dd3..32399f0 100644 --- a/board/pxa255_idp/Makefile +++ b/board/pxa255_idp/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS := pxa_idp.o -SOBJS := memsetup.o +SOBJS := lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk index d2a2040..55c8b27 100644 --- a/board/pxa255_idp/config.mk +++ b/board/pxa255_idp/config.mk @@ -1,3 +1,3 @@ #TEXT_BASE = 0xa1700000 -TEXT_BASE = 0xa3000000 +TEXT_BASE = 0xa3080000 #TEXT_BASE = 0 diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S new file mode 100644 index 0000000..aaa4d8e --- /dev/null +++ b/board/pxa255_idp/lowlevel_init.S @@ -0,0 +1,496 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +/* + * Memory setup + */ +.globl lowlevel_init +lowlevel_init: + + mov r10, lr + +#ifdef DEBUG_BLINK_ENABLE + /* 3rd blink */ + bl blink +#endif + + /* Set up GPIO pins first ----------------------------------------- */ + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +#ifdef DEBUG_BLINK_ENABLE + /* 4th debug blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + +#ifdef DEBUG_BLINK_ENABLE + /* 5th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* set MDREFR according to user define with exception of a few bits */ + + ldr r4, =CFG_MDREFR_VAL + orr r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ +#if 0 + /* FIXME turn on serial ports */ + /* look into moving this to board_init() */ + ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) + mov r3, #0x13 + str r3, [r2] +#endif + +#ifdef DEBUG_BLINK_ENABLE + /* 6th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ +#if 0 + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#endif + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End memsetup */ + /* ---------------------------------------------------------------- */ + +#ifdef DEBUG_BLINK_ENABLE + /* 7th blink */ + bl blink +#endif + +endlowlevel_init: + + mov pc, r10 + + +#ifdef DEBUG_BLINK_ENABLE + +/* debug LED code */ + +/* delay about 200ms */ +delay: + + /* reset OSCR to 0 */ + ldr r8, =OSCR + mov r9, #0 + str r9, [r8] + + /* make sure new value has stuck */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0x10000 + cmp r9, r8 + bgt 1b + + /* now, wait for delay to expire */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0xd4000 + cmp r8, r9 + bgt 1b + + mov pc, lr + +/* blink code -- trashes r7, r8, r9 */ + +.globl blink +blink: + + mov r7, lr + + /* set GPIO10 as outout */ + ldr r8, =GPDR0 + ldr r9, [r8] + orr r9, r9, #(1<<10) + str r9, [r8] + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + bl delay + + /* turn LED on */ + mov r9, #(1<<10) + ldr r8, =GPSR0 + str r9, [r8] + bl delay + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + + mov pc, r7 + +#endif --

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[U-Boot-Users] Pull request: u-boot-freebsd
by Rafal Jaworowski 15 Oct '07

15 Oct '07

The following changes since commit 636400198228d96983c06657b17f760f5989958e: Wolfgang Denk (1): Prepare for 1.3.0-rc3 release are available in the git repository at: git://www.denx.de/git/u-boot-freebsd.git master Rafal Jaworowski (5): [Net] Introduce standalone eth_receive() routine [POWERPC] Simplify bd_info struct Globalize envmatch() so it can be accessed from other U-Boot subsystems API for external applications Style cleanups Makefile | 7 +- api/Makefile | 40 +++ api/README | 55 ++++ api/api.c | 670 ++++++++++++++++++++++++++++++++++++++++++ api/api_net.c | 114 +++++++ api/api_platform.c | 74 +++++ api/api_storage.c | 370 +++++++++++++++++++++++ api_examples/Makefile | 103 +++++++ api_examples/crt0.S | 49 +++ api_examples/demo.c | 294 ++++++++++++++++++ api_examples/glue.c | 460 +++++++++++++++++++++++++++++ api_examples/libgenwrap.c | 96 ++++++ common/cmd_nvedit.c | 5 +- include/api_public.h | 102 +++++++ include/asm-ppc/u-boot.h | 17 +- include/common.h | 3 + include/configs/MPC8555CDS.h | 4 + include/net.h | 1 + lib_ppc/board.c | 5 + net/eth.c | 52 ++++ net/net.c | 6 + 21 files changed, 2512 insertions(+), 15 deletions(-) create mode 100644 api/Makefile create mode 100644 api/README create mode 100644 api/api.c create mode 100644 api/api_net.c create mode 100644 api/api_platform.c create mode 100644 api/api_storage.c create mode 100644 api_examples/Makefile create mode 100644 api_examples/crt0.S create mode 100644 api_examples/demo.c create mode 100644 api_examples/glue.c create mode 100644 api_examples/libgenwrap.c create mode 100644 include/api_public.h

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[U-Boot-Users] [PATCH] USB OHCI driver: Add NEC's PCI OHCI module ID
by David Saada 14 Oct '07

14 Oct '07

Description: Add NEC's PCI OHCI module ID to the USB OHCI driver Signed-off-by: David Saada <david.saada(a)ecitele.com> diff -purN usb_ohci.c.orig usb_ohci.c --- usb_ohci.c.orig 2007-09-11 15:59:55.780415000 +0300 +++ usb_ohci.c 2007-09-16 09:52:06.146578000 +0200 @@ -93,6 +93,7 @@ #ifdef CONFIG_PCI_OHCI static struct pci_device_id ohci_pci_ids[] = { {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */ + {0x1033, 0x0035}, /* NEC PCI OHCI module ids */ /* Please add supported PCI OHCI controller ids here */ {0, 0} }; -- View this message in context: http://www.nabble.com/-PATCH--USB-OHCI-driver%3A-Add-NEC%27s-PCI-OHCI-modul… Sent from the Uboot - Users mailing list archive at Nabble.com.

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