October 2007 - U-Boot

[U-Boot-Users] [patch] rtl8139.c: use PCI IO map
by Lucas Jin 16 Oct '07

16 Oct '07

Signed-off-by: Lucas Jin <lucasjin(a)gmail.com> --- ./drivers/rtl8139.c.orig 2007-10-12 22:17:52.000000000 +0800 +++ ./drivers/rtl8139.c 2007-10-13 17:34:40.117515408 +0800 @@ -104,8 +104,8 @@ #undef DEBUG_RX #define currticks() get_timer(0) -#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) -#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#define bus_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_io((pci_dev_t)dev->priv, a) /* Symbolic offsets to registers. */ enum RTL8139_registers { @@ -213,7 +213,7 @@ if ((devno = pci_find_devices(supported, idx++)) < 0) break; - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); iobase &= ~0xf; debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); -------------- Lucas Jin

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[U-Boot-Users] patches for 1.3.0-rc?
by Kumar Gala 15 Oct '07

15 Oct '07

Wolfgang, Any reason these two patches didn't make 1.3.0-rc3? http://article.gmane.org/gmane.comp.boot-loaders.u-boot/32332/match=gala http://article.gmane.org/gmane.comp.boot-loaders.u-boot/32331/match=gala - k

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[U-Boot-Users] AT91RM9200 boot.bin interaction with u-boot and SDRAM
by Craig Robinson 15 Oct '07

15 Oct '07

Dear Ulf, A while back (http://www.nabble.com/at91rm9200---silent-console-tf4418118.html#a12631849) you pointed me at the atmel patched source for u-boot 1.2.0. I have compiled and run this on the EK with out problems. Thank-you. However, I now come to getting u-boot to function on our EK based hardware. Our new board has AT49BV642D flash and I have added support to the code for this part (still compiles and runs on the EK). Aside from a total lack of Ethernet support, the main difference between our board and the EK is the size of the SDRAM. We use half that on the EK (16Meg rather than 32Meg). So, reading the source code for both u-boot and boot.bin, I'm thinking that we need to change some things to take into account the change in SDRAM. What I think I need to alter is: boot.bin - main.c #define DST 0x21f00000 to 0x20f00000 entry.S redefine STACK to be 0x21000000 not 0x22000000 u-boot - change TEXT_BASE to 0x20f00000 redefine PHYS_SDRAM_SIZE to 0x1000000 in <board>.h Is this correct and have I missed anything? Also, is it broadly correct to say that boot.bin does the following: 1. low level init 2. uncompress a gzipped file from SRC in parallel flash and put it in SDRAM at DST 3. jump to unzipped file at DST. If this is the case, then do we need to also ensure that CONFIG_SKIP_RELOCATE_UBOOT is defined? Is there a point to this aside from saving space in flash? Many thanks in advance. Craig Robinson. No virus found in this outgoing message. Checked by AVG Free Edition. Version: 7.5.488 / Virus Database: 269.14.8/1064 - Release Date: 11/10/2007 15:09

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[U-Boot-Users] [USB] Pull Request git://www.denx.de/git/u-boot-usb.git
by Markus Klotzbücher 15 Oct '07

15 Oct '07

Dear Wolfgang, Please pull from git://www.denx.de/git/u-boot-usb.git where the following change can be found: The following changes since commit 86ec86c04326c3913178a7679aa910de071da75d: Jean-Christophe PLAGNIOL-VILLARD (1): Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial are available in the git repository at: git://www.denx.de/git/u-boot-usb.git master Timo Ketola (1): Bugfix: Use only one PTD for one endpoint drivers/isp116x-hcd.c | 112 +++++++++++++++++++++++++++++++----------------- 1 files changed, 72 insertions(+), 40 deletions(-) Best regards Markus Klotzbuecher -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de

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[U-Boot-Users] Possible bug in PPC4xx dcache() function
by Larry Johnson 15 Oct '07

15 Oct '07

Greetings! If I call the dflush() function in cpu/ppc4xx/start.S on a PPC440EPx as part of initializing SDRAM, I later get the error The value of DVLIM special register is incorrect: 0x00000000 from spr_post_test(). I can make the spr_post_test() error message go away by applying the patch --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1711,6 +1711,7 @@ trap_reloc: rlwinm r8,r9,0,15,13 rlwinm r8,r8,0,17,15 mtmsr r8 + mfspr r8,dvlim addi r3,r0,0x0000 mtspr dvlim,r3 mfspr r3,ivpr @@ -1725,6 +1726,7 @@ trap_reloc: ..ag: dcbf r0,r3 addi r3,r3,-32 bdnz ..ag + mtspr dvlim,r8 sync mtmsr r9 blr The routine dflush() zeros DVLIM but does not save and restore the original value. Is this the intended behavior? The patch I tried seems safe, although I couldn't easily find the gcc function calling conventions for PowerPC. (Does anyone have a pointer to these?) -- Best regards, Larry Johnson <lrj(a)acm.org>

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[U-Boot-Users] embedding environment by hand
by Mike Frysinger 15 Oct '07

15 Oct '07

first a little background ... the Blackfin processor has a custom object format for booting code (called a "loader file" or "LDR" for short). this custom object format is what actually gets burned into say parallel or spi or nand flash. i have to hope that the Blackfin processor isnt alone in having a custom object format ;), so hopefully the changes i propose here will be useful to others. the exact object format is irrelevant here, but the point is that while the environment is actually embedded inside of the LDR image, it cannot be embedded with the standard method of creating the data array "environment" in environment.c and making sure the environment.o object gets linked at an exact offset. this is because we take the u-boot.bin and run it through another utility to get u-boot.ldr. the offsets in u-boot.bin do not correlate in any way to the offsets in u-boot.ldr nor can they as the LDR format may different drastically by processor. the utility that generates the u-boot.ldr has the ability to reserve space inside of the final image. so in the board configuration file, we say the environment lives at an offset of 0x4000 (to correspond to one of the flash sectors) of size say 0x2000. the utility is then told to generate space at an offset in u-boot.ldr at offset 0x4000 of size 0x2000. now the u-boot.ldr can be burned into flash without a problem and saving of the environment is OK. however, the initial u-boot.ldr is generated without the default environment programmed into it. so what i'd propose is to introduce a new define "ENV_IS_EMBEDDED_CUSTOM" and add a new flag to the envcrc helper. this would allow the environment.o linked into u-boot.bin to be empty and we can use envcrc helper to extract the environment blob so that the blob can be passed to extrenal utilities for embedding. the patch attached accomplishes both of these things. -mike

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[U-Boot-Users] [patch] fix bugs in rtl8139.c
by Lucas Jin 15 Oct '07

15 Oct '07

Signed-off-by: Lucas Jin <lucasjin(a)gmail.com> bug 1: "rx_ring" and "tx_buffer" are in local memory space, so they shouldn't be translated by "phys_to_bus". bug 2: macro KSEG1ADDR is just for MIPS, so we can use "le32_to_cpu" as a common way. ------------------------------ --- ./drivers/rtl8139.c.orig 2007-10-12 22:17:52.000000000 +0800 +++ ./drivers/rtl8139.c 2007-10-15 22:46:59.991316984 +0800 @@ -76,6 +76,7 @@ #include <net.h> #include <asm/io.h> #include <pci.h> +#include <linux/byteorder/generic.h> #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_RTL8139) @@ -383,7 +384,7 @@ #ifdef DEBUG_RX printf("rx ring address is %X\n",(unsigned long)rx_ring); #endif - outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); + outl((int)rx_ring, ioaddr + RxBuf); /* If we add multicast support, the MAR0 register would have to be * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot @@ -423,7 +424,7 @@ tx_buffer[len++] = '\0'; } - outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); + outl((int)tx_buffer, ioaddr + TxAddr0 + cur_tx*4); outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, ioaddr + TxStatus0 + cur_tx*4); @@ -480,7 +481,7 @@ #endif ring_offs = cur_rx % RX_BUF_LEN; - rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs)); + rx_status = le32_to_cpu(*(unsigned int*)(rx_ring + ring_offs)); rx_size = rx_status >> 16; rx_status &= 0xffff; -------------- Lucas Jin

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[U-Boot-Users] [GIT PULL] AVR32 fixes
by Haavard Skinnemoen 15 Oct '07

15 Oct '07

Hi Wolfgang, The following changes since commit 527c80f012030fa0b51f8594847ec56c9317e9b1: Stefan Roese (1): Merge with git://www.denx.de/git/u-boot.git are available in the git repository at: git://www.denx.de/git/u-boot-avr32.git master Eirik Aanonsen (2): Add some comments to clocks in atstk1002.h Update atstk1002 bootargs. Haavard Skinnemoen (3): Merge commit 'origin/master' Fix memtest breakage AVR32: Initialize bi_flash* in board_init_r Hans-Christian Egtvedt (2): Remove double quotation marks around MAC address for STK1002 Reduce BOOTDELAY variable to 1 second by default for STK1002 Semih Hazar (1): AVR32: Change prototype of memset board/atmel/atstk1000/flash.c | 4 ---- include/asm-avr32/string.h | 2 +- include/configs/atstk1002.h | 38 ++++++++++++++++++++++++++------------ lib_avr32/board.c | 12 +++++++++++- 4 files changed, 38 insertions(+), 18 deletions(-) diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 958f4dc..93d790f 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -55,10 +55,6 @@ unsigned long flash_init(void) unsigned long addr; unsigned int i; - gd->bd->bi_flashstart = CFG_FLASH_BASE; - gd->bd->bi_flashsize = CFG_FLASH_SIZE; - gd->bd->bi_flashoffset = _edata - _text; - flash_info[0].size = CFG_FLASH_SIZE; flash_info[0].sector_count = 135; diff --git a/include/asm-avr32/string.h b/include/asm-avr32/string.h index 8b05d1a..58582a3 100644 --- a/include/asm-avr32/string.h +++ b/include/asm-avr32/string.h @@ -23,6 +23,6 @@ #define __ASM_AVR32_STRING_H #define __HAVE_ARCH_MEMSET -extern void *memset(void *s, int c, size_t n); +extern void *memset(void *s, int c, __kernel_size_t n); #endif /* __ASM_AVR32_STRING_H */ diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 75b153e..1809fc5 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -39,8 +39,10 @@ #define CFG_HZ 1000 /* - * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL - * frequency and the peripherals to run at 1/4 the PLL frequency. + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the + * PLL frequency. + * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz */ #define CONFIG_PLL 1 #define CFG_POWER_MANAGER 1 @@ -48,9 +50,25 @@ #define CFG_PLL0_DIV 1 #define CFG_PLL0_MUL 7 #define CFG_PLL0_SUPPRESS_CYCLES 16 +/* + * Set the CPU running at: + * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz + */ #define CFG_CLKDIV_CPU 0 +/* + * Set the HSB running at: + * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz + */ #define CFG_CLKDIV_HSB 1 +/* + * Set the PBA running at: + * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz + */ #define CFG_CLKDIV_PBA 2 +/* + * Set the PBB running at: + * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz + */ #define CFG_CLKDIV_PBB 1 /* @@ -78,7 +96,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k" + "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" #define CONFIG_BOOTCOMMAND \ "fsload; bootm $(fileaddr)" @@ -87,7 +105,7 @@ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage * data on the serial line may interrupt the boot sequence. */ -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTDELAY 1 #define CONFIG_AUTOBOOT 1 #define CONFIG_AUTOBOOT_KEYED 1 #define CONFIG_AUTOBOOT_PROMPT \ @@ -103,8 +121,8 @@ * generated and assigned to the environment variables "ethaddr" and * "eth1addr". */ -#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" -#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" +#define CONFIG_ETHADDR 6a:87:71:14:cd:cb +#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_NET_MULTI 1 @@ -182,12 +200,8 @@ #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) #define CFG_LONGHELP 1 -#define CFG_MEMTEST_START \ - ({ gd->bd->bi_dram[0].start; }) -#define CFG_MEMTEST_END \ - ({ \ - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ - }) +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } #endif /* __CONFIG_H */ diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 8b9ca38..11d864f 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -310,10 +310,20 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) malloc_bin_reloc(); dma_alloc_init(); board_init_info(); - flash_init(); + + bd->bi_flashstart = 0; + bd->bi_flashsize = 0; + bd->bi_flashoffset = 0; + +#ifndef CFG_NO_FLASH + bd->bi_flashstart = CFG_FLASH_BASE; + bd->bi_flashsize = flash_init(); + bd->bi_flashoffset = (unsigned long)_edata - (unsigned long)_text; if (bd->bi_flashsize) display_flash_config(); +#endif + if (bd->bi_dram[0].size) display_dram_config();

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[U-Boot-Users] [PATCH] add ft_cpu_setup(..) on mpc8260
by Sergej Stepanov 15 Oct '07

15 Oct '07

add ft_cpu_setup(..)-function to adapt it for using with flattened device tree based on code from mpc5xxx Sigend-off-by: Sergej Stepanov <Sergej.Stepanov(a)ids.de> --- diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 94651dc..fbddd71 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -38,6 +38,9 @@ * * added HiP7 (824x/827x/8280) processors support by * Yuli Barcohen <yuli(a)arabellasw.com> + * + * added ft_cpu_setup(..) for using with CONFIG_OF_LIBFDT + * Sergej Stepanov <Sergej.Stepanov(a)ids.de> */ #include <common.h> @@ -47,6 +50,11 @@ #include <asm/processor.h> #include <asm/cpm_8260.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <libfdt_env.h> +#endif + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_GET_CPU_STR_F) @@ -294,3 +302,32 @@ void watchdog_reset (void) #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ +#if defined(CONFIG_OF_LIBFDT) +static void do_fixup(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) +{ + int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); + if (rc) + printf("Unable to update property %s:%s, err=%s\n", + node, prop, fdt_strerror(rc)); +} + +static void do_fixup_u32(void *fdt, const char *node, const char *prop, + u32 val, int create) +{ + val = cpu_to_fdt32(val); + do_fixup(fdt, node, prop, &val, sizeof(val), create); +} + +void ft_cpu_setup (void *blob, bd_t *bd) +{ + u32 *p; + ulong clock; + int len; + char * cpu_path = "/cpus/" OF_CPU; + + do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); + do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); + do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); +} +#endif /* CONFIG_OF_LIBFDT */

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[U-Boot-Users] [PATCH] ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier
by Stefan Roese 15 Oct '07

15 Oct '07

The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/sequoia/cmd_sequoia.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index f3803c0..e7997e9 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -25,6 +25,7 @@ #include <common.h> #include <command.h> #include <i2c.h> +#include <asm/io.h> /* * There are 2 versions of production Sequoia & Rainier platforms. @@ -200,8 +201,12 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* check CPLD register +5 for PCI 66MHz flag */ - if (in8(CFG_BCSR_BASE + 5) & 0x01) - buf[5] += 0x10; + if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0) + /* + * PLB-to-PCI divisor = 3 for 33MHz sync PCI + * instead of 2 for 66MHz systems + */ + buf[5] |= 0x08; if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); -- 1.5.3.4

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