March 2024 - U-Boot

[PATCH] mx6cuboxi: Do not print devicetree model
by Fabio Estevam 28 Mar '24

28 Mar '24

The mx6cuboxi_defconfig target supports several board variants. All of these variants use the hummingboard devicetree in U-Boot. Currently, the devicetree model as well as the board variant name are shown: U-Boot 2024.04-rc5-00003-g774ec4fda8 (Mar 27 2024 - 16:48:35 +0100) ... Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc) Board: MX6 Cubox-i ... Printing the devicetree model that is used internally by U-Boot may confuse users. Unselect the CONFIG_DISPLAY_BOARDINFO option so that only the board name is printed instead. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- configs/mx6cuboxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 27ceb22599a6..e3aba715aa58 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -28,6 +28,7 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;" CONFIG_SYS_PBSIZE=532 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_FS_EXT4=y -- 2.34.1

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[PATCH] mx6cuboxi: Fix Ethernet after DT sync with Linux
by Fabio Estevam 28 Mar '24

28 Mar '24

From: Josua Mayer <josua(a)solid-run.com> The i.MX6 Cubox-i and HummingBoards can have different PHYs at varying addresses. U-Boot needs to auto-detect which phy is actually present, and at which address it is responding. Auto-detection from multiple phy nodes specified in device-tree does not currently work correct. As a work-around merge all three possible phys into one node with the special address 0xffffffff which indicates to the generic phy driver to probe all addresses. Also fixup this fake address before booting Linux, *if* booting with U-Boot's internal dtb. Signed-off-by: Josua Mayer <josua(a)solid-run.com> [fabio: Added the changes to imx6qdl-sr-som-u-boot.dtsi.] Signed-off-by: Fabio Estevam <festevam(a)gmail.com> Tested-by: Christian Gmeiner <cgmeiner(a)igalia.com> --- ...qdl-hummingboard2-emmc-som-v15-u-boot.dtsi | 1 + arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi | 40 +++++++++++++++++++ board/solidrun/mx6cuboxi/mx6cuboxi.c | 8 +++- 3 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi index e9b188ed6587..358cf8abc4ff 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ #include "imx6qdl-u-boot.dtsi" +#include "imx6qdl-sr-som-u-boot.dtsi" / { board-detect { diff --git a/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi new file mode 100644 index 000000000000..4c5f043ea92a --- /dev/null +++ b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include <dt-bindings/gpio/gpio.h> + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; + phy-mode = "rgmii-id"; + + /* + * The PHY seems to require a long-enough reset duration to avoid + * some rare issues where the PHY gets stuck in an inconsistent and + * non-functional state at boot-up. 10ms proved to be fine . + */ + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ ethernet-phy@1; + /delete-node/ ethernet-phy@4; + + phy: ethernet-phy@0 { + /* + * The PHY can appear either: + * - AR8035: at address 0 or 4 + * - ADIN1300: at address 1 + * Actual address being detected at runtime. + */ + reg = <0xffffffff>; + qca,clk-out-frequency = <125000000>; + qca,smarteee-tw-us-1g = <24>; + adi,phy-output-clock = "125mhz-free-running"; + }; + }; +}; diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 8edabf4404c2..fbab39e800a6 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -447,7 +447,7 @@ static int find_ethernet_phy(void) */ int ft_board_setup(void *fdt, struct bd_info *bd) { - int node_phy0, node_phy1, node_phy4; + int node_phy, node_phy0, node_phy1, node_phy4; int ret, phy; bool enable_phy0 = false, enable_phy1 = false, enable_phy4 = false; enum board_type board; @@ -479,6 +479,12 @@ int ft_board_setup(void *fdt, struct bd_info *bd) return 0; } + // update U-Boot's own unified phy node phy address, if present + node_phy = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/phy"); + ret = fdt_setprop_u32(fdt, node_phy, "reg", phy); + if (ret < 0) + pr_err("%s: failed to update unified PHY node address\n", __func__); + // update all phy nodes status node_phy0 = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@0"); ret = fdt_setprop_string(fdt, node_phy0, "status", enable_phy0 ? "okay" : "disabled"); -- 2.34.1

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Thoughts about U-boot binary size increase
by Lukasz Majewski 28 Mar '24

28 Mar '24

Dear Community, I'd like to share with you some thoughts about growth of u-boot's binary size for SPL and u-boot proper. Board: XEA SoC : imx287 (still in active production) Problem: SPL size constrained to ~55 KiB (This cannot be exceeded). Board design constraints u-boot proper size to less than ~448 KiB When XEA was added (2019.07): - u-boot.sb (SPL): 37 KiB - u-boot.img : 401 KiB Now (2024.04): - u-boot.sb (SPL): 40 KiB - u-boot.img : 427 KiB (With a _lot_ of effort put to reduce the size) Hence, the question - would it be possible to take more concern about the binary size growth? Maybe CI could catch patches, which enable by default some features and the size is unintentionally increased? I'm open for any feedback and thoughts on "stopping" the binary size increase. Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma(a)denx.de

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[PATCH v2] riscv: Move virtio scan to board_late_init()
by Łukasz Stelmach 28 Mar '24

28 Mar '24

When virtio_init() gets called from board_init() PCI isn't ready. Thus, virtio-over-PCI (e.g. network interfaces) devices can't be detected and used without additional `virtio scan` scan in the shell or a script. Signed-off-by: Łukasz Stelmach <l.stelmach(a)samsung.com> --- Changes since v1: - remove virtio_init() call from board_init() - select BOARD_LATE_INIT for TARGET_QEMU_VIRT arch/riscv/Kconfig | 1 + board/emulation/qemu-riscv/qemu-riscv.c | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ac52c5e6daf..c5c2e8a9c9d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,6 +22,7 @@ config TARGET_OPENPITON_RISCV64 config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" + select BOARD_LATE_INIT config TARGET_SIFIVE_UNLEASHED bool "Support SiFive Unleashed Board" diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 181abbbf97d..173245b40e3 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -31,12 +31,6 @@ int is_flash_available(void) int board_init(void) { - /* - * Make sure virtio bus is enumerated so that peripherals - * on the virtio bus can be discovered by their drivers - */ - virtio_init(); - return 0; } @@ -46,6 +40,12 @@ int board_late_init(void) if (CONFIG_IS_ENABLED(USB_KEYBOARD)) usb_init(); + /* + * Make sure virtio bus is enumerated so that peripherals + * on the virtio bus can be discovered by their drivers + */ + virtio_init(); + return 0; } -- 2.39.2

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tcg2_platform_get_log failing to read address and size of memory-region via ofnode_get_addr_size
by Tim Harvey 28 Mar '24

28 Mar '24

Greetings, I'm unable to understand why tcg2_platform_get_log is failing to read a memory region. For example the following diffs: diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi index 7b2130dbdb21..57b3c227ceaf 100644 --- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi @@ -112,6 +112,7 @@ compatible = "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; + memory-region = <&event_log>; }; }; diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi index c305e325d007..697fd1148785 100644 --- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi @@ -13,6 +13,17 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + event_log: tcg_event_log { + no-map; + reg = <0 0x40000000 0x2000>; + }; + }; + gpio-keys { compatible = "gpio-keys"; And at runtime: u-boot=> fdt addr $fdtcontroladdr u-boot=> fdt list /soc@0/bus@30800000/spba-bus@30800000/spi@30830000/tpm@1/ tpm@1 { compatible = "tcg,tpm_tis-spi"; reg = <0x00000001>; spi-max-frequency = <0x02255100>; memory-region = <0x00000025>; }; u-boot=> fdt list /reserved-memory/ reserved-memory { #address-cells = <0x00000002>; #size-cells = <0x00000002>; ranges; tcg_event_log { }; }; u-boot=> fdt list /reserved-memory/tcg_event_log tcg_event_log { no-map; reg = <0x00000000 0x40000000 0x00002000>; phandle = <0x00000025>; }; So why does the following code in tcg2_platform_get_log() return -ENOMEM? if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args)) return -ENODEV; a = ofnode_get_addr_size(args.node, "reg", &s); if (a == FDT_ADDR_T_NONE) return -ENOMEM; debugging shows that dev_read_phandle_with_args returns non-zero but args.args_count is 0. I feel like the construct of using dev_read_phandle_with_args followed by the ofnode_get_addr_size is just wrong but I don't understand why nor do I understand how my dt changes differ from what is in arch/sandbox/dts/test.dts (other than its using address-size=1 which doesn't appear to be the issue in my testing). The abstraction of the ofnode and fdt stuff always trip me up... very confusing. Can anyone explain the issue here? Best Regards, Tim

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[PATCH 0/2] arm: socfpga: arria10: allow to reprogram FPGA with warm reboot
by Michał Barnaś 28 Mar '24

28 Mar '24

By default, the board requires power cycle (cold boot) to program the FPGA with bitstream. This change adds Kconfig that allows to enable reprogramming the FPGA with every boot. This makes the update process of the bitstream on the filesystem to be applied with simple system reboot. Michał Barnaś (2): arm: socfpga: arria10: add option to reprogram the FPGA every reboot chameleonv3: set in defconfig for FPGA to reprogram every reboot arch/arm/mach-socfpga/Kconfig | 8 ++++++++ arch/arm/mach-socfpga/spl_a10.c | 8 ++++++++ configs/socfpga_chameleonv3_defconfig | 1 + 3 files changed, 17 insertions(+) -- 2.44.0.rc1.240.g4c46232300-goog

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[[PATCH v2]] riscv: add backtrace support
by Ben Dooks 28 Mar '24

28 Mar '24

When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Signed-off-by: Ben Dooks <ben.dooks(a)codethink.co.uk> --- v2: - back to codethink email as sifive account is now gone - add option to build SPL with frame pointer (as suggested by Bo Gan <ganboing(a)gmail.com> --- arch/riscv/Kconfig | 20 ++++++++++++++++++++ arch/riscv/Makefile | 4 ++++ arch/riscv/cpu/start.S | 1 + arch/riscv/lib/interrupts.c | 35 +++++++++++++++++++++++++++++++++++ 4 files changed, 60 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6771d8d919..a446166631 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -111,6 +111,26 @@ config ARCH_RV64I endchoice +config FRAMEPOINTER + bool "Build with frame pointer for stack unwinding" + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + +config SPL_FRAMEPOINTER + bool "Build SPL with frame pointer for stack unwinding" + help + Choose this option to use the frame pointer so the stack can be + unwound if needed. This is useful for tracing where faults came + from as the source may be several functions back + + If you say Y here, then the code size will be increased due to + having to store the fp. + choice prompt "Code Model" default CMODEL_MEDLOW diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4963b5109b..0cb60c7c7e 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -45,6 +45,10 @@ endif ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) +ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y) + ARCH_FLAGS += -fno-omit-frame-pointer +endif + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) CFLAGS_EFI += $(ARCH_FLAGS) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 30cf674370..53de424378 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -419,6 +419,7 @@ call_board_init_r: */ mv a0, s3 /* gd_t */ mv a1, s4 /* dest_addr */ + mv s0, zero /* fp == NULL */ /* * jump to it ... diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index e966afa7e3..db3d7e294b 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -53,6 +53,40 @@ static void show_regs(struct pt_regs *regs) #endif } +#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER) +static void show_backtrace(struct pt_regs *regs) +{ + uintptr_t *fp = (uintptr_t *)regs->s0; + unsigned count = 0; + ulong ra; + + printf("backtrace:\n"); + + /* there are a few entry points where the s0 register is + * set to gd, so to avoid changing those, just abort if + * the value is the same */ + while (fp != NULL && fp != (uintptr_t *)gd) { + ra = fp[-1]; + printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT, + count, (ulong)fp, ra); + + if (gd && gd->flags & GD_FLG_RELOC) + printf(" - RA: " REG_FMT " reloc adjusted\n", + ra - gd->reloc_off); + else + printf("\n"); + + fp = (uintptr_t *)fp[-2]; + count++; + } +} +#else +static void show_backtrace(struct pt_regs *regs) +{ + printf("No backtrace support enabled\n"); +} +#endif + /** * instr_len() - get instruction length * @@ -119,6 +153,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); + show_backtrace(regs); show_code(epc); show_efi_loaded_images(epc); panic("\n"); -- 2.40.1

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[PATCH v1 0/2] Support new RISC-V ISA extension properties
by Conor Dooley 28 Mar '24

28 Mar '24

From: Conor Dooley <conor.dooley(a)microchip.com> This would have just been a single patch (the second one), but as I reported a while back there's a problem with extension detection when the ISA string exceeds 32 characters: https://lore.kernel.org/u-boot/20240221-daycare-reliably-8ec86f95fe71@spud/ The first patch here fixes what I see as a bit of a misuse of cpu_get_desc() in supports_extension() as a preparatory patch for adding the new properties. Or more accurately, new property, as U-Boot barely makes use of extension detection as-is in s-mode and only one of the two new properties is even needed. Maybe it's not a misuse, but I left a comment under the --- line on that patch about the before/after for the RISC-V cpu's cpu_get_desc() and maybe my approach here would not be appreciated. Cheers, Conor. CC: Rick Chen <rick(a)andestech.com> CC: Leo <ycliang(a)andestech.com> CC: Tom Rini <trini(a)konsulko.com> CC: Conor Dooley <conor.dooley(a)microchip.com> CC: Heinrich Schuchardt <xypron.glpk(a)gmx.de> CC: u-boot(a)lists.denx.de (open list) Conor Dooley (2): riscv: don't read riscv,isa in the riscv cpu's get_desc() riscv: support extension probing using riscv,isa-extensions arch/riscv/cpu/cpu.c | 60 ++++++++++++++++++++++++++--------------- drivers/cpu/riscv_cpu.c | 8 +++--- 2 files changed, 42 insertions(+), 26 deletions(-) -- 2.43.0

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Re: [PATCH] mx6cuboxi: fix ethernet after synchronise device-tree
by Josua Mayer 28 Mar '24

28 Mar '24

Please hold off merging this patch until someone tested it, I can not do so this week. @Tom Can you confirm if this fixes the networking on your Cubox? Also note that the phy-handle property may or may not be required, I am not sure. sincerely Josua Mayer On Thu, Jul 28, 2022 at 7:05 AM Josua Mayer <josua(a)solid-run.com> wrote: > The i.MX6 Cubox-i and HummingBoards can have different PHYs at varying > addresses. U-Boot needs to auto-detect which phy is actually present, > and at which address it is responding. > > Auto-detection from multiple phy nodes specified in device-tree does not > currently work correct. As a work-around merge all three possible phys > into one node with the special address 0xffffffff which indicates to the > generic phy driver to probe all addresses. > Also fixup this fake address before booting Linux, *if* booting with > U-Boot's internal dtb. > > Signed-off-by: Josua Mayer <josua(a)solid-run.com> > Fixes: d0399a46e7cd > --- > arch/arm/dts/imx6qdl-sr-som.dtsi | 30 +++++++++------------------- > board/solidrun/mx6cuboxi/mx6cuboxi.c | 6 +++++- > 2 files changed, 14 insertions(+), 22 deletions(-) > > diff --git a/arch/arm/dts/imx6qdl-sr-som.dtsi > b/arch/arm/dts/imx6qdl-sr-som.dtsi > index ce543e325c..2d7cbc26b3 100644 > --- a/arch/arm/dts/imx6qdl-sr-som.dtsi > +++ b/arch/arm/dts/imx6qdl-sr-som.dtsi > @@ -53,6 +53,7 @@ > &fec { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; > + phy-handle = <&phy>; > phy-mode = "rgmii-id"; > > /* > @@ -68,30 +69,17 @@ > #address-cells = <1>; > #size-cells = <0>; > > - /* > - * The PHY can appear at either address 0 or 4 due to the > - * configuration (LED) pin not being pulled sufficiently. > - */ > - ethernet-phy@0 { > - reg = <0>; > + phy: ethernet-phy@0 { > + /* > + * The PHY can appear either: > + * - AR8035: at address 0 or 4 > + * - ADIN1300: at address 1 > + * Actual address being detected at runtime. > + */ > + reg = <0xffffffff>; > qca,clk-out-frequency = <125000000>; > qca,smarteee-tw-us-1g = <24>; > - }; > - > - ethernet-phy@4 { > - reg = <4>; > - qca,clk-out-frequency = <125000000>; > - qca,smarteee-tw-us-1g = <24>; > - }; > - > - /* > - * ADIN1300 (som rev 1.9 or later) is always at address 1. > It > - * will be enabled automatically by U-Boot if detected. > - */ > - ethernet-phy@1 { > - reg = <1>; > adi,phy-output-clock = "125mhz-free-running"; > - status = "disabled"; > }; > }; > }; > diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c > b/board/solidrun/mx6cuboxi/mx6cuboxi.c > index debf4f6a3b..52172a03b1 100644 > --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c > +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c > @@ -446,7 +446,7 @@ static int find_ethernet_phy(void) > */ > int ft_board_setup(void *fdt, struct bd_info *bd) > { > - int node_phy0, node_phy1, node_phy4; > + int node_phy, node_phy0, node_phy1, node_phy4; > int ret, phy; > bool enable_phy0 = false, enable_phy1 = false, enable_phy4 = false; > enum board_type board; > @@ -478,6 +478,10 @@ int ft_board_setup(void *fdt, struct bd_info *bd) > return 0; > } > > + // update U-Boot's own unified phy node phy address, if present > + node_phy = fdt_path_offset(fdt, "/soc/bus@2100000/ethernet@2188000 > /mdio/phy"); > + ret = fdt_setprop_u32(fdt, node_phy, "reg", phy); > + > // update all phy nodes status > node_phy0 = fdt_path_offset(fdt, "/soc/bus@2100000 > /ethernet@2188000/mdio/ethernet-phy@0"); > ret = fdt_setprop_string(fdt, node_phy0, "status", enable_phy0 ? > "okay" : "disabled"); > -- > 2.37.1 > >

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[PATCH v1 1/1] [U-Boot] drivers: misc: Fixes: Rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG
by wan.yee.lau＠intel.com 28 Mar '24

28 Mar '24

From: Wan Yee Lau <wan.yee.lau(a)intel.com> Commit 3f190c55a4211215914126b74357344342329943 ("drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA") This commit rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG in Makefile. Signed-off-by: Wan Yee Lau <wan.yee.lau(a)intel.com> --- drivers/misc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1522f6c3b7..5bb1b315cd 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -90,4 +90,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o -obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o +obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o -- 2.25.1

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