March 2024 - U-Boot

[PATCH 1/2] arm: imx9: Correct imx9_probe_mu prototype
by Ye Li 30 Mar '24

30 Mar '24

Since the event callback imx9_probe_mu is re-defined, update its prototype. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- arch/arm/include/asm/arch-imx9/mu.h | 2 +- board/freescale/imx93_evk/spl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx9/mu.h b/arch/arm/include/asm/arch-imx9/mu.h index b860499..649b8a6 100644 --- a/arch/arm/include/asm/arch-imx9/mu.h +++ b/arch/arm/include/asm/arch-imx9/mu.h @@ -8,6 +8,6 @@ #include <event.h> -int imx9_probe_mu(void *ctx, struct event *event); +int imx9_probe_mu(void); #endif diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index 2fd5559..7331a20 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -116,7 +116,7 @@ void board_init_f(ulong dummy) preloader_console_init(); - ret = imx9_probe_mu(NULL, NULL); + ret = imx9_probe_mu(); if (ret) { printf("Fail to init Sentinel API\n"); } else { -- 2.7.4

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[PATCH] mx6cuboxi: Convert to watchdog driver model
by Fabio Estevam 30 Mar '24

30 Mar '24

Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused the 'reset' command in U-Boot to not cause a board reset. Fix it by switching to the watchdog driver model via sysreset, which is the preferred method for implementing the watchdog reset. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- Christian, Can you test this, please? .../dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi | 10 ++++++++++ configs/mx6cuboxi_defconfig | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi index 23a05773b579..e9b188ed6587 100644 --- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi @@ -13,6 +13,12 @@ &gpio6 4 0 >; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &soc { @@ -58,3 +64,7 @@ &usdhc3 { bootph-all; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 66d4aaeda2d9..27ceb22599a6 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -71,6 +71,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y CONFIG_USB=y @@ -89,3 +91,4 @@ CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y +CONFIG_IMX_WATCHDOG=y -- 2.34.1

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[PATCH] warp7: Convert to watchdog driver model
by Fabio Estevam 30 Mar '24

30 Mar '24

Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused the 'reset' command in U-Boot to not cause a board reset. Fix it by switching to the watchdog driver model via sysreset, which is the preferred method for implementing the watchdog reset. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/dts/imx7s-warp-u-boot.dtsi | 10 ++++++++++ configs/warp7_defconfig | 3 +++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi index 4f44598c9a27..98784fd7a2ef 100644 --- a/arch/arm/dts/imx7s-warp-u-boot.dtsi +++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi @@ -7,6 +7,12 @@ chosen { stdout-path = &uart1; }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; }; &aips3 { @@ -24,3 +30,7 @@ &uart1 { bootph-all; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 9b518a121be6..48042b702c22 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -67,6 +67,8 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -80,5 +82,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" +CONFIG_IMX_WATCHDOG=y CONFIG_OPTEE_TZDRAM_SIZE=0x3000000 CONFIG_BOOTM_OPTEE=y -- 2.34.1

2 2

[PATCH] mx6cuboxi: Fix board revision detection
by Fabio Estevam 30 Mar '24

30 Mar '24

Currently, an i.MX6 Cuboxi board is incorrectly detected as the HummingBoard model: U-Boot 2024.04-rc5 (Mar 26 2024 - 15:59:22 +0100) CPU: Freescale i.MX6Q rev1.3 996 MHz (running at 792 MHz) CPU: Extended Commercial temperature grade (-20C to 105C) at 26C Reset cause: POR Model: SolidRun HummingBoard2 Dual/Quad (1.5som+emmc) gpio@20a4000: set_dir_flags: error: gpio GPIO3_8 not reserved gpio@20a4000: get_value: error: gpio GPIO3_8 not reserved gpio@20a8000: set_dir_flags: error: gpio GPIO4_4 not reserved gpio@20a8000: get_value: error: gpio GPIO4_4 not reserved gpio@20b0000: set_dir_flags: error: gpio GPIO6_9 not reserved gpio@20b0000: get_value: error: gpio GPIO6_9 not reserved Board: MX6 HummingBoard DRAM: 2 GiB ... This error happens because request_detect_gpios() uses the GPIO DM API, but board_type() still uses the legacy non-DM GPIO API. Fix it by using the GPIO DM API in board_type() to read the board revision pins in SPL. Reported-by: Christian Gmeiner <cgmeiner(a)igalia.com> Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 8edabf4404c2..7fe515f928a0 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -336,20 +336,17 @@ static enum board_type board_type(void) * HB 1 1 x */ - gpio_direction_input(IMX_GPIO_NR(2, 8)); - val3 = gpio_get_value(IMX_GPIO_NR(2, 8)); + val3 = !!dm_gpio_get_value(&board_detect_desc[0]); if (val3 == 0) return HUMMINGBOARD2; - gpio_direction_input(IMX_GPIO_NR(3, 4)); - val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); + val2 = !!dm_gpio_get_value(&board_detect_desc[1]); if (val2 == 0) return HUMMINGBOARD; - gpio_direction_input(IMX_GPIO_NR(4, 9)); - val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); + val1 = !!dm_gpio_get_value(&board_detect_desc[2]); if (val1 == 0) { return CUBOXI; @@ -363,8 +360,8 @@ static bool is_rev_15_som(void) int val1, val2; SETUP_IOMUX_PADS(som_rev_detect); - val1 = gpio_get_value(IMX_GPIO_NR(6, 0)); - val2 = gpio_get_value(IMX_GPIO_NR(6, 4)); + val1 = !!dm_gpio_get_value(&board_detect_desc[3]); + val2 = !!dm_gpio_get_value(&board_detect_desc[4]); if (val1 == 1 && val2 == 0) return true; -- 2.34.1

2 2

[RFC 0/2] Update RAM Bank Logic for RK3588
by Chris Morgan 30 Mar '24

30 Mar '24

From: Chris Morgan <macromorgan(a)hotmail.com> Use the ATAG info provided by the Rockchip binary TPL to identify RAM banks on the RK3588 when using the ROCKCHIP_TPL binary. This is needed because there are specific addresses that should not be written to for all RK3588 based devices with >=16GB of RAM, writing to these addresses immediately results in a crash. I intended this to be an RFC the first time I submitted it, so I'm correcting that mistake now. Additionally I have reduced a lot of the ATAGS code to only focus on the few bits we need in this case. Chris Morgan (2): rockchip: sdram: Allow board/soc specific RAM bank logic rockchip: rk3588: Add SoC specific RAM bank logic arch/arm/mach-rockchip/rk3588/rk3588.c | 93 ++++++++++++++++++++++++++ arch/arm/mach-rockchip/sdram.c | 7 ++ 2 files changed, 100 insertions(+) -- 2.34.1

3 6

[RFC] Makefile.lib: find capsule ESL dtsi file when CONFIG_OF_UPSTREAM=y
by Jonathan Humphreys 30 Mar '24

30 Mar '24

When CONFIG_OF_UPSTREAM is enabled, DTS files are in SOC subdirectories (vs the top level dts directory), but when CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled, the dynamically created dtsi file containing the capsule ESL DT node is in the parent directory. This results in a build failure because the #include inserted in the DTS file is local to the current directory. Update Makefile to have the DT preprocessing of #includes search in the parent (dts top level) directory too. I'm not sure if this is the best solution. I was also tempted to just manually include the capsule-key property in the board dts, and avoid the Makefile implicit inclusion trickery. I would actually prefer this approach as everything is more explicit. But this isn't an option because if CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled, the implicit inclusion of the dtsi file happens. It would be better, IMO, if we only included the generated dtsi file if CONFIG_EFI_CAPSULE_ESL_FILE is defined. Was only supporting the implicit inclusiong approach an intentional design choice? Thanks Jon Signed-off-by: Jonathan Humphreys <j-humphreys(a)ti.com> --- scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 12857316c58..62f87517c09 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -334,7 +334,7 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ (cat $< > $(pre-tmp)); \ $(foreach f,$(subst $(quote),,$(dtsi_include_list)), \ echo '$(pound)include "$(f)"' >> $(pre-tmp);) \ - $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \ + $(HOSTCC) -E $(dtc_cpp_flags) -I$(obj) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) ; \ $(DTC) -O dtb -o $@ -b 0 \ -i $(dir $<) -i $(u_boot_dtsi_loc) $(DTC_FLAGS) \ -d $(depfile).dtc.tmp $(dtc-tmp) || \ -- 2.34.1

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[PATCH v2] tpm-v2: allow algoirthm name to be configured for pcr_read and pcr_extend
by Tim Harvey 30 Mar '24

30 Mar '24

For pcr_read and pcr_extend commands allow the digest algorithm to be specified by an additional argument. If not specified it will default to SHA256 for backwards compatibility. A follow-on to this could be to extend all PCR banks with the detected algo when the <digest_algo> argument is 'auto'. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- v2: - use tpm2_algorithm_to_len - use enum tpm2_algorithms - make function names and parameter names more consistent with existing tpm-v2 functions - fix various spelling errors --- cmd/tpm-v2.c | 49 ++++++++++++++++++++++++++++++++++-------------- include/tpm-v2.h | 18 ++++++++++++++++++ lib/tpm-v2.c | 34 +++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 14 deletions(-) diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index 7e479b9dfe36..2343b4d9cb9e 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -99,11 +99,19 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc, struct tpm_chip_priv *priv; u32 index = simple_strtoul(argv[1], NULL, 0); void *digest = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0); + int algo = TPM2_ALG_SHA256; + int algo_len; int ret; u32 rc; - if (argc != 3) + if (argc < 3 || argc > 4) return CMD_RET_USAGE; + if (argc == 4) { + algo = tpm2_name_to_algorithm(argv[3]); + if (algo < 0) + return CMD_RET_FAILURE; + } + algo_len = tpm2_algorithm_to_len(algo); ret = get_tpm(&dev); if (ret) @@ -116,8 +124,12 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc, if (index >= priv->pcr_count) return -EINVAL; - rc = tpm2_pcr_extend(dev, index, TPM2_ALG_SHA256, digest, - TPM2_DIGEST_LEN); + rc = tpm2_pcr_extend(dev, index, algo, digest, algo_len); + if (!rc) { + printf("PCR #%u extended with %d byte %s digest\n", index, + algo_len, tpm2_algorithm_name(algo)); + print_byte_string(digest, algo_len); + } unmap_sysmem(digest); @@ -127,15 +139,23 @@ static int do_tpm2_pcr_extend(struct cmd_tbl *cmdtp, int flag, int argc, static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + enum tpm2_algorithms algo = TPM2_ALG_SHA256; struct udevice *dev; struct tpm_chip_priv *priv; u32 index, rc; + int algo_len; unsigned int updates; void *data; int ret; - if (argc != 3) + if (argc < 3 || argc > 4) return CMD_RET_USAGE; + if (argc == 4) { + algo = tpm2_name_to_algorithm(argv[3]); + if (algo < 0) + return CMD_RET_FAILURE; + } + algo_len = tpm2_algorithm_to_len(algo); ret = get_tpm(&dev); if (ret) @@ -151,11 +171,12 @@ static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc, data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0); - rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256, - data, TPM2_DIGEST_LEN, &updates); + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, algo, + data, algo_len, &updates); if (!rc) { - printf("PCR #%u content (%u known updates):\n", index, updates); - print_byte_string(data, TPM2_DIGEST_LEN); + printf("PCR #%u %s %d byte content (%u known updates):\n", index, + tpm2_algorithm_name(algo), algo_len, updates); + print_byte_string(data, algo_len); } unmap_sysmem(data); @@ -415,14 +436,14 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command", " <hierarchy> is one of:\n" " * TPM2_RH_LOCKOUT\n" " * TPM2_RH_PLATFORM\n" -"pcr_extend <pcr> <digest_addr>\n" -" Extend PCR #<pcr> with digest at <digest_addr>.\n" +"pcr_extend <pcr> <digest_addr> [<digest_algo>]\n" +" Extend PCR #<pcr> with digest at <digest_addr> with digest_algo.\n" " <pcr>: index of the PCR\n" -" <digest_addr>: address of a 32-byte SHA256 digest\n" -"pcr_read <pcr> <digest_addr>\n" -" Read PCR #<pcr> to memory address <digest_addr>.\n" +" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n" +"pcr_read <pcr> <digest_addr> [<digest_algo>]\n" +" Read PCR #<pcr> to memory address <digest_addr> with <digest_algo>.\n" " <pcr>: index of the PCR\n" -" <digest_addr>: address to store the a 32-byte SHA256 digest\n" +" <digest_addr>: address of digest of digest_algo type (defaults to SHA256)\n" "get_capability <capability> <property> <addr> <count>\n" " Read and display <count> entries indexed by <capability>/<property>.\n" " Values are 4 bytes long and are written at <addr>.\n" diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 33dd103767c4..933882fcbf97 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -965,4 +965,22 @@ u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, */ u32 tpm2_auto_start(struct udevice *dev); +/** + * tpm2_name_to_algorithm() - Return an algorithm id given a supported + * algorithm name + * + * @name: algorithm name + * Return: enum tpm2_algorithms or -EINVAL + */ +enum tpm2_algorithms tpm2_name_to_algorithm(const char *name); + +/** + * tpm2_algorithm_name() - Return an algorithm name string for a + * supported algorithm id + * + * @algorithm_id: algorithm defined in enum tpm2_algorithms + * Return: algorithm name string or "" + */ +const char *tpm2_algorithm_name(enum tpm2_algorithms); + #endif /* __TPM_V2_H */ diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index 68eaaa639f89..19b2535682e1 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -29,6 +29,13 @@ const enum tpm2_algorithms tpm2_supported_algorithms[4] = { TPM2_ALG_SHA512, }; +const char *tpm2_supported_algorithm_names[4] = { + "sha1", + "sha256", + "sha384", + "sha512", +}; + int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks) { u32 supported = 0; @@ -1555,3 +1562,30 @@ u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, return 0; } + +enum tpm2_algorithms tpm2_name_to_algorithm(const char *name) +{ + enum tpm2_algorithms algo; + size_t i; + + for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) { + algo = tpm2_supported_algorithms[i]; + if (!strcasecmp(name, tpm2_supported_algorithm_names[i])) + return algo; + } + printf("%s: unsupported algorithm %s\n", __func__, name); + + return -EINVAL; +} + +const char *tpm2_algorithm_name(enum tpm2_algorithms algo) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) { + if (tpm2_supported_algorithms[i] == algo) + return tpm2_supported_algorithm_names[i]; + } + + return ""; +} -- 2.25.1

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Re: [PATCH 01/19] spi: cadence_qspi: Add support for DDR PHY mode
by Greg Malysa 30 Mar '24

30 Mar '24

Hi Tejas, +Ian Roberts, (Apologies for the double mail--I accidentally dropped the u-boot mailing list in version 1) We have been developing OSPI support against the same Cadence IP in the Analog parts (SC594 and SC598) and we have some specific feedback as this patch series will affect the driver's functionality on our platform and require changes to our upcoming patches to work together. > { > @@ -353,6 +649,9 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, > break; > } > > + if (op->cmd.dtr) > + err = cadence_spi_setup_ddrmode(spi, op); > + > return err; > } This appears to trigger calibration with the first spi command received with the dtr flag set (cadence_spi_mem_exec_op -> cadence_spi_setup_ddrmode -> cadence_spi_setdlldelay -> cadence_qspi_rx_dll_tuning). However the calibration code assumes that this command is a read ID command, because code has been added to spi_nor_micro_octal_dtr_enable specifically to read the ID first. This will cause problems if we are adding support to another chip and are unaware that this host SPI controller detail needs to be added to the DTR enable function inside spi-nor-core. in cadence_qspi_rx_dll_tuning: > + id_matched = true; > + for (j = 0; j < op->data.nbytes; j++) { > + if (spi->device_id[j] != id[j]) { > + id_matched = false; > + break; > + } > + } This should probably just be a call to memcmp. Additionally, this assumes that the ID has already been read into spi->device_id, which happens in spi_nor_read_id. We believe that setup_ddrmode should be self contained, for example generating a non-dtr ID read and store (locally) first, then reconfiguring for DTR and issuing a DTR read. Based on our experience with the ADI EZKIT, reading a 3 or 6 byte ID is not always sufficient to perform robust calibration, as some data lines may end up being "calibrated" against a constant value. For example, the ISSI flash chips capable of DTR include a "data learning pattern" register which could be used to ensure that calibration is performed against a 0 to 1 transition and a 1 to 0 transition. Such functionality will be chip-specific, so we need to a way to connect what happens in the dtr enable function in spi-nor-core with what happens inside the driver (possibly another ops function). in priv_setup_ddrmode: > + /* Disable DAC mode */ > + if (priv->use_dac_mode) { > + clrbits_le32(regbase + CQSPI_REG_CONFIG, > + CQSPI_REG_CONFIG_DIRECT); > + priv->use_dac_mode = false; > + } Why is DAC forcefully disabled? On our platform we can only achieve max PHY mode performance with DAC enabled. Can we provide a platform-tunable flag to control this? In priv_setup_ddrmode: > + clrsetbits_le32(regbase + CQSPI_REG_RD_DATA_CAPTURE, > + (CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK << > + CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB), > + CQSPI_REG_READCAPTURE_DQS_ENABLE); DQS is not required for PHY operation. Some chips can operate in DDR mode and don't have a DQS line; we have one of these on our boards. Please make this configurable > +__weak int cadence_qspi_versal_set_dll_mode(struct udevice *dev) > +{ > + return -ENOTSUPP; > +} > + Setting the DLL mode will not be a Versal-specific function. Can we rename this (and other Versal-specific names) in order to make it clearer that each platform integrating this IP is providing its own implementation for this function, rather than it being a uniquely versal-related capability? For DLL mode in particular, it may be sufficient to check for a device tree property, which can be included in the generic driver without any platform-specific functions. In cadence_spi_setdlldelay: > + priv->extra_dummy = false; > + for (extra_dummy = 0; extra_dummy <= 1; extra_dummy++) { > + if (extra_dummy) > + priv->extra_dummy = true; > + > + rxtap = cadence_qspi_rx_dll_tuning(spi, op, txtap, extra_dummy); > + if (extra_dummy && rxtap < 0) { > + printf("Failed RX dll tuning\n"); > + return rxtap; > + } > + } Can you please explain the extra dummy cycles? Why are more needed outside of what is called out for in flash datasheets? This looks to us like magic compensating for a calibration failure or a configuration failure where the flash chip is not providing the expected number of dummy cycles. in cadence_qspi_rx_dll_tuning: > + ret = cadence_qspi_apb_command_read_setup(priv, op); > + if (!ret) { > + ret = cadence_qspi_apb_command_read(priv, op); > + if (ret < 0) { > + printf("error %d reading JEDEC ID\n", ret); > + return ret; > + } > + I see that this cannot use cadence_spi_mem_exec_op() because it would recursively trigger itself as the calibration was not yet completed, but as a result this does not support all of the read modes that the device could be configured for. I think this is further reason to have a specialized function for enabling DTR rather than triggering it on the first DTR operation. > +static int cadence_spi_child_pre_probe(struct udevice *bus) > +{ > + struct spi_slave *slave = dev_get_parent_priv(bus); > + > + slave->bytemode = SPI_4BYTE_MODE; > + > + return 0; > +} > + > +__weak int cadence_qspi_versal_set_dll_mode(struct udevice *dev) > +{ > + return -ENOTSUPP; > +} Although it is likely that any flash supporting DTR uses 4 byte addressing, we should not set it here. > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > index faf02c7778..5895b5de09 100644 > --- a/drivers/mtd/spi/spi-nor-core.c > +++ b/drivers/mtd/spi/spi-nor-core.c Can we split the micron-specific changes into a separate patch? I realize currently that they are tightly coupled with the calibration implementation, but after changing the calibration implementation perhaps this will be possible. Some additional comments not specific to any part of the code: How does this patch address the case when the calibrated frequency is faster than the non-calibrated mode can run at? For example, if spi-max-frequency is 125MHz, but single IO operation breaks down at speeds greater than 50MHz? (This also happens on our board). Also, the calibration algorithm doesn't appear to re-calibrate the read capture delay register, which is required whenever the clock or IO mode changes. At Timesys we have a set of patches that implement DDR and PHY calibration for the same Cadence IP that presents different solutions to the above issues. However, our patches only support bypass mode calibration and direct mode, because they are the only options that work on our hardware. Would you be interested in looking at our version and working together to create a new version of this patchset that can support both of our platforms at once? Thanks, Greg -- Greg Malysa Timesys Corporation

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[PATCH] lib: fix newline in debug message
by Maxim Moskalets 30 Mar '24

30 Mar '24

Signed-off-by: Maxim Moskalets <maximmosk4(a)gmail.com> --- lib/rsa/rsa-verify.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 1007b6979a..e1093ce1a4 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -342,7 +342,7 @@ static int rsa_verify_key(struct image_sign_info *info, return -EINVAL; } - debug("Checksum algorithm: %s", checksum->name); + debug("Checksum algorithm: %s\n", checksum->name); /* Sanity check for stack size */ if (sig_len > RSA_MAX_SIG_BITS / 8) { -- 2.39.2

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[PATCH v4 0/7] Clean up arm linker scripts
by Ilias Apalodimas 29 Mar '24

29 Mar '24

The arm linker scripts had a mix of symbols and C defined variables in an effort to emit relative references instead of absolute ones e.g [0]. A linker bug prevented us from doing so [1] -- fixed since 2016. This has led to confusion over the years, ending up with mixed section definitions. Some sections are defined with overlays and different definitions between v7 and v8 architectures. For example __efi_runtime_rel_start/end is defined as a linker symbol for armv8 and a C variable in armv7. Linker scripts nowadays can emit relative references, as long as the symbol definition is contained within the section definition. So let's switch most of the C defined variables and clean up the arm sections.c file. There's still a few symbols remaining -- __secure_start/end, __secure_stack_start/end and __end which can be cleaned up in a followup series. For both QEMU v7/v8 bloat-o-meter shows now size difference $~ ./scripts/bloat-o-meter u-boot u-boot.new add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) Function old new delta Total: Before=798861, After=798861, chg +0.00% The symbols seem largely unchanged apart from a difference in .bss as well as the emited sections and object types of the affected variables. On the output below the first value is from -next and the second comes from -next + this patchset. The .bss_start/end sections have disappeared from the newer binaries. # For example on QEMU v8: efi_runtime_start 7945: 0000000000000178 0 OBJECT GLOBAL DEFAULT 2 __efi_runtime_start 7942: 0000000000000178 0 NOTYPE GLOBAL DEFAULT 2 __efi_runtime_start efi_runtime_stop 9050: 0000000000000d38 0 OBJECT GLOBAL DEFAULT 2 __efi_runtime_stop 9047: 0000000000000d38 0 NOTYPE GLOBAL DEFAULT 2 __efi_runtime_stop __efi_runtime_rel_start 7172: 00000000000dc2f0 0 OBJECT GLOBAL DEFAULT 10 __efi_runtime_rel_start 7169: 00000000000dc2f0 0 NOTYPE GLOBAL DEFAULT 10 __efi_runtime_rel_start __efi_runtime_rel_stop 7954: 00000000000dc4a0 0 OBJECT GLOBAL DEFAULT 10 __efi_runtime_rel_stop 7951: 00000000000dc4a0 0 NOTYPE GLOBAL DEFAULT 10 __efi_runtime_rel_stop __rel_dyn_start 7030: 00000000000dc4a0 0 OBJECT GLOBAL DEFAULT 11 __rel_dyn_start 7027: 00000000000dc4a0 0 NOTYPE GLOBAL DEFAULT 11 __rel_dyn_start __rel_dyn_end 8959: 0000000000102b10 0 OBJECT GLOBAL DEFAULT 12 __rel_dyn_end 8956: 0000000000102b10 0 NOTYPE GLOBAL DEFAULT 11 __rel_dyn_end image_copy_start 9051: 0000000000000000 0 OBJECT GLOBAL DEFAULT 1 __image_copy_start 9048: 0000000000000000 0 NOTYPE GLOBAL DEFAULT 1 __image_copy_start image_copy_end 7467: 00000000000dc4a0 0 OBJECT GLOBAL DEFAULT 11 __image_copy_end 7464: 00000000000dc4a0 0 NOTYPE GLOBAL DEFAULT 11 __image_copy_end bss_start 12: 0000000000102b10 0 SECTION LOCAL DEFAULT 12 .bss_start 8087: 0000000000000018 0 NOTYPE GLOBAL DEFAULT 1 _bss_start_ofs 8375: 0000000000102b10 0 OBJECT GLOBAL DEFAULT 12 __bss_start 8084: 0000000000000018 0 NOTYPE GLOBAL DEFAULT 1 _bss_start_ofs 8372: 0000000000102b10 0 NOTYPE GLOBAL DEFAULT 12 __bss_start bss_end 14: 000000000010bc30 0 SECTION LOCAL DEFAULT 14 .bss_end 7683: 000000000010bc30 0 OBJECT GLOBAL DEFAULT 14 __bss_end 8479: 0000000000000020 0 NOTYPE GLOBAL DEFAULT 1 _bss_end_ofs 7680: 000000000010bbb0 0 NOTYPE GLOBAL DEFAULT 12 __bss_end 8476: 0000000000000020 0 NOTYPE GLOBAL DEFAULT 1 _bss_end_ofs # For QEMU v7: efi_runtime_start 10703: 000003bc 0 OBJECT GLOBAL DEFAULT 2 __efi_runtime_start 10699: 000003c0 0 NOTYPE GLOBAL DEFAULT 2 __efi_runtime_start efi_runtime_stop 11796: 000012ec 0 OBJECT GLOBAL DEFAULT 2 __efi_runtime_stop 11792: 000012ec 0 NOTYPE GLOBAL DEFAULT 2 __efi_runtime_stop __efi_runtime_rel_start 9937: 000c40dc 0 OBJECT GLOBAL DEFAULT 8 __efi_runtime_rel_start 9935: 000c40dc 0 NOTYPE GLOBAL DEFAULT 9 __efi_runtime_rel_start __efi_runtime_rel_stop 10712: 000c41dc 0 OBJECT GLOBAL DEFAULT 10 __efi_runtime_rel_stop 10708: 000c41dc 0 NOTYPE GLOBAL DEFAULT 9 __efi_runtime_rel_stop __rel_dyn_start 9791: 000c41dc 0 OBJECT GLOBAL DEFAULT 10 __rel_dyn_start 9789: 000c41dc 0 NOTYPE GLOBAL DEFAULT 10 __rel_dyn_start __rel_dyn_end 11708: 000da5f4 0 OBJECT GLOBAL DEFAULT 10 __rel_dyn_end 11704: 000da5f4 0 NOTYPE GLOBAL DEFAULT 10 __rel_dyn_end image_copy_start 448: 0000177c 0 NOTYPE LOCAL DEFAULT 3 _image_copy_start_ofs 11797: 00000000 0 OBJECT GLOBAL DEFAULT 1 __image_copy_start 445: 0000177c 0 NOTYPE LOCAL DEFAULT 3 _image_copy_start_ofs 11793: 00000000 0 NOTYPE GLOBAL DEFAULT 1 __image_copy_start image_copy_end 450: 00001780 0 NOTYPE LOCAL DEFAULT 3 _image_copy_end_ofs 10225: 000c41dc 0 OBJECT GLOBAL DEFAULT 10 __image_copy_end 447: 00001780 0 NOTYPE LOCAL DEFAULT 3 _image_copy_end_ofs 10222: 000c41dc 0 NOTYPE GLOBAL DEFAULT 10 __image_copy_end bss_start 11: 000c41dc 0 SECTION LOCAL DEFAULT 11 .bss_start 11124: 000c41dc 0 OBJECT GLOBAL DEFAULT 11 __bss_start 11120: 000c41dc 0 NOTYPE GLOBAL DEFAULT 11 __bss_start bss_end 13: 000cbbf8 0 SECTION LOCAL DEFAULT 13 .bss_end 10442: 000cbbf8 0 OBJECT GLOBAL DEFAULT 13 __bss_end 10439: 000cbbf8 0 NOTYPE GLOBAL DEFAULT 11 __bss_end It's worth noting that since the efi regions are affected by the change, booting with EFI is preferable while testing. Booting the kernel only should be enough since the efi stub and the kernel proper do request boottime and runtime services respectively. Something along the lines of > virtio scan && load virtio 0 $kernel_addr_r Image && bootefi $kernel_addr_r will work for QEMU aarch64. Tested platforms: - QEMU aarch64 - Xilinx kv260 kria starter kit & zynq - QEMU armv7 - STM32MP157C-DK2 [0] commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated") [1] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for shared object") Ilias Apalodimas (7): arm: baltos: remove custom linker script arm: clean up v7 and v8 linker scripts for bss_start/end arm: fix __efi_runtime_rel_start/end definitions arm: clean up v7 and v8 linker scripts for __rel_dyn_start/end arm: fix __efi_runtime_start/end definitions arm: move image_copy_start/end to linker symbols arm: remove redundant section alignments arch/arm/cpu/armv8/u-boot-spl.lds | 26 ++-- arch/arm/cpu/armv8/u-boot.lds | 43 ++----- arch/arm/cpu/u-boot-spl.lds | 2 +- arch/arm/cpu/u-boot.lds | 72 +++-------- arch/arm/lib/sections.c | 10 -- arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 2 +- arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 23 ++-- arch/arm/mach-zynq/u-boot-spl.lds | 2 +- arch/arm/mach-zynq/u-boot.lds | 67 +++------- board/vscom/baltos/u-boot.lds | 128 -------------------- include/asm-generic/sections.h | 3 + lib/efi_loader/efi_runtime.c | 1 + 12 files changed, 71 insertions(+), 308 deletions(-) delete mode 100644 board/vscom/baltos/u-boot.lds -- Changes since v3: - ASSERT in the linker script if the .bss start address isn't 8b aligned instead of CONFIG_SPL_BSS_START_ADDR. This is a bit cleaerer and has no functional change Changes since v2: - Preserve the .bss alignment since it's needed by some C runtime setup code. The sdram .bss region for armv8 SPL is defined by a Kconfig option, so instead of aligning it explicitly assert if the Kconfig symbol is not 8b aligned - Align image_copy_end on patch #6. Richard I kept you r-b since that change was minimal, but some code assume the dtb will be appended which requires alignment. Please yell if you see something wrong - Added comments based on Richards review on why bss_start - bss_end needs to be divided by 4/8 (for armv7/8 respectively) Changes since v1: - bring back overlays for armv7 rel.dyn and bss sections and add a comment explaining why we overlay those - Remove redundant alignment from sections (new patch #7) - Added r-b tags from Sam Changes since RFC: - Rebase on top of -next and get rid of the dragonboard linker script changes. Caleb removed that file completely - Rewrite some commit messages to include the binutils bug details (thanks Sam) 2.37.2

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