September 2022 - U-Boot

[PATCH] xilinx: Fix mdio bus description for vck190-sc
by Michal Simek 12 Sep '22

12 Sep '22

Current behavior is that eth_phy_get_mdio_bus Net: FEC: can't find phy-handle ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Net: ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 4940825b002f..3fa18f560c9c 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -155,8 +155,12 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; - phy0: ethernet-phy@0 { /* u131 M88E1512 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@0 { /* u131 M88E1512 */ + reg = <0>; + }; }; }; -- 2.36.1

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[PATCH v2] ARM: zynq: DT: List OCM memory
by Michal Simek 12 Sep '22

12 Sep '22

Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high that's why it is placed on fixed location. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- Changes in v2: - Remove ocmc controller and use only OCM - Remove OCM setup from zc702 arch/arm/dts/zynq-7000.dtsi | 11 +++++++++++ arch/arm/dts/zynq-zc702.dts | 13 ------------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 11fa0ef2bfed..edc147d63f1e 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -192,6 +192,17 @@ reg = <0xf8006000 0x1000>; }; + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index f2e05a55b958..1bd4f8c9f661 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -64,19 +64,6 @@ }; }; -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffc0000 0x10000>; - ocm-sram@0 { - reg = <0x0 0x10000>; - }; - }; -}; - &can0 { status = "okay"; pinctrl-names = "default"; -- 2.36.1

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[PATCH] ARM: zynq: Align qspi node name with Linux kernel
by Michal Simek 12 Sep '22

12 Sep '22

Nodes should follow generic rules where compatible and reg properties should be listed on the top of node. That's why sync it up. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynq-7000.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index b4aa09d149b0..11fa0ef2bfed 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -235,13 +235,13 @@ }; qspi: spi@e000d000 { - clock-names = "ref_clk", "pclk"; - clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; - status = "disabled"; + reg = <0xe000d000 0x1000>; interrupt-parent = <&intc>; interrupts = <0 19 4>; - reg = <0xe000d000 0x1000>; + clocks = <&clkc 10>, <&clkc 43>; + clock-names = "ref_clk", "pclk"; + status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; @@ -378,9 +378,9 @@ devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; interrupt-parent = <&intc>; interrupts = <0 8 4>; - reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; -- 2.36.1

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[PATCH] cmd: bdinfo: Enable dumping lmb data when LMB is enabled
by Michal Simek 12 Sep '22

12 Sep '22

The commit 9996cea75f5a ("lmb/bdinfo: dump lmb info via bdinfo") added support for dumping LMB information as the part of bdinfo. But code itself should be called only when LMB is enabled. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- cmd/bdinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 9e23c4dd8fe5..af2e9757db50 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -130,7 +130,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) bdinfo_print_num_l("multi_dtb_fit", (ulong)gd->multi_dtb_fit); #endif - if (gd->fdt_blob) { + if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) { struct lmb lmb; lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); -- 2.36.1

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[PATCH] binman: Get futility by building it
by Simon Glass 12 Sep '22

12 Sep '22

A binary download is not great, since it depends on libraries being present in the system. Build futility from source instead. Note that this requires two patches to the source repo which are in progress: https://issuetracker.google.com/issues/245993083?pli=1 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/binman/bintool.py | 10 +++++++--- tools/binman/btool/futility.py | 9 ++++++--- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py index 032179a99de..a582d9d3446 100644 --- a/tools/binman/bintool.py +++ b/tools/binman/bintool.py @@ -319,7 +319,7 @@ class Bintool: return result.stdout @classmethod - def build_from_git(cls, git_repo, make_target, bintool_path): + def build_from_git(cls, git_repo, make_target, bintool_path, flags=None): """Build a bintool from a git repo This clones the repo in a temporary directory, builds it with 'make', @@ -330,6 +330,7 @@ class Bintool: make_target (str): Target to pass to 'make' to build the tool bintool_path (str): Relative path of the tool in the repo, after build is complete + flags (list of str): Flags or variables to pass to make, or None Returns: tuple: @@ -341,8 +342,11 @@ class Bintool: print(f"- clone git repo '{git_repo}' to '{tmpdir}'") tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir) print(f"- build target '{make_target}'") - tools.run('make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}', - make_target) + cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}', + make_target] + if flags: + cmd += flags + tools.run(*cmd) fname = os.path.join(tmpdir, bintool_path) if not os.path.exists(fname): print(f"- File '{fname}' was not produced") diff --git a/tools/binman/btool/futility.py b/tools/binman/btool/futility.py index 75a05c2ac66..f88139a0ab5 100644 --- a/tools/binman/btool/futility.py +++ b/tools/binman/btool/futility.py @@ -160,8 +160,11 @@ class Bintoolfutility(bintool.Bintool): Raises: Valuerror: Fetching could not be completed """ - if method != bintool.FETCH_BIN: + if method != bintool.FETCH_BUILD: return None - fname, tmpdir = self.fetch_from_drive( - '1hdsInzsE4aJbmBeJ663kYgjOQyW1I-E0') + result = self.build_from_git( + 'https://chromium.googlesource.com/a/chromiumos/platform/vboot_reference', + 'all', + 'build/futility/futility', + ['USE_FLASHROM=0']) return fname, tmpdir -- 2.37.2.789.g6183377224-goog

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[PATCH v2 0/3] i2c: stm32: cleanup & stop handling fix
by Alain Volmat 12 Sep '22

12 Sep '22

This series corrects the handling of the stop condition and cleanup few bits in the driver stm32f7_i2c.c v2: update commit message in patch 3/3 Alain Volmat (3): i2c: stm32: fix comment and remove unused AUTOEND bit i2c: stm32: remove unused stop parameter in start & reload handling i2c: stm32: only send a STOP upon transfer completion drivers/i2c/stm32f7_i2c.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) -- 2.25.1

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[PATCH v3 1/1] efi_driver: don't bind internal block devices
by Heinrich Schuchardt 12 Sep '22

12 Sep '22

UEFI block devices can either mirror U-Boot's internal devices or be provided by an EFI application like iPXE. When ConnectController() is invoked for the EFI_BLOCK_IO_PROTOCOL interface for such an application provided device we create a virtual U-Boot block device of type "efi_blk". Currently we do not call ConnectController() when handles for U-Boot's internal block devices are created. If an EFI application calls ConnectController() for a handle relating to an internal block device, we erroneously create an extra "efi_blk" block device. E.g. the UEFI shell has a command 'connect -r' which calls ConnectController() for all handles with device path protocol. In the Supported() method of our EFI_DRIVER_BINDING_PROTOCOL return EFI_UNSUPPORTED when dealing with an U-Boot internal device. Reported-by: Etienne Carriere <etienne.carriere(a)linaro.org> Fixes: commit 05ef48a2484b ("efi_driver: EFI block driver") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> Reviewed-by: Etienne Carriere <etienne.carriere(a)linaro.org> Tested-by: Etienne Carriere <etienne.carriere(a)linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- v3: return EFI_UNSUPPORTED changes Fixes: line v2: add code comment --- lib/efi_driver/efi_uclass.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c index b01ce89c84..1d7a0f57e3 100644 --- a/lib/efi_driver/efi_uclass.c +++ b/lib/efi_driver/efi_uclass.c @@ -71,6 +71,15 @@ static efi_status_t EFIAPI efi_uc_supported( EFI_ENTRY("%p, %p, %ls", this, controller_handle, efi_dp_str(remaining_device_path)); + /* + * U-Boot internal devices install protocols interfaces without calling + * ConnectController(). Hence we should not bind an extra driver. + */ + if (controller_handle->dev) { + ret = EFI_UNSUPPORTED; + goto out; + } + ret = EFI_CALL(systab.boottime->open_protocol( controller_handle, bp->ops->protocol, &interface, this->driver_binding_handle, -- 2.37.2

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[PATCH u-boot-marvell 0/5] mvebu important fixes
by Marek Behún 12 Sep '22

12 Sep '22

Hello Stefan, could you please test and send these patches to Tom for the next rc, if possible? I discovered that loadb does not work with higher speeds and lzmadec is way too slow, bisected to one of Pali's commits, and then Pali investigated that there are some issues with cache settings. Marek Pali Rohár (5): arm: mvebu: Fix function enable_caches arm: mvebu: Guard non-AXP code by checking for AXP arm: mvebu: lowlevel.S: Use CR_M from asm/system.h arm: mvebu: Enable L2 cache also on Armada 38x arm: mvebu: Fix moving internal registers arch/arm/include/asm/pl310.h | 9 +++++++-- arch/arm/mach-mvebu/cpu.c | 37 +++++++++++++++------------------- arch/arm/mach-mvebu/lowlevel.S | 30 ++++++++++++++++++++++++++- 3 files changed, 52 insertions(+), 24 deletions(-) -- 2.35.1

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[PATCH] ddr: socfpga: Add ECC DRAM scrubbing support for gen5
by teik.heng.chong＠intel.com 12 Sep '22

12 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- arch/arm/mach-socfpga/spl_gen5.c | 4 +++ drivers/ddr/altera/sdram_gen5.c | 57 ++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 287fbd1713..b79d8cbd5d 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -29,6 +29,8 @@ DECLARE_GLOBAL_DATA_PTR; +static struct bd_info bdata __section(".data"); + u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + @@ -148,6 +150,8 @@ void board_init_f(ulong dummy) /* enable console uart printing */ preloader_console_init(); + gd->bd = &bdata; + ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index 8d3ce495de..9d69f009e9 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -3,6 +3,7 @@ * Copyright Altera Corporation (C) 2014-2015 */ #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <errno.h> #include <div64.h> @@ -17,10 +18,14 @@ #include <asm/arch/system_manager.h> #include <asm/bitops.h> #include <asm/io.h> +#include <asm/system.h> #include <dm/device_compat.h> +#include <linux/sizes.h> #include "sequencer.h" +#define PGTABLE_OFF 0x4000 + #ifdef CONFIG_SPL_BUILD struct altera_gen5_sdram_priv { @@ -563,6 +568,54 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl) return temp; } +static int sdram_is_ecc_enabled(struct socfpga_sdr_ctrl *sdr_ctrl) +{ + return !!(readl(&sdr_ctrl->ctrl_cfg) & + SDR_CTRLGRP_CTRLCFG_ECCEN_MASK); +} + +/* Initialize SDRAM ECC bits to avoid false DBE */ +static void sdram_init_ecc_bits(phys_size_t size) +{ + phys_size_t start, size_init, start_addr; + + start = get_timer(0); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = size; + + gd->arch.tlb_addr = gd->bd->bi_dram[0].start + PGTABLE_OFF; + gd->arch.tlb_size = PGTABLE_SIZE; + + memset((void *)gd->bd->bi_dram[0].start, 0, gd->arch.tlb_addr + + gd->arch.tlb_size); + + icache_enable(); + dcache_enable(); + + printf("DDRCAL: Scrubbing ECC RAM (%lu MiB).\n", size >> 20); + + start_addr = gd->arch.tlb_addr + gd->arch.tlb_size; + size -= (gd->arch.tlb_addr + gd->arch.tlb_size); + + while (size > 0) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + memset((void *)start_addr, 0, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + + flush_dcache_all(); + + printf("DDRCAL: Scrubbing ECC RAM done.\n"); + + dcache_disable(); + + printf("DDRCAL: SDRAM-ECC initialized success with %d ms\n", + (u32)get_timer(start)); +} + static int altera_gen5_sdram_of_to_plat(struct udevice *dev) { struct altera_gen5_sdram_plat *plat = dev_get_plat(dev); @@ -605,6 +658,10 @@ static int altera_gen5_sdram_probe(struct udevice *dev) sdram_size = sdram_calculate_size(sdr_ctrl); debug("SDRAM: %ld MiB\n", sdram_size >> 20); + if (sdram_is_ecc_enabled(sdr_ctrl)) { + sdram_init_ecc_bits(sdram_size); + } + /* Sanity check ensure correct SDRAM size specified */ if (get_ram_size(0, sdram_size) != sdram_size) { puts("SDRAM size check failed!\n"); -- 2.26.2

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[PATCH 1/8] configs: HSD #1508104447-2: configs: socfpga: stratix10: Enable CONFIG_CMD_MTD
by Jit Loon Lim 11 Sep '22

11 Sep '22

From: Ley Foon Tan <ley.foon.tan(a)intel.com> Enable CONFIG_CMD_MTD. CONFIG_MTD_PARTITIONS is enabled by CONFIG_CMD_MTD. So, remove CONFIG_MTD_PARTITIONS from socfpga_stratix10_socdk.h. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_stratix10_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 07e9f20a41..39226a8b95 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/socfpga_stratix10_qspi_defconfig b/configs/socfpga_stratix10_qspi_defconfig index 6d41356fe0..27730db8c8 100644 --- a/configs/socfpga_stratix10_qspi_defconfig +++ b/configs/socfpga_stratix10_qspi_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y -- 2.26.2

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