September 2022 - U-Boot

[PATCH] arm: socfpga: Enable driver model for watchdog timer drivers
by Jit Loon Lim 11 Sep '22

11 Sep '22

From: Chee Hong Ang <chee.hong.ang(a)intel.com> All SoCFPGA platforms are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/dts/socfpga_stratix10_socdk.dts | 4 ++ ...efconfig => socfpga_agilex_nand_defconfig} | 43 ++++++++++++------- configs/socfpga_agilex_qspi_defconfig | 2 + 3 files changed, 34 insertions(+), 15 deletions(-) copy configs/{socfpga_agilex_qspi_defconfig => socfpga_agilex_nand_defconfig} (58%) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 8aa55a60ab..663adb42e6 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -137,3 +137,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/configs/socfpga_agilex_qspi_defconfig b/configs/socfpga_agilex_nand_defconfig similarity index 58% copy from configs/socfpga_agilex_qspi_defconfig copy to configs/socfpga_agilex_nand_defconfig index 8522e72cbc..4ca811b8d2 100644 --- a/configs/socfpga_agilex_qspi_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -5,33 +5,36 @@ CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x020C0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x00200000 CONFIG_DM_GPIO=y -CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SPL_TEXT_BASE=0xffe00000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -# CONFIG_PSCI_RESET is not set CONFIG_ARMV8_PSCI=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_qspi" -CONFIG_QSPI_BOOT=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand" +CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" -CONFIG_SPL_CACHE=y +CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run nandboot" +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -41,16 +44,25 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_BLK=y CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y -# CONFIG_MMC is not set +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND_DENALI_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y @@ -67,5 +79,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y \ No newline at end of file +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_qspi_defconfig b/configs/socfpga_agilex_qspi_defconfig index 8522e72cbc..03bfc1689b 100644 --- a/configs/socfpga_agilex_qspi_defconfig +++ b/configs/socfpga_agilex_qspi_defconfig @@ -67,5 +67,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y \ No newline at end of file -- 2.26.2

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[PATCH] arm: socfpga: increase QSPI kernel Image size for Stratix10 and Agilex
by Jit Loon Lim 11 Sep '22

11 Sep '22

From: Joyce Ooi <joyce.ooi(a)intel.com> This patch increases the allocated kernel Image size to 32MB for QSPI for Stratix10 and Agilex as the latest kernel size has increased. Signed-off-by: Joyce Ooi <joyce.ooi(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_qspi_defconfig | 2 +- configs/socfpga_stratix10_qspi_defconfig | 2 +- include/configs/socfpga_soc64_common.h | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/socfpga_agilex_qspi_defconfig b/configs/socfpga_agilex_qspi_defconfig index f9d38f6887..8522e72cbc 100644 --- a/configs/socfpga_agilex_qspi_defconfig +++ b/configs/socfpga_agilex_qspi_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x02080000 +CONFIG_ENV_OFFSET=0x020C0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_DM_GPIO=y diff --git a/configs/socfpga_stratix10_qspi_defconfig b/configs/socfpga_stratix10_qspi_defconfig index 161063f51d..6d41356fe0 100644 --- a/configs/socfpga_stratix10_qspi_defconfig +++ b/configs/socfpga_stratix10_qspi_defconfig @@ -6,7 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x02080000 +CONFIG_ENV_OFFSET=0x020C0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 CONFIG_DM_GPIO=y diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index c966d31362..d83686209c 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -37,9 +37,9 @@ * Environment variable */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "qspibootimageaddr=0x020B0000\0" \ - "qspifdtaddr=0x02090000\0" \ - "bootimagesize=0x01400000\0" \ + "qspibootimageaddr=0x020E0000\0" \ + "qspifdtaddr=0x020D0000\0" \ + "bootimagesize=0x01F00000\0" \ "fdtimagesize=0x00010000\0" \ "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ -- 2.26.2

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[PATCH 1/2] arch: arm: mach-socfpga: HSD #1508115548-1: Add SMMU status and Stream ID checking functions
by Jit Loon Lim 11 Sep '22

11 Sep '22

Add functions for checking SMMU bypass status and matching valid hardware device Stream ID in SMMU Stream Mapping Registers. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/include/mach/smmu_s10.h | 65 ++++++++++ arch/arm/mach-socfpga/smmu_s10.c | 118 ++++++++++++++++++ 2 files changed, 183 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/smmu_s10.h create mode 100644 arch/arm/mach-socfpga/smmu_s10.c diff --git a/arch/arm/mach-socfpga/include/mach/smmu_s10.h b/arch/arm/mach-socfpga/include/mach/smmu_s10.h new file mode 100644 index 0000000000..dfcc99f82a --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/smmu_s10.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2018 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/* SMMU registers */ +#define SMMU_SCR0 0 +#define SMMU_SIDR0 0x20 +#define SMMU_SIDR1 0x24 + +#define SMMU_SCR0_CLIENTPD BIT(0) +#define SMMU_SIDR0_NUMSMRG_MASK GENMASK(7, 0) +#define SMMU_SIDR1_NUMCB_MASK GENMASK(7, 0) + +/* Stream mapping registers */ +#define SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) +#define SMMU_SMR_VALID BIT(31) +#define SMMU_SMR_MASK GENMASK(30, 16) +#define SMMU_SMR_ID GENMASK(14, 0) + +#define SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) +#define SMMU_S2CR_TYPE GENMASK(17, 16) +#define SMMU_S2CR_CBNDX GENMASK(7, 0) + +/* Register groups for Context Bank */ +#define SMMU_GR0_CB(n, r) (0x20000 + ((n) << 12) + ((r) << 2)) +#define SMMU_CB_SCTLR 0 +#define SMMU_CB_SCTLR_M BIT(0) + +#define SMMU_SID_SDM2HPS_PSI_BE 0 + +void socfpga_init_smmu(void); +int is_smmu_bypass(void); +int is_smmu_stream_id_enabled(u32 stream_id); + +#define SMMU_SET_STREAMID(x, r, w) ((x << r) | (x << w)) + +#define SYSMGR_EMAC0_SID_ADDR 0xffd12050 /* EMAC0 (emac0_ace) */ +#define SYSMGR_EMAC1_SID_ADDR 0xffd12054 /* EMAC0 (emac1_ace) */ +#define SYSMGR_EMAC2_SID_ADDR 0xffd12058 /* EMAC0 (emac2_ace) */ +#define SYSMGR_NAND_SID_ADDR 0xffd1205c /* NAND (nand_axuser) */ +#define SYSMGR_SDMMC_SID_ADDR 0xffd1202c /* SDMMC (sdmmcgrp_l3master) */ +#define SYSMGR_USB0_SID_ADDR 0xffd12038 /* USB0 (usb0_l3master) */ +#define SYSMGR_USB1_SID_ADDR 0xffd1203c /* USB0 (usb1_l3master) */ +#define SYSMGR_DMA_SID_ADDR 0xffd12074 /* DMA (dma_l3master) */ +#define SYSMGR_ETR_SID_ADDR 0xffd12078 /* ETR (etr_l3master) */ +/* Stream ID field offsets */ +#define EMAC_W_OFST 20 +#define EMAC_R_OFST 8 +#define NAND_W_OFST 0 +#define NAND_R_OFST 16 +#define SDMMC_OFST 16 +#define USB_OFST 16 +#define DMA_W_OFST 0 +#define DMA_R_OFST 16 +#define ETR_W_OFST 0 +#define ETR_R_OFST 16 +struct smmu_stream_id { + unsigned long addr; + u32 sid; + u32 r_bit_ofst; + u32 w_bit_ofst; + u32 secure_bit_offset; +}; \ No newline at end of file diff --git a/arch/arm/mach-socfpga/smmu_s10.c b/arch/arm/mach-socfpga/smmu_s10.c new file mode 100644 index 0000000000..d6ab39755d --- /dev/null +++ b/arch/arm/mach-socfpga/smmu_s10.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2018 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/firewall.h> +#include <asm/arch/smmu_s10.h> +#include <asm/arch/system_manager.h> +DECLARE_GLOBAL_DATA_PTR; +static const struct smmu_stream_id dev_stream_id[] = { + {SYSMGR_EMAC0_SID_ADDR, 0x01, EMAC_W_OFST, EMAC_R_OFST}, + {SYSMGR_EMAC1_SID_ADDR, 0x02, EMAC_W_OFST, EMAC_R_OFST}, + {SYSMGR_EMAC2_SID_ADDR, 0x03, EMAC_W_OFST, EMAC_R_OFST}, + {SYSMGR_NAND_SID_ADDR, 0x04, NAND_W_OFST, NAND_R_OFST}, + {SYSMGR_SDMMC_SID_ADDR, 0x05, SDMMC_OFST, SDMMC_OFST}, + {SYSMGR_USB0_SID_ADDR, 0x06, USB_OFST, USB_OFST}, + {SYSMGR_USB1_SID_ADDR, 0x07, USB_OFST, USB_OFST}, + {SYSMGR_DMA_SID_ADDR, 0x08, DMA_W_OFST, DMA_R_OFST}, + {SYSMGR_ETR_SID_ADDR, 0x09, ETR_W_OFST, ETR_R_OFST}, +}; +static void set_smmu_streamid(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(dev_stream_id); i++) { + u32 mask = SMMU_SET_STREAMID(0x3FF, + dev_stream_id[i].r_bit_ofst, + dev_stream_id[i].w_bit_ofst); + u32 value = SMMU_SET_STREAMID(dev_stream_id[i].sid, + dev_stream_id[i].r_bit_ofst, + dev_stream_id[i].w_bit_ofst); + clrbits_le32(dev_stream_id[i].addr, mask); + setbits_le32(dev_stream_id[i].addr, value); + } +} +/* + * Need to set the Secure bit (to make it non-secure) on each peripheral + * so that SMMU can access the peripheral + */ +static void set_smmu_accessible_reg(void) +{ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0, + BIT(27) | BIT(25)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1, + BIT(27) | BIT(25)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2, + BIT(27) | BIT(25)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NANDGRP_L3MASTER, + BIT(21) | BIT(17)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_L3MASTER, + BIT(5)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB0_L3MASTER, + BIT(9)); + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB1_L3MASTER, + BIT(9)); +} +static inline void setup_smmu_firewall(void) +{ + /* Enable nonsecure SMMU accesses */ + writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); +} +void socfpga_init_smmu(void) +{ + setup_smmu_firewall(); + set_smmu_streamid(); + set_smmu_accessible_reg(); +} + +int is_smmu_bypass(void) +{ + return readl(SOCFPGA_SMMU_ADDRESS + SMMU_SCR0) & SMMU_SCR0_CLIENTPD; +} + +int is_smmu_stream_id_enabled(u32 stream_id) +{ + int i; + u32 smrg_num; + u32 smr, s2cr, sid_mask; + u32 cb, cb_index, cb_num; + + if (is_smmu_bypass()) + return 0; + + /* Get number of Stream Mapping Register Groups */ + smrg_num = readl(SOCFPGA_SMMU_ADDRESS + SMMU_SIDR0) & + SMMU_SIDR0_NUMSMRG_MASK; + + /* Get number of Context Bank */ + cb_num = readl(SOCFPGA_SMMU_ADDRESS + SMMU_SIDR1) & + SMMU_SIDR1_NUMCB_MASK; + + for (i = 0; i < smrg_num; i++) { + smr = readl(SOCFPGA_SMMU_ADDRESS + SMMU_GR0_SMR((u64)i)); + sid_mask = (smr & SMMU_SMR_MASK) >> 16; + + /* Skip if Stream ID is invalid or not matched */ + if (!(smr & SMMU_SMR_VALID) || (smr & sid_mask) != stream_id) + continue; + + /* Get Context Bank index from valid matching Stream ID */ + s2cr = readl(SOCFPGA_SMMU_ADDRESS + SMMU_GR0_S2CR((u64)i)); + cb_index = s2cr & SMMU_S2CR_CBNDX; + + /* Skip if Context Bank is invalid or not Translation mode */ + if (cb_index >= cb_num || (s2cr & SMMU_S2CR_TYPE)) + continue; + + cb = readl(SOCFPGA_SMMU_ADDRESS + SMMU_GR0_CB((u64)cb_index, + SMMU_CB_SCTLR)); + /* Return MMU enable status for this Context Bank */ + return (cb & SMMU_CB_SCTLR_M); + } + + return 0; +} \ No newline at end of file -- 2.26.2

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[PATCH] configs: socfpga: agilex: Enable CONFIG_SPL_CACHE in NAND defconfig
by Jit Loon Lim 11 Sep '22

11 Sep '22

add new CONFIG_SPL_CACHE for SPL build. Enable it to allow cache driver build in SPL for Agilex NAND defconfig. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_nand_defconfig | 84 +++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 configs/socfpga_agilex_nand_defconfig diff --git a/configs/socfpga_agilex_nand_defconfig b/configs/socfpga_agilex_nand_defconfig new file mode 100644 index 0000000000..65477ba0a0 --- /dev/null +++ b/configs/socfpga_agilex_nand_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x00200000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xffe00000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_ARMV8_PSCI=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand" +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run nandboot" +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND_DENALI_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set \ No newline at end of file -- 2.26.2

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[PATCH 1/7] configs: HSD #1507526426-2: configs: socfpga: agilex: Enable CONFIG_CMD_MTD
by Jit Loon Lim 11 Sep '22

11 Sep '22

From: Ley Foon Tan <ley.foon.tan(a)intel.com> Enable CONFIG_CMD_MTD. CONFIG_MTD_PARTITIONS is enabled by CONFIG_CMD_MTD. So, remove CONFIG_MTD_PARTITIONS from socfpga_agilex_socdk.h. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index bdfe764d9e..c7b203fece 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -53,6 +53,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index e2d869610c..bd6360a0a4 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -47,6 +47,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y -- 2.26.2

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[PATCH] arch: arm: mach-socfpga: HSD #1707102234: Agilex: Disable MPFE HMC Adapter Firewall
by Jit Loon Lim 11 Sep '22

11 Sep '22

From: Thor Thayer <thor.thayer(a)linux.intel.com> Disable the MPFE HMC Adapter Firewall for the MPU because the Linux SDRAM ECC needs to access that register. Also cleanup the HMC Firewall added for SMMU. Signed-off-by: Thor Thayer <thor.thayer(a)linux.intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/firewall.c | 10 ++++++++++ arch/arm/mach-socfpga/include/mach/firewall.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 69229dc651..c6c41b2134 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -104,4 +104,14 @@ void firewall_setup(void) socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA); writel(SYSMGR_DMAPERIPH_ALL_NS, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH); + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX + /* Disable the MPFE Firewall for SMMU */ + writel(FIREWALL_MPFE_SCR_DISABLE_ALL, SOCFPGA_FW_MPFE_SCR_ADDRESS + + FW_MPFE_SCR_HMC); + /* Disable MPFE Firewall for HMC adapter (ECC) */ + writel(FIREWALL_MPFE_SCR_DISABLE_MPU, SOCFPGA_FW_MPFE_SCR_ADDRESS + + FW_MPFE_SCR_HMC_ADAPTOR); +#endif + } diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 5cb7f23f8f..e45acb6501 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -75,6 +75,7 @@ struct socfpga_firwall_l4_sys { }; #define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) +#define FIREWALL_MPFE_SCR_DISABLE_MPU BIT(0) #define FIREWALL_BRIDGE_DISABLE_ALL (~0) /* Cache coherency unit (CCU) registers */ @@ -126,6 +127,10 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff +/* Firewall MPFE SCR Registers */ +#define FW_MPFE_SCR_HMC 0x00 +#define FW_MPFE_SCR_HMC_ADAPTOR 0x04 + #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) -- 2.26.2

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[PATCH] arch: arm: mach-socfpga: HSD #1707095796: Remove MPFE Firewall for SMMU
by Jit Loon Lim 11 Sep '22

11 Sep '22

From: Thor Thayer <thor.thayer(a)linux.intel.com> Remove firewall on MPFE so that SMMU can setup/walk tables in the DDR. Signed-off-by: Thor Thayer <thor.thayer(a)linux.intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/firewall.c | 6 ++++++ arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 + arch/arm/mach-socfpga/include/mach/firewall.h | 1 + 3 files changed, 8 insertions(+) diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 69229dc651..bbfcdbd9ae 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -104,4 +104,10 @@ void firewall_setup(void) socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA); writel(SYSMGR_DMAPERIPH_ALL_NS, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH); + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX + /* Disable the MPFE Firewall for SMMU */ + writel(FIREWALL_MPFE_SCR_DISABLE_ALL, SOCFPGA_FW_MPFE_SCR_ADDRESS); +#endif + } diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 3f899fcfa3..45c6458597 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,6 +10,7 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 5cb7f23f8f..885c04c27f 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -75,6 +75,7 @@ struct socfpga_firwall_l4_sys { }; #define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) +#define FIREWALL_MPFE_SCR_DISABLE_ALL (BIT(0) | BIT(8) | BIT(16)) #define FIREWALL_BRIDGE_DISABLE_ALL (~0) /* Cache coherency unit (CCU) registers */ -- 2.26.2

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[PATCH] scripts: config_whitelist: CONFIG_SYS_FLASH_AUTOPROTECT_LIST
by Sergei Antonov 10 Sep '22

10 Sep '22

CONFIG_SYS_FLASH_AUTOPROTECT_LIST is a feature of drivers/mtd/cfi_flash.c driver. It allows to specify a range of protected eraseblocks on flash memory. Fixes build error: Error: You must add new CONFIG options using Kconfig The following new ad-hoc CONFIG options were detected: CONFIG_SYS_FLASH_AUTOPROTECT_LIST Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- scripts/config_whitelist.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 22a0f2bf8a5d..d2e4e5375baf 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -633,6 +633,7 @@ CONFIG_SYS_FLASH0 CONFIG_SYS_FLASH1 CONFIG_SYS_FLASH1_BASE_PHYS CONFIG_SYS_FLASH1_BASE_PHYS_EARLY +CONFIG_SYS_FLASH_AUTOPROTECT_LIST CONFIG_SYS_FLASH_BANKS_LIST CONFIG_SYS_FLASH_BANKS_SIZES CONFIG_SYS_FLASH_BASE -- 2.34.1

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Pull request for efi-2022-10-rc5
by Heinrich Schuchardt 10 Sep '22

10 Sep '22

Dear Tom, The following changes since commit e9de8c8c649044080371399a1ef4923b08632611: Merge tag 'u-boot-stm32-20220907' of https://source.denx.de/u-boot/custodians/u-boot-stm (2022-09-08 08:33:41 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2022-10-rc5 for you to fetch changes up to 8cf8ad353345cc4a92288b5136e7d714d2bdde4a: efi_driver: don't bind internal block devices (2022-09-09 16:07:54 +0200) Gitlab CI showed no issues: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/13403 ---------------------------------------------------------------- Pull request for efi-2022-10-rc5 Documentation: * man-page for tftpput UEFI: * fix driver binding protocol for block IO devices * don't delete invalid handles * add a unit test for the EFI Conformance Profile Table Other: * correct short text for tftpboot ---------------------------------------------------------------- Etienne Carriere (1): lib: efi_loader: don't delete invalid handles Heinrich Schuchardt (6): cmd: fix tftpput command cmd: correct short text for tftpboot doc: man-page for tftpput efi_selftest: export efi_st_get_config_table() efi_selftest: unit test for EFI Conformance Profile Table efi_driver: don't bind internal block devices cmd/Kconfig | 2 +- cmd/net.c | 92 ++++++++++++++++++++++++++---------- doc/usage/cmd/tftpput.rst | 87 ++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + include/efi_selftest.h | 11 +++++ lib/efi_driver/efi_uclass.c | 9 ++++ lib/efi_loader/efi_boottime.c | 9 +++- lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest.c | 38 +++++++-------- lib/efi_selftest/efi_selftest_ecpt.c | 76 +++++++++++++++++++++++++++++ lib/efi_selftest/efi_selftest_fdt.c | 17 ------- lib/efi_selftest/efi_selftest_util.c | 11 +++++ 12 files changed, 290 insertions(+), 64 deletions(-) create mode 100644 doc/usage/cmd/tftpput.rst create mode 100644 lib/efi_selftest/efi_selftest_ecpt.c

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[PATCH] arm: dts: imx8mm-venice-gw7902: add dig1_ctl and dig2_ctl gpios
by Tim Harvey 10 Sep '22

10 Sep '22

The GW7902 revision B adds two additional GPIO's to control the direction of the 2 isolated digital I/O circuits. Define them as: - dig1_ctl - dig2_ctl Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mm-venice-gw7903.dts | 4 +++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi index 896e5d4edde3..ff9b12a83408 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi @@ -43,6 +43,20 @@ line-name = "dig2_out#"; }; + dig2ctl { + gpio-hog; + output-low; + gpios = <2 GPIO_ACTIVE_HIGH>; + line-name = "dig2_ctl"; + }; + + dig1ctl { + gpio-hog; + output-low; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "dig1_ctl"; + }; + dig1out { gpio-hog; output-high; diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts index a7dae9bd4c11..1b69ac0e12b0 100644 --- a/arch/arm/dts/imx8mm-venice-gw7903.dts +++ b/arch/arm/dts/imx8mm-venice-gw7903.dts @@ -250,7 +250,7 @@ }; &gpio2 { - gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "", + gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "", "dig1_out#", "dig1_in", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; @@ -630,6 +630,8 @@ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */ + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */ MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ -- 2.25.1

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