September 2022 - U-Boot

[PATCH v2 09/11] arm: dts: rockchip: sync rk3066/rk3188 DT files from Linux
by Johan Jonker 09 Sep '22

09 Sep '22

Sync rk3066/rk3188 DT files from Linux. This is the state as of v5.18 in Linux + nfc node for MK808 rk3066a. CRU nodes now have a clock property. To prefend dtoc errors a fixed clock must also be included for tpl/spl in the rk3xxx-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3066a-mk808.dts | 18 ++++++++++++++++++ arch/arm/dts/rk3066a.dtsi | 3 ++- arch/arm/dts/rk3188-radxarock.dts | 3 +-- arch/arm/dts/rk3188.dtsi | 24 +++++++++++++++--------- arch/arm/dts/rk3xxx-u-boot.dtsi | 4 ++++ 5 files changed, 40 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/rk3066a-mk808.dts b/arch/arm/dts/rk3066a-mk808.dts index 667d57a4..cfa318a5 100644 --- a/arch/arm/dts/rk3066a-mk808.dts +++ b/arch/arm/dts/rk3066a-mk808.dts @@ -160,6 +160,24 @@ status = "okay"; }; +&nfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + label = "rk-nand"; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <1024>; + nand-ecc-strength = <40>; + nand-is-boot-medium; + rockchip,boot-blks = <8>; + rockchip,boot-ecc-strength = <24>; + }; +}; + &pinctrl { usb-host { host_drv: host-drv { diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi index c25b9695..de9915d9 100644 --- a/arch/arm/dts/rk3066a.dtsi +++ b/arch/arm/dts/rk3066a.dtsi @@ -202,8 +202,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index e7138a4a..a9ed3cd2 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -6,7 +6,6 @@ /dts-v1/; #include <dt-bindings/input/input.h> #include "rk3188.dtsi" -#include "rk3188-radxarock-u-boot.dtsi" / { model = "Radxa Rock"; @@ -25,7 +24,7 @@ compatible = "gpio-keys"; autorepeat; - power { + key-power { gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 9a80f83a..cdd4a0bd 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -54,7 +54,7 @@ }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -195,8 +195,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; }; @@ -223,7 +224,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@2000a000 { + gpio0: gpio@2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -236,7 +237,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@2003c000 { + gpio1: gpio@2003c000 { compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -249,7 +250,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@2003e000 { + gpio2: gpio@2003e000 { compatible = "rockchip,gpio-bank"; reg = <0x2003e000 0x100>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -262,7 +263,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio3@20080000 { + gpio3: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -275,15 +276,15 @@ #interrupt-cells = <2>; }; - pcfg_pull_up: pcfg_pull_up { + pcfg_pull_up: pcfg-pull-up { bias-pull-up; }; - pcfg_pull_down: pcfg_pull_down { + pcfg_pull_down: pcfg-pull-down { bias-pull-down; }; - pcfg_pull_none: pcfg_pull_none { + pcfg_pull_none: pcfg-pull-none { bias-disable; }; @@ -641,6 +642,11 @@ &grf { compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; + io_domains: io-domains { + compatible = "rockchip,rk3188-io-voltage-domain"; + status = "disabled"; + }; + usbphy: usbphy { compatible = "rockchip,rk3188-usb-phy"; #address-cells = <1>; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi index e67432fb..c77d1fae 100644 --- a/arch/arm/dts/rk3xxx-u-boot.dtsi +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -33,3 +33,7 @@ &uart2 { clock-frequency = <24000000>; }; + +&xin24m { + u-boot,dm-pre-reloc; +}; -- 2.20.1

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[PATCH v2] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files
by Johan Jonker 09 Sep '22

09 Sep '22

Move all rk3128 u-boot specific properties in separate dtsi files. Sort emmc node. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Changed V2: Keep max-frequency property in dtsi --- arch/arm/dts/rk3128-evb-u-boot.dtsi | 7 +++++++ arch/arm/dts/rk3128-evb.dts | 10 +++++----- arch/arm/dts/rk3128-u-boot.dtsi | 19 +++++++++++++++++++ arch/arm/dts/rk3128.dtsi | 9 --------- 4 files changed, 31 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/rk3128-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3128-u-boot.dtsi diff --git a/arch/arm/dts/rk3128-evb-u-boot.dtsi b/arch/arm/dts/rk3128-evb-u-boot.dtsi new file mode 100644 index 00000000..8b16bbe4 --- /dev/null +++ b/arch/arm/dts/rk3128-evb-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3128-u-boot.dtsi" + +&emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index a407ac2d..e7d8f7c9 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -37,6 +37,11 @@ }; }; +&emmc { + fifo-mode; + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -74,11 +79,6 @@ status = "okay"; }; -&emmc { - fifo-mode; - status = "okay"; -}; - &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi new file mode 100644 index 00000000..4a98e249 --- /dev/null +++ b/arch/arm/dts/rk3128-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rockchip-u-boot.dtsi" + +/ { + dmc: dmc@20004000 { + compatible = "rockchip,rk3128-dmc", "syscon"; + reg = <0x0 0x20004000 0x0 0x1000>; + u-boot,dm-pre-reloc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 62fd5343..760c98b6 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -237,14 +237,7 @@ clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; }; - dmc: dmc@20004000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3128-dmc", "syscon"; - reg = <0x0 0x20004000 0x0 0x1000>; - }; - cru: clock-controller@20000000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-cru"; reg = <0x20000000 0x1000>; rockchip,grf = <&grf>; @@ -453,7 +446,6 @@ }; emmc: dwmmc@1021c000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; max-frequency = <150000000>; @@ -538,7 +530,6 @@ }; grf: syscon@20008000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3128-grf", "syscon"; reg = <0x20008000 0x1000>; }; -- 2.20.1

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[PATCH] [RFC] lib: efi_loader: don't delete invalid handles
by Etienne Carriere 09 Sep '22

09 Sep '22

Changes efi_delete_handle() to not free EFI handles that are not related to EFI objects. This change tries to resolved an issue seen since U-Boot v2022.07 in which EFI ExitBootService attempts to release some EFI handles twice. The issue was seen booting a EFI shell that invokes 'connect -r' and then boots a Linux kernel. Execution of connect command makes EFI subsystem to bind a block device for each root block devices EFI handles. However these EFI device handles are already bound to a driver and we can have 2 registered devices relating to the same EFI handler. On ExitBootService, the loop removing the devices makes these EFI handles to be released twice which corrupts memory. This patch prevents the memory release operation caused by the issue but I don't think this patch is the right way to addresse the problem. Any help will be much appreciated. Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> --- lib/efi_loader/efi_boottime.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 4da64b5d29..e38990ace2 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -619,9 +619,15 @@ efi_status_t efi_remove_all_protocols(const efi_handle_t handle) */ void efi_delete_handle(efi_handle_t handle) { + efi_status_t ret; + if (!handle) return; - efi_remove_all_protocols(handle); + + ret = efi_remove_all_protocols(handle); + if (ret == EFI_INVALID_PARAMETER) + return; + list_del(&handle->link); free(handle); } -- 2.25.1

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[PATCH 0/2] mmc: Add support for F_SDH30_E51
by Kunihiko Hayashi 09 Sep '22

09 Sep '22

This series adds a new quirk "SUPPORT_SINGLE" for single transaction to sdhci framework and Socionext F_SDH30_E51 IP support to f_sdh30 driver. Kunihiko Hayashi (2): mmc: sdhci: Add new quirks for SUPPORT_SINGLE mmc: f_sdh30: Add support for F_SDH30_E51 drivers/mmc/Kconfig | 4 +-- drivers/mmc/f_sdh30.c | 64 +++++++++++++++++++++++++++++++++++++++++-- drivers/mmc/sdhci.c | 8 ++++-- include/sdhci.h | 1 + 4 files changed, 70 insertions(+), 7 deletions(-) -- 2.17.1

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[PATCH] arch: arm: mach-socfpga: To notify SDM when SPL pass control to U-Boot
by Jit Loon Lim 09 Sep '22

09 Sep '22

From: Chin Liang See <chin.liang.see(a)intel.com> Prior SPL pass control to U-Boot, SPL will send a mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on HPS SW transition. The purpose is for debug as user can query SDM on HPS error details when HPS enters a warm reset due to error such as watchdog. Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/spl_s10.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index c20e87cdbe..9bfd1a0f6a 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -92,3 +92,9 @@ void board_init_f(ulong dummy) mbox_qspi_open(); #endif } + +/* board specific function prior loading SSBL / U-Boot */ +void spl_board_prepare_for_boot(void) +{ + mbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); +} -- 2.26.2

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[PATCH] arch: arm: mach-socfpga: Add mailbox command for HPS execution stage notification
by Jit Loon Lim 09 Sep '22

09 Sep '22

From: Chin Liang See <chin.liang.see(a)intel.com> Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on the stage of HPS code execution. In general, there are three main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System which is Linux Signed-off-by: Chin Liang See <chin.liang.see(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++ arch/arm/mach-socfpga/mailbox_s10.c | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index fbaf11597e..87af6f1cfe 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -123,6 +123,7 @@ enum ALT_SDM_MBOX_RESP_CODE { #define MBOX_QSPI_CLOSE 51 #define MBOX_QSPI_DIRECT 59 #define MBOX_REBOOT_HPS 71 +#define MBOX_HPS_STAGE_NOTIFY 93 /* Mailbox registers */ #define MBOX_CIN 0 /* command valid offset */ @@ -166,6 +167,11 @@ enum ALT_SDM_MBOX_RESP_CODE { #define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) #define RCF_PIN_STATUS_NSTATUS BIT(31) +/* Defines for HPS_STAGE_NOTIFY */ +#define HPS_EXECUTION_STATE_FSBL 0 +#define HPS_EXECUTION_STATE_SSBL 1 +#define HPS_EXECUTION_STATE_OS 2 + int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, u32 *resp_buf); int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, @@ -182,6 +188,7 @@ int mbox_qspi_open(void); #endif int mbox_reset_cold(void); +int mbox_hps_stage_notify(u32 execution_stage); int mbox_get_fpga_config_status(u32 cmd); int mbox_get_fpga_config_status_psci(u32 cmd); #endif /* _MAILBOX_S10_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 101af23855..e86d9bf214 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -479,6 +479,12 @@ int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, urgent, resp_buf_len, resp_buf); } +int mbox_hps_stage_notify(u32 execution_stage) +{ + return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY, + MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL); +} + int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) { return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); -- 2.26.2

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[PATCH] board: gateworks: venice: update GW74xx PMIC config
by Tim Harvey 08 Sep '22

08 Sep '22

Update the GW74xx PMIC configuration. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/venice/spl.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 56a985ed668f..eadb58f9ac75 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -153,20 +153,18 @@ static int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ dm_i2c_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - /* Buck 1 DVS control through PMIC_STBY_REQ */ - dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - /* Set DVS1 to 0.8v for suspend */ - dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + /* increase VDD_SOC to 0.95V before first DRAM access */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); - /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ - dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + /* Set DVS1 to 0.85v for suspend */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); - /* VDD_DRAM off in suspend: B1_ENMODE=10 */ - dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); + /* Enable DVS control through PMIC_STBY_REQ */ + dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - /* set VDD_SNVS_0V8 from default 0.85V */ - dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */ + dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* set WDOG_B_CFG to cold reset */ dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); -- 2.25.1

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[PULL] Pull request for u-boot master / v2022.10 = u-boot-stm32-20220907
by Patrick DELAUNAY 08 Sep '22

08 Sep '22

Hi Tom, Please pull the STM32 related fixes for u-boot/master, v2022.10: u-boot-stm32-20220907 - simplify the STM32MP15x package parsing code - remove test on CONFIG_DM_REGULATOR in stm32mp1 board and enable CONFIG_DM_REGULATOR for stm32f769-disco - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start' after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>) - Fix SYS_HZ_CLOCK value for stih410-b2260 board - Switch STMM32MP15x DHSOM to FMC2 EBI driver - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/13383 Thanks, Patrick git request-pull origin/master https://source.denx.de/u-boot/custodians/u-boot-stm.git/ u-boot-stm32-20220907 The following changes since commit 51601397fcbb13e6dc2e4223408230c82955a601: Prepare v2022.10-rc4 (2022-09-05 20:32:56 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git/ tags/u-boot-stm32-20220907 for you to fetch changes up to d6ff3c9f04f744345fe77a3d82c5b5e0c07c456a: ARM: dts: stm32mp15: remove hwlocks from pinctrl (2022-09-06 15:40:14 +0200) ---------------------------------------------------------------- - simplify the STM32MP15x package parsing code - remove test on CONFIG_DM_REGULATOR in stm32mp1 board and enable CONFIG_DM_REGULATOR for stm32f769-disco - handle ck_usbo_48m clock provided by USBPHYC to fix the command 'usb start' after alignment with Linux kernel v5.19 DT (clocks = <&usbphyc>) - Fix SYS_HZ_CLOCK value for stih410-b2260 board - Switch STMM32MP15x DHSOM to FMC2 EBI driver - Remove hwlocks from pinctrl in STM32MP15x to avoid issue with kernel ---------------------------------------------------------------- Etienne Carriere (1): ARM: dts: stm32mp15: remove hwlocks from pinctrl Marek Vasut (1): ARM: stm32: Switch DHSOM to FMC2 EBI driver Patrice Chotard (3): ARM: dts: stm32: Fix display-timings settings for stm32f746-disco configs: stm32: Enable CONFIG_DM_REGULATOR for stm32f769-disco configs: stih410-b2260: Fix SYS_HZ_CLOCK value Patrick Delaunay (5): stm32mp: simplify the STM32MP15x package parsing code board: stm32mp1: remove test on CONFIG_DM_REGULATOR phy: stm32-usbphyc: add counter of PLL consumer phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clock clk: stm32mp: handle ck_usbo_48m clock provided by USBPHYC arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 +- arch/arm/dts/stm32mp151.dtsi | 2 -- arch/arm/dts/stm32mp15xx-dhcom-picoitx-u-boot.dtsi | 8 ----- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 14 --------- arch/arm/dts/stm32mp15xx-dhcor-drc-compact-u-boot.dtsi | 16 ---------- arch/arm/mach-stm32mp/stm32mp15x.c | 15 ++-------- board/dhelectronics/dh_stm32mp1/board.c | 52 -------------------------------- board/st/stm32mp1/stm32mp1.c | 8 ++--- configs/stm32f769-disco_defconfig | 1 + configs/stm32f769-disco_spl_defconfig | 1 + configs/stm32mp15_dhcom_basic_defconfig | 1 + configs/stm32mp15_dhcor_basic_defconfig | 1 + drivers/clk/stm32/clk-stm32mp1.c | 35 ++++++++++++---------- drivers/phy/phy-stm32-usbphyc.c | 155 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------- include/configs/stih410-b2260.h | 2 +- 15 files changed, 158 insertions(+), 155 deletions(-)

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[tom.rini@gmail.com: Fwd: New Defects reported by Coverity Scan for Das U-Boot]
by Tom Rini 08 Sep '22

08 Sep '22

And here's the most recent one. ----- Forwarded message from Tom Rini <tom.rini(a)gmail.com> ----- Date: Wed, 24 Aug 2022 07:38:55 -0400 From: Tom Rini <tom.rini(a)gmail.com> To: trini(a)konsulko.com Subject: Fwd: New Defects reported by Coverity Scan for Das U-Boot ---------- Forwarded message --------- From: <scan-admin(a)coverity.com> Date: Mon, Aug 22, 2022 at 7:07 PM Subject: New Defects reported by Coverity Scan for Das U-Boot To: <tom.rini(a)gmail.com> Hi, Please find the latest report on new defect(s) introduced to Das U-Boot found with Coverity Scan. 3 new defect(s) introduced to Das U-Boot found with Coverity Scan. 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 3 of 3 defect(s) ** CID 356244: Null pointer dereferences (FORWARD_NULL) ________________________________________________________________________________________________________ *** CID 356244: Null pointer dereferences (FORWARD_NULL) /boot/vbe.c: 46 in vbe_find_first_device() 40 int vbe_find_first_device(struct udevice **devp) 41 { 42 uclass_find_first_device(UCLASS_BOOTMETH, devp); 43 if (*devp && is_vbe(*devp)) 44 return 0; 45 >>> CID 356244: Null pointer dereferences (FORWARD_NULL) >>> Passing "devp" to "vbe_find_next_device", which dereferences null "*devp". 46 return vbe_find_next_device(devp); 47 } 48 49 int vbe_list(void) 50 { 51 struct bootstd_priv *std; ** CID 356243: Code maintainability issues (UNUSED_VALUE) /boot/vbe_simple.c: 237 in bootmeth_vbe_simple_ft_fixup() ________________________________________________________________________________________________________ *** CID 356243: Code maintainability issues (UNUSED_VALUE) /boot/vbe_simple.c: 237 in bootmeth_vbe_simple_ft_fixup() 231 /* 232 * Ideally we would have driver model support for fixups, but that does 233 * not exist yet. It is a step too far to try to do this before VBE is 234 * in place. 235 */ 236 for (ret = vbe_find_first_device(&dev); dev; >>> CID 356243: Code maintainability issues (UNUSED_VALUE) >>> Assigning value from "vbe_find_next_device(&dev)" to "ret" here, but that stored value is overwritten before it can be used. 237 ret = vbe_find_next_device(&dev)) { 238 struct simple_state state; 239 240 if (strcmp("vbe_simple", dev->driver->name)) 241 continue; 242 ** CID 356242: (TAINTED_SCALAR) ________________________________________________________________________________________________________ *** CID 356242: (TAINTED_SCALAR) /test/dm/ofnode.c: 501 in make_ofnode_fdt() 495 ut_assertok(fdt_end_node(fdt)); 496 497 ut_assert(fdt_begin_node(fdt, "new-mmc") >= 0); 498 ut_assertok(fdt_end_node(fdt)); 499 500 ut_assertok(fdt_end_node(fdt)); >>> CID 356242: (TAINTED_SCALAR) >>> Passing tainted expression "fdt->size_dt_strings" to "fdt_finish", which uses it as an offset. 501 ut_assertok(fdt_finish(fdt)); 502 503 return 0; 504 } 505 506 static int dm_test_ofnode_root(struct unit_test_state *uts) /test/dm/ofnode.c: 501 in make_ofnode_fdt() 495 ut_assertok(fdt_end_node(fdt)); 496 497 ut_assert(fdt_begin_node(fdt, "new-mmc") >= 0); 498 ut_assertok(fdt_end_node(fdt)); 499 500 ut_assertok(fdt_end_node(fdt)); >>> CID 356242: (TAINTED_SCALAR) >>> Passing tainted expression "fdt->size_dt_strings" to "fdt_finish", which uses it as an offset. 501 ut_assertok(fdt_finish(fdt)); 502 503 return 0; 504 } 505 506 static int dm_test_ofnode_root(struct unit_test_state *uts) ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P… To manage Coverity Scan email notifications for "tom.rini(a)gmail.com", click https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P… -- Tom ----- End forwarded message ----- -- Tom

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[PATCH] configs: stm32mp*: fix system reset
by Jorge Ramirez-Ortiz 08 Sep '22

08 Sep '22

Enabling CONFIG_SYSRESET_PSCI prevents CONFIG_RESET_SCMI from executing. The side effect observed are I2C devices no longer being accessible from U-boot after a soft reset. Fixes: 11517ccc8c52 ("configs: add stm32mp13 defconfig") Fixes: 17aeb589fa9d ("stm32mp15: remove configs dependency on CONFIG_TFABOOT") Signed-off-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> --- configs/stm32mp13_defconfig | 1 - configs/stm32mp15_defconfig | 1 - configs/stm32mp15_trusted_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 673b468d31..44cee2e656 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -69,7 +69,6 @@ CONFIG_RNG_OPTEE=y CONFIG_DM_RTC=y CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y -CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index e5a2996c2c..2ad02f3652 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -133,7 +133,6 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_STM32_SPI=y -CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index e14668042f..9e24e82920 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -134,7 +134,6 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_STM32_SPI=y -CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set -- 2.34.1

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