September 2022 - U-Boot

[PATCH] HSD #2205749969: board: altera: Add fitImage to support S10 secure boot for both U-Boot and kernel
by Jit Loon Lim 01 Sep '22

01 Sep '22

From: "Ooi, Joyce" <joyce.ooi(a)intel.com> FitImage files are added to load Linux kernel image and U-boot image for Stratix10 Secure Boot. Signed-off-by: Ooi, Joyce <joyce.ooi(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- .../stratix10-socdk/its/kernel-sign.its | 51 +++++++++++++++++++ .../altera/stratix10-socdk/its/uboot-sign.its | 41 +++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 board/altera/stratix10-socdk/its/kernel-sign.its create mode 100644 board/altera/stratix10-socdk/its/uboot-sign.its diff --git a/board/altera/stratix10-socdk/its/kernel-sign.its b/board/altera/stratix10-socdk/its/kernel-sign.its new file mode 100644 index 0000000000..5136365b99 --- /dev/null +++ b/board/altera/stratix10-socdk/its/kernel-sign.its @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2019 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +/ { + description = "Linux kernel image with FDT blob"; + #address-cells = <1>; + + images { + kernel { + description = "Linux Kernel"; + data = /incbin/("Image"); + type = "kernel"; + arch = "arm64"; + os = "linux"; + compression = "none"; + load = <0x2080000>; + entry = <0x2080000>; + hash { + algo = "sha256"; + }; + }; + fdt { + description = "Linux DTB"; + data = /incbin/("socfpga_stratix10_socdk.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash { + algo = "sha256"; + }; + }; + }; + configurations { + default = "conf"; + conf { + description = "Linux boot configuration"; + kernel = "kernel"; + fdt = "fdt"; + signature { + algo = "sha256,rsa4096"; + key-name-hint = "dev"; + sign-images = "fdt", "kernel"; + }; + }; + }; +}; diff --git a/board/altera/stratix10-socdk/its/uboot-sign.its b/board/altera/stratix10-socdk/its/uboot-sign.its new file mode 100644 index 0000000000..611bb980f9 --- /dev/null +++ b/board/altera/stratix10-socdk/its/uboot-sign.its @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2019 Intel Corporation. All rights reserved + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +/ { + description = "Authenticator"; + #address-cells = <1>; + + images { + standalone { + description = "Authenticator binary"; + data = /incbin/("../../../../u-boot-dtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x1000>; + entry = <0x1000>; + os = "u-boot"; + hash { + algo = "sha256"; + }; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Authenticator fitImage"; + standalone = "standalone"; + signature { + algo = "sha256,rsa4096"; + key-name-hint = "dev"; + sign-images = "standalone"; + }; + }; + }; +}; -- 2.26.2

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[PATCH] arm: socfpga: stratix10: Enable CONFIG_FPGA_INTEL_PR
by Jit Loon Lim 01 Sep '22

01 Sep '22

From: Chee Hong Ang <chee.hong.ang(a)intel.com> Enable Intel FPGA Partial Reconfiguration driver by default for Stratix10. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- configs/socfpga_stratix10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 07e9f20a41..8bc41cb289 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -66,6 +66,7 @@ CONFIG_BOOTFILE="Image" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y -- 2.26.2

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[PATCH] driver: fpga: Adding Freeze Bridge for PR console support
by Jit Loon Lim 01 Sep '22

01 Sep '22

From: Chin Liang See <chin.liang.see(a)intel.com> Adding Partial Reconfiguration (pr) command at U-Boot console. The pr command will control the Freeze Controller which will freeze and unfreeze the Partial Reconfiguration region. The pr command also support multiple Partial Reconfiguration region by specifying the region ID. Here are the example of expected steps for partial reconfiguration $ bridge enable $ fatload mmc 0:1 100 pr_bitstream.rbf $ pr start 0 $ fpga load 0 100 $filesize $ pr end 0 Signed-off-by: Chin Liang See <chin.liang.see(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/intel_pr.c | 141 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/fpga/intel_pr.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index e07a9cf80e..6e542353fe 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -48,6 +48,15 @@ config FPGA_INTEL_SDM_MAILBOX Enable FPGA driver for writing full bitstream into Intel FPGA devices through SDM (Secure Device Manager) Mailbox. +config FPGA_INTEL_PR + bool "Enable Intel FPGA Partial Reconfiguration driver" + depends on FPGA_ALTERA + help + Say Y here to enable the Intel FPGA Partial Reconfiguration driver + + This provides basic functionality for partial reconfiguration which + include the freeze controller support. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 83243fb107..2eff387100 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -22,4 +22,5 @@ obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o +obj-$(CONFIG_FPGA_INTEL_PR) += intel_pr.o endif diff --git a/drivers/fpga/intel_pr.c b/drivers/fpga/intel_pr.c new file mode 100644 index 0000000000..05f2092600 --- /dev/null +++ b/drivers/fpga/intel_pr.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <command.h> +#include <errno.h> +#include <wait_bit.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/libfdt.h> +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define FREEZE_CSR_STATUS_OFFSET 0 +#define FREEZE_CSR_CTRL_OFFSET 4 +#define FREEZE_CSR_ILLEGAL_REQ_OFFSET 8 +#define FREEZE_CSR_REG_VERSION 12 + +#define FREEZE_CSR_STATUS_FREEZE_REQ_DONE BIT(0) +#define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1) + +#define FREEZE_CSR_CTRL_FREEZE_REQ BIT(0) +#define FREEZE_CSR_CTRL_RESET_REQ BIT(1) +#define FREEZE_CSR_CTRL_UNFREEZE_REQ BIT(2) + +#define FREEZE_TIMEOUT 20000 + +static int intel_get_freeze_br_addr(fdt_addr_t *addr, unsigned int region) +{ + int offset; + char freeze_br[12]; + + snprintf(freeze_br, sizeof(freeze_br), "freeze_br%d", region); + + const char *alias = fdt_get_alias(gd->fdt_blob, freeze_br); + + if (!alias) { + printf("alias %s not found in dts\n", freeze_br); + return -ENODEV; + } + + offset = fdt_path_offset(gd->fdt_blob, alias); + if (offset < 0) { + printf("%s not found in dts\n", alias); + return -ENODEV; + } + + *addr = fdtdec_get_addr(gd->fdt_blob, offset, "reg"); + if (*addr == FDT_ADDR_T_NONE) { + printf("%s has no 'reg' property!\n", freeze_br); + return -ENXIO; + } + + return 0; +} + +static int intel_freeze_br_do_freeze(unsigned int region) +{ + u32 status; + int ret; + fdt_addr_t addr; + + ret = intel_get_freeze_br_addr(&addr, region); + if (ret) + return ret; + + status = readl(addr + FREEZE_CSR_STATUS_OFFSET); + + if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) + return 0; + else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) + return -EINVAL; + + writel(FREEZE_CSR_CTRL_FREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); + + return wait_for_bit_le32((const u32 *)(addr + + FREEZE_CSR_STATUS_OFFSET), + FREEZE_CSR_STATUS_FREEZE_REQ_DONE, true, + FREEZE_TIMEOUT, false); +} + +static int intel_freeze_br_do_unfreeze(unsigned int region) +{ + u32 status; + int ret; + fdt_addr_t addr; + + ret = intel_get_freeze_br_addr(&addr, region); + if (ret) + return ret; + + status = readl(addr + FREEZE_CSR_STATUS_OFFSET); + + if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) + return 0; + else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) + return -EINVAL; + + writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, addr + FREEZE_CSR_CTRL_OFFSET); + + return wait_for_bit_le32((const u32 *)(addr + + FREEZE_CSR_STATUS_OFFSET), + FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE, true, + FREEZE_TIMEOUT, false); +} + +static int do_pr(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + const char *cmd; + char *region; + unsigned int region_num = 0; + + if (argc != 2 && argc != 3) + return CMD_RET_USAGE; + + cmd = argv[1]; + if (argc == 3) + region_num = simple_strtoul(argv[2], &region, 0); + + if (strcmp(cmd, "start") == 0) + return intel_freeze_br_do_freeze(region_num); + else if (strcmp(cmd, "end") == 0) + return intel_freeze_br_do_unfreeze(region_num); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + pr, 3, 1, do_pr, + "SoCFPGA partial reconfiguration control", + "start [region] - Start the partial reconfiguration by freeze the\n" + "PR region\n" + "end [region] - End the partial reconfiguration by unfreeze the PR\n" + "region\n" + "" +); -- 2.26.2

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[PATCH v2 00/32] Add support for MediaTek MT7981/MT7986 SoCs - v2
by Weijie Gao 01 Sep '22

01 Sep '22

This patch series add support for MediaTek MT7981/MT7986 SoCs with their reference boards and related drivers. This patch series add basic boot support on eMMC/SD/SPI-NOR/SPI-NAND for these boards. The clock, pinctrl drivers and the SoC initializaton code are also included. Product spec for MT7986: https://www.mediatek.com/products/home-networking/mediatek-filogic-830 Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image - Fix coding style - Minor changes Weijie Gao (32): arm: mediatek: add support for MediaTek MT7986 SoC arm: mediatek: add support for MediaTek MT7981 SoC board: mediatek: add MT7986 reference boards board: mediatek: add MT7981 reference boards mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs net: mediatek: use a struct to cover variations of all SoCs net: mediatek: stop using bitfileds for DMA descriptors net: mediatek: add support for PDMA v2 net: mediatek: add support for MediaTek MT7981/MT7986 serial: mtk: add support for using dynamic baud clock souce arm: dts: mt7622: force high-speed mode for uart pwm: mtk: add support for MediaTek MT7986 SoC pwm: mtk: add support for MediaTek MT7981 SoC timer: mtk: add support for MediaTek MT7981/MT7986 SoCs watchdog: mediatek: add support for MediaTek MT7986 SoC spi: add support for MediaTek spi-mem controller i2c: add support for MediaTek I2C interface arm: dts: mt7622: add i2c support dt-bindings: pinctrl: mediatek: add a header for common pinconf parameters pinctrl: mediatek: add pinctrl driver for MT7981 SoC pinctrl: mediatek: add pinctrl driver for MT7986 SoC clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock clk: mediatek: add support to configure clock driver parent clk: mediatek: add infrasys clock mux support clk: mediatek: add CLK_XTAL support for clock driver clk: mediatek: add clock driver support for MediaTek MT7986 SoC clk: mediatek: add clock driver support for MediaTek MT7981 SoC cpu: add basic cpu driver for MediaTek ARM chips tools: mtk_image: split gfh header verification into a new function tools: mtk_image: split the code of generating NAND header into a new file tools: mtk_image: add support for nand headers used by newer chips MAINTAINERS: update maintainer for MediaTek ARM platform MAINTAINERS | 6 + arch/arm/dts/Makefile | 9 + arch/arm/dts/mt7622-rfb.dts | 18 + arch/arm/dts/mt7622.dtsi | 25 + arch/arm/dts/mt7981-emmc-rfb.dts | 139 +++ arch/arm/dts/mt7981-rfb.dts | 173 +++ arch/arm/dts/mt7981-sd-rfb.dts | 139 +++ arch/arm/dts/mt7981.dtsi | 293 +++++ arch/arm/dts/mt7986-u-boot.dtsi | 33 + arch/arm/dts/mt7986.dtsi | 346 ++++++ arch/arm/dts/mt7986a-emmc-rfb.dts | 16 + arch/arm/dts/mt7986a-rfb.dts | 218 ++++ arch/arm/dts/mt7986a-sd-rfb.dts | 177 +++ arch/arm/dts/mt7986b-emmc-rfb.dts | 16 + arch/arm/dts/mt7986b-rfb.dts | 204 ++++ arch/arm/dts/mt7986b-sd-rfb.dts | 173 +++ arch/arm/mach-mediatek/Kconfig | 23 + arch/arm/mach-mediatek/Makefile | 2 + arch/arm/mach-mediatek/mt7981/Makefile | 4 + arch/arm/mach-mediatek/mt7981/init.c | 45 + arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 + arch/arm/mach-mediatek/mt7986/Makefile | 4 + arch/arm/mach-mediatek/mt7986/init.c | 45 + arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 + board/mediatek/mt7981/MAINTAINERS | 10 + board/mediatek/mt7981/Makefile | 3 + board/mediatek/mt7981/mt7981_rfb.c | 10 + board/mediatek/mt7986/MAINTAINERS | 10 + board/mediatek/mt7986/Makefile | 3 + board/mediatek/mt7986/mt7986_rfb.c | 10 + configs/mt7981_emmc_rfb_defconfig | 64 + configs/mt7981_rfb_defconfig | 69 ++ configs/mt7981_sd_rfb_defconfig | 64 + configs/mt7986_rfb_defconfig | 66 ++ configs/mt7986a_bpir3_emmc_defconfig | 64 + configs/mt7986a_bpir3_sd_defconfig | 64 + drivers/clk/mediatek/Makefile | 2 + drivers/clk/mediatek/clk-mt7981.c | 683 +++++++++++ drivers/clk/mediatek/clk-mt7986.c | 672 +++++++++++ drivers/clk/mediatek/clk-mtk.c | 156 ++- drivers/clk/mediatek/clk-mtk.h | 13 +- drivers/cpu/Makefile | 1 + drivers/cpu/mtk_cpu.c | 106 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/mtk_i2c.c | 822 +++++++++++++ drivers/mmc/mtk-sd.c | 68 +- drivers/net/mtk_eth.c | 261 ++-- drivers/net/mtk_eth.h | 101 +- drivers/pinctrl/mediatek/Kconfig | 8 + drivers/pinctrl/mediatek/Makefile | 2 + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1049 +++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 775 ++++++++++++ drivers/pwm/pwm-mtk.c | 40 +- drivers/serial/serial_mtk.c | 80 +- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mtk_spim.c | 701 +++++++++++ drivers/timer/mtk_timer.c | 59 +- drivers/watchdog/mtk_wdt.c | 1 + include/configs/mt7981.h | 26 + include/configs/mt7986.h | 26 + include/dt-bindings/clock/mt7981-clk.h | 267 +++++ include/dt-bindings/clock/mt7986-clk.h | 249 ++++ include/dt-bindings/pinctrl/mt65xx.h | 41 + tools/Makefile | 1 + tools/mtk_image.c | 377 ++---- tools/mtk_image.h | 25 - tools/mtk_nand_headers.c | 668 +++++++++++ tools/mtk_nand_headers.h | 165 +++ 70 files changed, 9525 insertions(+), 548 deletions(-) create mode 100644 arch/arm/dts/mt7981-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7981-rfb.dts create mode 100644 arch/arm/dts/mt7981-sd-rfb.dts create mode 100644 arch/arm/dts/mt7981.dtsi create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi create mode 100644 arch/arm/dts/mt7986.dtsi create mode 100644 arch/arm/dts/mt7986a-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7986a-rfb.dts create mode 100644 arch/arm/dts/mt7986a-sd-rfb.dts create mode 100644 arch/arm/dts/mt7986b-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7986b-rfb.dts create mode 100644 arch/arm/dts/mt7986b-sd-rfb.dts create mode 100644 arch/arm/mach-mediatek/mt7981/Makefile create mode 100644 arch/arm/mach-mediatek/mt7981/init.c create mode 100644 arch/arm/mach-mediatek/mt7981/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/mt7986/Makefile create mode 100644 arch/arm/mach-mediatek/mt7986/init.c create mode 100644 arch/arm/mach-mediatek/mt7986/lowlevel_init.S create mode 100644 board/mediatek/mt7981/MAINTAINERS create mode 100644 board/mediatek/mt7981/Makefile create mode 100644 board/mediatek/mt7981/mt7981_rfb.c create mode 100644 board/mediatek/mt7986/MAINTAINERS create mode 100644 board/mediatek/mt7986/Makefile create mode 100644 board/mediatek/mt7986/mt7986_rfb.c create mode 100644 configs/mt7981_emmc_rfb_defconfig create mode 100644 configs/mt7981_rfb_defconfig create mode 100644 configs/mt7981_sd_rfb_defconfig create mode 100644 configs/mt7986_rfb_defconfig create mode 100644 configs/mt7986a_bpir3_emmc_defconfig create mode 100644 configs/mt7986a_bpir3_sd_defconfig create mode 100644 drivers/clk/mediatek/clk-mt7981.c create mode 100644 drivers/clk/mediatek/clk-mt7986.c create mode 100644 drivers/cpu/mtk_cpu.c create mode 100644 drivers/i2c/mtk_i2c.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c create mode 100644 drivers/spi/mtk_spim.c create mode 100644 include/configs/mt7981.h create mode 100644 include/configs/mt7986.h create mode 100644 include/dt-bindings/clock/mt7981-clk.h create mode 100644 include/dt-bindings/clock/mt7986-clk.h create mode 100644 include/dt-bindings/pinctrl/mt65xx.h create mode 100644 tools/mtk_nand_headers.c create mode 100644 tools/mtk_nand_headers.h -- 2.17.1

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How can I change the LPDDR4x configuration on U-boot
by Byungkook Kim 01 Sep '22

01 Sep '22

Dear Geniuses, I'm a beginner in the embedded world, so naturally I have a few questions. ^^;; I will ask the most curious thing among them. It is a very difficult problem for me, but I think it is a simple for you. Please teach me. I bought SBC(Single Board Computer) to study embedded Linux & U-boot recently. - Processor : Amlogic A311D2 - RAM : 8GB LPDDR4X 2pcs 4GB LPDDR4x DRAM has mounted on the SBC so total density is 8GB. The 4GB LPDDR4X DRAM structure used for this SBC is like as below. The SBC working well with U-boot & Ubuntu. ### My Question ### I have 2GB LPDDR4x devices and the structure is like as below. The structural difference is the 4GB device is 2-rank(2CS) structure and the 2GB device is 1-rank(1CS) structure. If I replace the LPDDR4X device from 2pcs 4GB to 2pcs 2GB then I think it needed to modify the u-boot codes. I found 'timing.c' file and change the DDR_SIZE_TYPE define like as below. - Before : #define DDR_SIZE_TYPE_1 AN_408_DDR0_4G_DDR1_4G_RANK01 - After : #define DDR_SIZE_TYPE_1 AN_408_DDR0_2G_DDR1_2G But I don't know the exact modify points, it seems that this alone is nor enough. Please teach me. Best Regards, BK Kim

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