September 2022 - U-Boot

[PATCH v2 1/1] efi_loader: support CTRL+\ - CTRL+_
by Heinrich Schuchardt 02 Sep '22

02 Sep '22

In the extended text input protocol support input of control letters 0x1c - 0x1f. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- v2: add missing break --- lib/efi_loader/efi_console.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 3164fd484e..56f197f39a 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -993,6 +993,7 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke_ex( /* * CTRL+A - CTRL+Z have to be signaled as a - z. * SHIFT+CTRL+A - SHIFT+CTRL+Z have to be signaled as A - Z. + * CTRL+\ - CTRL+_ have to be signaled as \ - _. */ switch (next_key.key.unicode_char) { case 0x01 ... 0x07: @@ -1005,6 +1006,9 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke_ex( next_key.key.unicode_char += 0x40; else next_key.key.unicode_char += 0x60; + break; + case 0x1c ... 0x1f: + next_key.key.unicode_char += 0x40; } *key_data = next_key; key_available = false; -- 2.37.2

2 1

[PATCH] arm: socfpga: Ensure the DTS QSPI clock is set correctly
by Jit Loon Lim 02 Sep '22

02 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> The clocking section of Linux device tree was changed between 4.9.78-ltsi and 4.14.73-ltsi. This patch ensures that QSPI clock can be set correctly despite of different clocking section location in both Linux 4.9.78-ltsi and 4.14.73-ltsi. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- include/configs/socfpga_soc64_common.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 06198ddd82..14506ac2b2 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -57,8 +57,10 @@ "echo Enabling QSPI at Linux DTB...;" \ "fdt addr ${fdt_addr}; fdt resize;" \ "fdt set /soc/spi@ff8d2000 status okay;" \ - "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ - " ${qspi_clock}; fi; \0" \ + "if fdt set /soc/clocks/qspi-clk clock-frequency" \ + " ${qspi_clock}; then" \ + " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \ + " ${qspi_clock}; fi; fi\0" \ "scriptaddr=0x02100000\0" \ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ -- 2.26.2

1 0

[PATCH] arm: socfpga: soc64: Enable ARM SMCCC
by Jit Loon Lim 02 Sep '22

02 Sep '22

From: Chee Hong Ang <chee.hong.ang(a)intel.com> Enable ARM Secure Monitor Call Calling Convention (SMCCC) Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> --- configs/socfpga_agilex_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index e2d869610c..ebdc7dad8c 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARM_SMCCC=y CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 07e9f20a41..4ea459fb3e 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_ARM_SMCCC=y CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_TEXT_BASE=0x1000 -- 2.26.2

1 0

[PATCH 0/2] *** SUBJECT HERE ***
by sieu.mun.tang＠intel.com 02 Sep '22

02 Sep '22

From: Sieu Mun Tang <sieu.mun.tang(a)intel.com> *** BLURB HERE *** Tien Fong Chee (2): arch: arm: mach-socfpga: Use custom header target buffer in SPL arch: arm: mach-socfpga: Add SPL fitImage config match arch/arm/mach-socfpga/spl_a10.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.25.1

1 2

[PATCH] driver: fpga: Add support for loading FPGA bitstream from RAW partition
by sieu.mun.tang＠intel.com 02 Sep '22

02 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Removed checking on filename, so that FPGA bitstream can be loaded from pre-defined bitstream offset of RAW partition to program FPGA. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang(a)intel.com> --- drivers/fpga/socfpga_arria10.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index d8089122af..3874b4a014 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -924,8 +924,7 @@ void fpgamgr_program(const void *buf, size_t bsize, u32 offset) fpga_fsinfo.filename = get_fpga_filename(); - if (fpga_fsinfo.filename) - socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset); + socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset); } #endif -- 2.25.1

1 0

[PATCH] reset: socfpga: release more A10 peripherals out of reset
by Jit Loon Lim 02 Sep '22

02 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Current implementation almost release all peripherals out of reset for gen5, but A10 has more peripherals than gen5, hence this patch is required to release the rest of peripherals to support old kernels. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/reset/reset-socfpga.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 6e3f03e248..bd30396fe5 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -115,6 +115,9 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + writel(0, data->modrst_base + 8); +#endif } return 0; -- 2.26.2

1 0

[PATCH 1/1] efi_loader: support CTRL+\ - CTRL+_
by Heinrich Schuchardt 02 Sep '22

02 Sep '22

In the extended text input protocol support input of control letters 0x1c - 0x1f. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- lib/efi_loader/efi_console.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c index 1fcaabe1c4..eab315cbd4 100644 --- a/lib/efi_loader/efi_console.c +++ b/lib/efi_loader/efi_console.c @@ -994,6 +994,7 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke_ex( /* * CTRL+A - CTRL+Z have to be signaled as a - z. * SHIFT+CTRL+A - SHIFT+CTRL+Z have to be signaled as A - Z. + * CTRL+\ - CTRL+_ have to be signaled as \ - _. */ switch (next_key.key.unicode_char) { case 0x01 ... 0x07: @@ -1006,6 +1007,8 @@ static efi_status_t EFIAPI efi_cin_read_key_stroke_ex( next_key.key.unicode_char += 0x40; else next_key.key.unicode_char += 0x60; + case 0x1c ... 0x1f: + next_key.key.unicode_char += 0x40; } *key_data = next_key; key_available = false; -- 2.37.2

2 2

[PATCH] arch: arm: dts: socfpga: Add dts support for QSPI Arria 10 SoCDK
by sieu.mun.tang＠intel.com 01 Sep '22

01 Sep '22

From: Sieu Mun Tang <sieu.mun.tang(a)intel.com> Enable dtb build for QSPI Arria 10 SoCDK. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang(a)intel.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10_socdk_qspi.dts | 63 +++ .../socfpga_arria10_socdk_qspi_handoff.dtsi | 522 ++++++++++++++++++ 3 files changed, 586 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7330121dba..2534b1c9ad 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -427,6 +427,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_3.dtb \ socfpga_arria10_chameleonv3_480_2.dtb \ + socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_is1.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 0000000000..cf11d6b3bc --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright (C) 2019 Intel Corporation + * + * These codes were based on handoffs + * generated from both Qsys and Quartus. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" +#include "socfpga_arria10_socdk-u-boot.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_socdk_qspi_handoff.dtsi" + +/ { + aliases { + spi0 = &qspi; + }; + + fs_loader0: fs-loader { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0 100000000 3>; + }; +}; + +&fpga_mgr { + u-boot,dm-pre-reloc; + firmware-loader = <&fs_loader0>; + altr,bitstream = "300000"; +}; + +&l4_main_clk { + u-boot,dm-pre-reloc; +}; + +&qspi_clk { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; + + flash0: n25q00a@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi new file mode 100644 index 0000000000..eff15b494a --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright (C) 2019 Intel Corporation + * + * These codes were based on handoffs + * generated from both Qsys and Quartus. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ + + /* Clock sources */ + clocks { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + /* Clock source: altera_arria10_hps_eosc1 */ + altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + /* Clock source: altera_arria10_hps_cb_intosc_ls */ + altera_arria10_hps_cb_intosc_ls: + altera_arria10_hps_cb_intosc_ls { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = + "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + /* Clock source: altera_arria10_hps_f2h_free */ + altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + }; + + /* + * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_clk_mgr: clock_manager@0xffd04000 { + compatible = "altr,socfpga-a10-clk-init"; + reg = <0xffd04000 0x00000200>; + reg-names = "soc_clock_manager_OCP_SLV"; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp + */ + mainpll { + /* Field: vco0.psrc */ + vco0-psrc = <0>; + /* Field: vco1.denom */ + vco1-denom = <1>; + /* Field: vco1.numer */ + vco1-numer = <191>; + /* Field: mpuclk.cnt */ + mpuclk-cnt = <0>; + /* Field: mpuclk.src */ + mpuclk-src = <0>; + /* Field: nocclk.cnt */ + nocclk-cnt = <0>; + /* Field: nocclk.src */ + nocclk-src = <0>; + /* Field: cntr2clk.cnt */ + cntr2clk-cnt = <900>; + /* Field: cntr3clk.cnt */ + cntr3clk-cnt = <900>; + /* Field: cntr4clk.cnt */ + cntr4clk-cnt = <900>; + /* Field: cntr5clk.cnt */ + cntr5clk-cnt = <900>; + /* Field: cntr6clk.cnt */ + cntr6clk-cnt = <900>; + /* Field: cntr7clk.cnt */ + cntr7clk-cnt = <900>; + /* Field: cntr7clk.src */ + cntr7clk-src = <0>; + /* Field: cntr8clk.cnt */ + cntr8clk-cnt = <900>; + /* Field: cntr9clk.cnt */ + cntr9clk-cnt = <900>; + /* Field: cntr9clk.src */ + cntr9clk-src = <0>; + /* Field: cntr15clk.cnt */ + cntr15clk-cnt = <900>; + /* Field: nocdiv.l4mainclk */ + nocdiv-l4mainclk = <0>; + /* Field: nocdiv.l4mpclk */ + nocdiv-l4mpclk = <0>; + /* Field: nocdiv.l4spclk */ + nocdiv-l4spclk = <2>; + /* Field: nocdiv.csatclk */ + nocdiv-csatclk = <0>; + /* Field: nocdiv.cstraceclk */ + nocdiv-cstraceclk = <1>; + /* Field: nocdiv.cspdbgclk */ + nocdiv-cspdbgclk = <1>; + }; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp + */ + perpll { + /* Field: vco0.psrc */ + vco0-psrc = <0>; + /* Field: vco1.denom */ + vco1-denom = <1>; + /* Field: vco1.numer */ + vco1-numer = <159>; + /* Field: cntr2clk.cnt */ + cntr2clk-cnt = <7>; + /* Field: cntr2clk.src */ + cntr2clk-src = <1>; + /* Field: cntr3clk.cnt */ + cntr3clk-cnt = <900>; + /* Field: cntr3clk.src */ + cntr3clk-src = <1>; + /* Field: cntr4clk.cnt */ + cntr4clk-cnt = <19>; + /* Field: cntr4clk.src */ + cntr4clk-src = <1>; + /* Field: cntr5clk.cnt */ + cntr5clk-cnt = <499>; + /* Field: cntr5clk.src */ + cntr5clk-src = <1>; + /* Field: cntr6clk.cnt */ + cntr6clk-cnt = <900>; + /* Field: cntr6clk.src */ + cntr6clk-src = <1>; + /* Field: cntr7clk.cnt */ + cntr7clk-cnt = <900>; + /* Field: cntr8clk.cnt */ + cntr8clk-cnt = <900>; + /* Field: cntr8clk.src */ + cntr8clk-src = <0>; + /* Field: cntr9clk.cnt */ + cntr9clk-cnt = <900>; + /* Field: emacctl.emac0sel */ + emacctl-emac0sel = <0>; + /* Field: emacctl.emac1sel */ + emacctl-emac1sel = <0>; + /* Field: emacctl.emac2sel */ + emacctl-emac2sel = <0>; + /* Field: gpiodiv.gpiodbclk */ + gpiodiv-gpiodbclk = <32000>; + }; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp + */ + alteragrp { + /* Register: nocclk */ + nocclk = <0x0384000b>; + /* Register: mpuclk */ + mpuclk = <0x03840001>; + }; + }; + + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Version: 1.0 + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp + */ + shared { + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Register: pinmux_shared_io_q1_1 */ + <0x00000000 0x00000008>, + /* Register: pinmux_shared_io_q1_2 */ + <0x00000004 0x00000008>, + /* Register: pinmux_shared_io_q1_3 */ + <0x00000008 0x00000008>, + /* Register: pinmux_shared_io_q1_4 */ + <0x0000000c 0x00000008>, + /* Register: pinmux_shared_io_q1_5 */ + <0x00000010 0x00000008>, + /* Register: pinmux_shared_io_q1_6 */ + <0x00000014 0x00000008>, + /* Register: pinmux_shared_io_q1_7 */ + <0x00000018 0x00000008>, + /* Register: pinmux_shared_io_q1_8 */ + <0x0000001c 0x00000008>, + /* Register: pinmux_shared_io_q1_9 */ + <0x00000020 0x00000008>, + /* Register: pinmux_shared_io_q1_10 */ + <0x00000024 0x00000008>, + /* Register: pinmux_shared_io_q1_11 */ + <0x00000028 0x00000008>, + /* Register: pinmux_shared_io_q1_12 */ + <0x0000002c 0x00000008>, + /* Register: pinmux_shared_io_q2_1 */ + <0x00000030 0x00000004>, + /* Register: pinmux_shared_io_q2_2 */ + <0x00000034 0x00000004>, + /* Register: pinmux_shared_io_q2_3 */ + <0x00000038 0x00000004>, + /* Register: pinmux_shared_io_q2_4 */ + <0x0000003c 0x00000004>, + /* Register: pinmux_shared_io_q2_5 */ + <0x00000040 0x00000004>, + /* Register: pinmux_shared_io_q2_6 */ + <0x00000044 0x00000004>, + /* Register: pinmux_shared_io_q2_7 */ + <0x00000048 0x00000004>, + /* Register: pinmux_shared_io_q2_8 */ + <0x0000004c 0x00000004>, + /* Register: pinmux_shared_io_q2_9 */ + <0x00000050 0x00000004>, + /* Register: pinmux_shared_io_q2_10 */ + <0x00000054 0x00000004>, + /* Register: pinmux_shared_io_q2_11 */ + <0x00000058 0x00000004>, + /* Register: pinmux_shared_io_q2_12 */ + <0x0000005c 0x00000004>, + /* Register: pinmux_shared_io_q3_1 */ + <0x00000060 0x00000003>, + /* Register: pinmux_shared_io_q3_2 */ + <0x00000064 0x00000003>, + /* Register: pinmux_shared_io_q3_3 */ + <0x00000068 0x00000003>, + /* Register: pinmux_shared_io_q3_4 */ + <0x0000006c 0x00000003>, + /* Register: pinmux_shared_io_q3_5 */ + <0x00000070 0x00000003>, + /* Register: pinmux_shared_io_q3_6 */ + <0x00000074 0x0000000f>, + /* Register: pinmux_shared_io_q3_7 */ + <0x00000078 0x0000000a>, + /* Register: pinmux_shared_io_q3_8 */ + <0x0000007c 0x0000000a>, + /* Register: pinmux_shared_io_q3_9 */ + <0x00000080 0x0000000a>, + /* Register: pinmux_shared_io_q3_10 */ + <0x00000084 0x0000000a>, + /* Register: pinmux_shared_io_q3_11 */ + <0x00000088 0x00000001>, + /* Register: pinmux_shared_io_q3_12 */ + <0x0000008c 0x00000001>, + /* Register: pinmux_shared_io_q4_1 */ + <0x00000090 0x00000000>, + /* Register: pinmux_shared_io_q4_2 */ + <0x00000094 0x00000000>, + /* Register: pinmux_shared_io_q4_3 */ + <0x00000098 0x0000000f>, + /* Register: pinmux_shared_io_q4_4 */ + <0x0000009c 0x0000000c>, + /* Register: pinmux_shared_io_q4_5 */ + <0x000000a0 0x0000000f>, + /* Register: pinmux_shared_io_q4_6 */ + <0x000000a4 0x0000000f>, + /* Register: pinmux_shared_io_q4_7 */ + <0x000000a8 0x0000000a>, + /* Register: pinmux_shared_io_q4_8 */ + <0x000000ac 0x0000000a>, + /* Register: pinmux_shared_io_q4_9 */ + <0x000000b0 0x0000000c>, + /* Register: pinmux_shared_io_q4_10 */ + <0x000000b4 0x0000000c>, + /* Register: pinmux_shared_io_q4_11 */ + <0x000000b8 0x0000000c>, + /* Register: pinmux_shared_io_q4_12 */ + <0x000000bc 0x0000000c>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp + */ + dedicated { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Register: pinmux_dedicated_io_4 */ + <0x0000000c 0x00000004>, + /* Register: pinmux_dedicated_io_5 */ + <0x00000010 0x00000004>, + /* Register: pinmux_dedicated_io_6 */ + <0x00000014 0x00000004>, + /* Register: pinmux_dedicated_io_7 */ + <0x00000018 0x00000004>, + /* Register: pinmux_dedicated_io_8 */ + <0x0000001c 0x00000004>, + /* Register: pinmux_dedicated_io_9 */ + <0x00000020 0x00000004>, + /* Register: pinmux_dedicated_io_10 */ + <0x00000024 0x0000000a>, + /* Register: pinmux_dedicated_io_11 */ + <0x00000028 0x0000000a>, + /* Register: pinmux_dedicated_io_12 */ + <0x0000002c 0x0000000a>, + /* Register: pinmux_dedicated_io_13 */ + <0x00000030 0x0000000a>, + /* Register: pinmux_dedicated_io_14 */ + <0x00000034 0x0000000a>, + /* Register: pinmux_dedicated_io_15 */ + <0x00000038 0x0000000a>, + /* Register: pinmux_dedicated_io_16 */ + <0x0000003c 0x0000000d>, + /* Register: pinmux_dedicated_io_17 */ + <0x00000040 0x0000000d>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp + */ + dedicated_cfg { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + /* Register: configuration_dedicated_io_bank */ + <0x00000100 0x00000101>, + /* Register: configuration_dedicated_io_1 */ + <0x00000104 0x000b080a>, + /* Register: configuration_dedicated_io_2 */ + <0x00000108 0x000b080a>, + /* Register: configuration_dedicated_io_3 */ + <0x0000010c 0x000b080a>, + /* Register: configuration_dedicated_io_4 */ + <0x00000110 0x0008282a>, + /* Register: configuration_dedicated_io_5 */ + <0x00000114 0x000a282a>, + /* Register: configuration_dedicated_io_6 */ + <0x00000118 0x0008282a>, + /* Register: configuration_dedicated_io_7 */ + <0x0000011c 0x000a282a>, + /* Register: configuration_dedicated_io_8 */ + <0x00000120 0x000a282a>, + /* Register: configuration_dedicated_io_9 */ + <0x00000124 0x000a282a>, + /* Register: configuration_dedicated_io_10 */ + <0x00000128 0x00090000>, + /* Register: configuration_dedicated_io_11 */ + <0x0000012c 0x00090000>, + /* Register: configuration_dedicated_io_12 */ + <0x00000130 0x00090000>, + /* Register: configuration_dedicated_io_13 */ + <0x00000134 0x00090000>, + /* Register: configuration_dedicated_io_14 */ + <0x00000138 0x00090000>, + /* Register: configuration_dedicated_io_15 */ + <0x0000013c 0x00090000>, + /* Register: configuration_dedicated_io_16 */ + <0x00000140 0x0008282a>, + /* Register: configuration_dedicated_io_17 */ + <0x00000144 0x000a282a>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp + */ + fpga { + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + /* Register: pinmux_emac0_usefpga */ + <0x00000000 0x00000000>, + /* Register: pinmux_emac1_usefpga */ + <0x00000004 0x00000000>, + /* Register: pinmux_emac2_usefpga */ + <0x00000008 0x00000000>, + /* Register: pinmux_i2c0_usefpga */ + <0x0000000c 0x00000000>, + /* Register: pinmux_i2c1_usefpga */ + <0x00000010 0x00000000>, + /* Register: pinmux_i2c_emac0_usefpga */ + <0x00000014 0x00000000>, + /* Register: pinmux_i2c_emac1_usefpga */ + <0x00000018 0x00000000>, + /* Register: pinmux_i2c_emac2_usefpga */ + <0x0000001c 0x00000000>, + /* Register: pinmux_nand_usefpga */ + <0x00000020 0x00000000>, + /* Register: pinmux_qspi_usefpga */ + <0x00000024 0x00000000>, + /* Register: pinmux_sdmmc_usefpga */ + <0x00000028 0x00000000>, + /* Register: pinmux_spim0_usefpga */ + <0x0000002c 0x00000000>, + /* Register: pinmux_spim1_usefpga */ + <0x00000030 0x00000000>, + /* Register: pinmux_spis0_usefpga */ + <0x00000034 0x00000000>, + /* Register: pinmux_spis1_usefpga */ + <0x00000038 0x00000000>, + /* Register: pinmux_uart0_usefpga */ + <0x0000003c 0x00000000>, + /* Register: pinmux_uart1_usefpga */ + <0x00000040 0x00000000>; + }; + }; + + /* + * Driver: altera_arria10_soc_noc_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_noc: noc@0xffd10000 { + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + + firewall { + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.limit + */ + mpu0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit + */ + l3-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.limit + */ + fpga2sdram0-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.limit + */ + fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.limit + */ + fpga2sdram2-0 = <0x00000000 0x0000ffff>; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + init-val = <1>; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + init-val = <1>; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + init-val = <0>; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + init-val = <1>; + }; +}; -- 2.25.1

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[PATCH] board: altera: arria10: Add default kernel fitImage for Arria10 QSPI SoCDK
by sieu.mun.tang＠intel.com 01 Sep '22

01 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Add default fitImage file bundling kernel and dtb images for Arria10 QSPI. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang(a)intel.com> --- board/altera/arria10-socdk/fit_kernel.its | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 board/altera/arria10-socdk/fit_kernel.its diff --git a/board/altera/arria10-socdk/fit_kernel.its b/board/altera/arria10-socdk/fit_kernel.its new file mode 100644 index 0000000000..c9559f3f1f --- /dev/null +++ b/board/altera/arria10-socdk/fit_kernel.its @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +/dts-v1/; + +/ { + description = "FIT image with kernel and DTB"; + #address-cells = <1>; + + images { + kernel { + description = "Linux Kernel"; + data = /incbin/("../../../Image"); + type = "kernel"; + os = "linux"; + arch = "arm"; + compression = "none"; + load = <0x8000>; + entry = <0x8000>; + }; + + fdt { + description = "Linux DTB"; + data = /incbin/("../../../socfpga_arria10_socdk_qspi.dtb"); + type = "flat_dt"; + os = "linux"; + arch = "arm"; + compression = "none"; + + }; + }; + + configurations { + default = "conf"; + conf { + description = "Linux boot configuration"; + kernel = "kernel"; + fdt = "fdt"; + }; + }; +}; -- 2.25.1

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[PATCH] board: altera: arria10: Add default U-Boot fitImage for Arria10 SoCDK
by sieu.mun.tang＠intel.com 01 Sep '22

01 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Add default U-Boot fitImage file so that fit features can be supported and loaded by SPL. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang(a)intel.com> --- board/altera/arria10-socdk/fit_uboot.its | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 board/altera/arria10-socdk/fit_uboot.its diff --git a/board/altera/arria10-socdk/fit_uboot.its b/board/altera/arria10-socdk/fit_uboot.its new file mode 100644 index 0000000000..aa80e8e278 --- /dev/null +++ b/board/altera/arria10-socdk/fit_uboot.its @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +/dts-v1/; + +/ { + description = "FIT image with boot binaries"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (32-bit)"; + data = /incbin/("../../../u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm"; + compression = "none"; + load = <0x01000040>; + entry = <0x01000040>; + }; + + fdt { + description = "U-Boot DTB"; + data = /incbin/("../../../u-boot.dtb"); + type = "flat_dt"; + os = "U-Boot"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "conf"; + conf { + description = "Intel Arria10 SoCDK"; + loadables = "uboot"; + fdt = "fdt"; + }; + }; +}; -- 2.25.1

1 0