September 2022 - U-Boot

[GIT PULL] xilinx patches for v2023.01-rc1
by Michal Simek 13 Sep '22

13 Sep '22

Hi Tom, please pull the following patches to your tree. Buildman and CI loop doesn't show any issue. Thanks, Michal The following changes since commit 98b3a998b31a83d8167f888b11ddd5cce8194f35: Merge branch '2022-09-02-assorted-improvements' into next (2022-09-02 21:53:36 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2023.01-rc1 for you to fetch changes up to 39d3c3cfaa4f5099a2d687de4530c9ca4bee256d: xilinx: common: Add support for SOC detection (2022-09-13 11:32:48 +0200) ---------------------------------------------------------------- Xilinx changes for v2023.01-rc1 cmd: - bdinfo - guard LMB code to run only when LMB is enabled timer: - convert arm twd timer to DM power-domain: - Skip loading config object for Versal xilinx: - Fix logic when dfu_alt_info is generated - Define only mmc devnum not partition - Add xlnx prefix to GEM compatible string - Add missing tca6416 to zynqmp SC - vck190 - Add env redund offset - Enable CMD_GREPENV/SETEXPR by default - Move board_get_usable_ram_top() to common location - Add support for SOC detection net/gem: - Check rate before setting it up microblaze: - drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE - Show cache size in bdinfo spi: - cadence_qspi: driver updates - zynqmp_gqspi: driver updates - zynqmp_gqspi: Add tap delays for Versal zynq: - Enable mkeficapsule compilation - Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info - Align bss and end of u-boot image to 64bits - Align qspi node name with Linux kernel - DT: List OCM memory zynqmp: - Fix AES cache handling with a user provided key - SOM: Add mtd partition for secure OS storage area - Add ref_clk property for REFCLKPER calculation - Fix mdio bus description for vck190-sc xilinx-mini: - Remove unneeded configs - Disable LMB versal: - Enable i2c mux pca954x by default - Define CONFIG_CQSPI_REF_CLK - Enable power domain driver - Enable zynqmp_gqspi driver ---------------------------------------------------------------- Amit Kumar Mahapatra (1): arm64: zynqmp: Add mtd partition for secure OS storage area Ashok Reddy Soma (13): xilinx: zynqmp: Disable various configs for mini U-Boot xilinx: zynqmp: Disable LMB for mini u-boot firmware: zynqmp: Skip loading config object for Versal xilinx: versal: Enable power domain driver xilinx: versal: Define CONFIG_CQSPI_REF_CLK spi: cadence-qspi: Correct flash reset function name spi: cadence_qspi: Call read_setup for STIG_READ spi: cadence-qspi: Use priv instead of plat across the driver spi: zynqmp_gqspi: Add tap delays for Versal spi: zynqmp_gqspi: Add support for IO mode spi: zynqmp_gqspi: Fix issue of reading more than 32bits length spi: zynqmp_qspi: Code alignment arm64: versal: Enable zynqmp_gqspi driver Harini Katakam (1): arm: dts: Add xlnx prefix to GEM compatible string Janne Ylalehto (1): xilinx: zynqmp: Fix AES with a user provided key Michal Simek (18): xilinx: versal: Enable i2c mux uclass with pca954x driver cmd: bdinfo: Enable dumping lmb data when LMB is enabled xilinx: zynq: Disable LMB for mini configurations xilinx: zynq: Enable mkeficapsule tools compilation xilinx: Fix logic when dfu_alt_info is generated xilinx: zynq: Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info xilinx: Define only mmc devnum not partition arm64: zynqmp: Add missing tca6416 to zynqmp SC xilinx: Enable CMD_GREPENV/SETEXPR by default ARM: zynq: Align bss and end of u-boot image to 64bits arm64: xilinx: Move board_get_usable_ram_top() to common location xilinx: versal: Disable LMB for mini configurations net: gem: Check rate before setting it up arm64: versal: Define zynqmp_mmio_write() for versal ARM: zynq: Align qspi node name with Linux kernel ARM: zynq: DT: List OCM memory xilinx: Fix mdio bus description for vck190-sc xilinx: common: Add support for SOC detection Ovidiu Panait (4): microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE cpu: microblaze: add error handling in microblaze_cpu_get_desc() cmd: bdinfo: introduce bdinfo_print_size() helper microblaze: add arch_print_bdinfo() implementation Piyush Mehta (1): arm64: zynqmp: add ref_clk property for REFCLKPER calculation Stefan Herbrechtsmeier (2): zynq: Convert arm twd timer to DM driver fpga: zynq: Remove post config info message for SPL T Karthik Reddy (1): xilinx: Add env redund offset arch/arm/Kconfig | 3 + arch/arm/dts/zynq-7000.dtsi | 26 ++- arch/arm/dts/zynq-zc702.dts | 13 -- arch/arm/dts/zynqmp-clk-ccf.dtsi | 8 + arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 20 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 10 +- arch/arm/dts/zynqmp.dtsi | 10 +- arch/arm/mach-versal/include/mach/sys_proto.h | 8 + arch/arm/mach-zynq/Makefile | 1 - arch/arm/mach-zynq/clk.c | 6 +- arch/arm/mach-zynq/timer.c | 113 ---------- arch/arm/mach-zynq/u-boot.lds | 4 +- arch/microblaze/lib/Makefile | 1 + arch/microblaze/lib/bdinfo.c | 24 ++ board/xilinx/common/board.c | 54 +++++ board/xilinx/microblaze-generic/microblaze-generic.c | 21 -- board/xilinx/versal/board.c | 23 -- board/xilinx/zynq/board.c | 10 +- board/xilinx/zynqmp/cmds.c | 6 +- board/xilinx/zynqmp/zynqmp.c | 36 +-- cmd/bdinfo.c | 9 +- configs/microblaze-generic_defconfig | 2 +- configs/xilinx_versal_mini_defconfig | 1 + configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 9 + configs/xilinx_zynq_virt_defconfig | 4 +- configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_single_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 14 +- configs/xilinx_zynqmp_virt_defconfig | 2 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + drivers/cpu/microblaze_cpu.c | 4 +- drivers/fpga/zynqpl.c | 3 +- drivers/net/zynq_gem.c | 11 +- drivers/power/domain/zynqmp-power-domain.c | 5 +- drivers/spi/cadence_ospi_versal.c | 56 ++--- drivers/spi/cadence_qspi.c | 104 +++++---- drivers/spi/cadence_qspi.h | 56 +++-- drivers/spi/cadence_qspi_apb.c | 231 ++++++++++---------- drivers/spi/zynqmp_gqspi.c | 221 +++++++++++++------ drivers/timer/Kconfig | 6 + drivers/timer/Makefile | 1 + drivers/timer/arm_twd_timer.c | 108 +++++++++ env/Kconfig | 1 + include/configs/microblaze-generic.h | 6 - include/init.h | 13 ++ 49 files changed, 754 insertions(+), 517 deletions(-) delete mode 100644 arch/arm/mach-zynq/timer.c create mode 100644 arch/microblaze/lib/bdinfo.c create mode 100644 drivers/timer/arm_twd_timer.c -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

2 1

[PATCH] arm: dts: socfpga: Add dts support for NAND Arria 10 SoCDK
by teik.heng.chong＠intel.com 13 Sep '22

13 Sep '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Enable dtb build for NAND Arria 10 SoCDK. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10_socdk_nand.dts | 56 ++ .../socfpga_arria10_socdk_nand_handoff.dtsi | 522 ++++++++++++++++++ 3 files changed, 579 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand_handoff.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2534b1c9ad..6bd7732796 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -427,6 +427,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_3.dtb \ socfpga_arria10_chameleonv3_480_2.dtb \ + socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/dts/socfpga_arria10_socdk_nand.dts new file mode 100644 index 0000000000..0e855648da --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_nand.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + * + * These codes were based on handoffs + * generated from both Qsys and Quartus. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" +#include "socfpga_arria10_socdk-u-boot.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_socdk_nand_handoff.dtsi" + +/ { + fs_loader0: fs-loader { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + }; +}; + +&fpga_mgr { + u-boot,dm-pre-reloc; + firmware-loader = <&fs_loader0>; + altr,bitstream = "300000"; +}; + +&l4_mp_clk { + u-boot,dm-pre-reloc; +}; + +&nand_x_clk { + u-boot,dm-pre-reloc; +}; + +&nand_ecc_clk { + u-boot,dm-pre-reloc; +}; + +&nand_clk { + u-boot,dm-pre-reloc; +}; + +&nand { + u-boot,dm-pre-reloc; + status = "okay"; + + partition@nand-boot { + label = "Boot and fpga data"; + reg = <0x0 0x1EA0000>; + }; + partition@nand-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x1EA0000 0x6160000>; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.dtsi new file mode 100644 index 0000000000..34a57a2b95 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_nand_handoff.dtsi @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + * + * These codes were based on handoffs + * generated from both Qsys and Quartus. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ + + /* Clock sources */ + clocks { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + /* Clock source: altera_arria10_hps_eosc1 */ + altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + /* Clock source: altera_arria10_hps_cb_intosc_ls */ + altera_arria10_hps_cb_intosc_ls: + altera_arria10_hps_cb_intosc_ls { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = + "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + /* Clock source: altera_arria10_hps_f2h_free */ + altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + }; + + /* + * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_clk_mgr: clock_manager@0xffd04000 { + compatible = "altr,socfpga-a10-clk-init"; + reg = <0xffd04000 0x00000200>; + reg-names = "soc_clock_manager_OCP_SLV"; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp + */ + mainpll { + /* Field: vco0.psrc */ + vco0-psrc = <0>; + /* Field: vco1.denom */ + vco1-denom = <1>; + /* Field: vco1.numer */ + vco1-numer = <159>; + /* Field: mpuclk.cnt */ + mpuclk-cnt = <0>; + /* Field: mpuclk.src */ + mpuclk-src = <0>; + /* Field: nocclk.cnt */ + nocclk-cnt = <0>; + /* Field: nocclk.src */ + nocclk-src = <0>; + /* Field: cntr2clk.cnt */ + cntr2clk-cnt = <900>; + /* Field: cntr3clk.cnt */ + cntr3clk-cnt = <900>; + /* Field: cntr4clk.cnt */ + cntr4clk-cnt = <900>; + /* Field: cntr5clk.cnt */ + cntr5clk-cnt = <900>; + /* Field: cntr6clk.cnt */ + cntr6clk-cnt = <900>; + /* Field: cntr7clk.cnt */ + cntr7clk-cnt = <900>; + /* Field: cntr7clk.src */ + cntr7clk-src = <0>; + /* Field: cntr8clk.cnt */ + cntr8clk-cnt = <900>; + /* Field: cntr9clk.cnt */ + cntr9clk-cnt = <900>; + /* Field: cntr9clk.src */ + cntr9clk-src = <0>; + /* Field: cntr15clk.cnt */ + cntr15clk-cnt = <900>; + /* Field: nocdiv.l4mainclk */ + nocdiv-l4mainclk = <0>; + /* Field: nocdiv.l4mpclk */ + nocdiv-l4mpclk = <0>; + /* Field: nocdiv.l4spclk */ + nocdiv-l4spclk = <2>; + /* Field: nocdiv.csatclk */ + nocdiv-csatclk = <0>; + /* Field: nocdiv.cstraceclk */ + nocdiv-cstraceclk = <1>; + /* Field: nocdiv.cspdbgclk */ + nocdiv-cspdbgclk = <1>; + }; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp + */ + perpll { + /* Field: vco0.psrc */ + vco0-psrc = <0>; + /* Field: vco1.denom */ + vco1-denom = <1>; + /* Field: vco1.numer */ + vco1-numer = <159>; + /* Field: cntr2clk.cnt */ + cntr2clk-cnt = <7>; + /* Field: cntr2clk.src */ + cntr2clk-src = <1>; + /* Field: cntr3clk.cnt */ + cntr3clk-cnt = <900>; + /* Field: cntr3clk.src */ + cntr3clk-src = <1>; + /* Field: cntr4clk.cnt */ + cntr4clk-cnt = <19>; + /* Field: cntr4clk.src */ + cntr4clk-src = <1>; + /* Field: cntr5clk.cnt */ + cntr5clk-cnt = <499>; + /* Field: cntr5clk.src */ + cntr5clk-src = <1>; + /* Field: cntr6clk.cnt */ + cntr6clk-cnt = <900>; + /* Field: cntr6clk.src */ + cntr6clk-src = <1>; + /* Field: cntr7clk.cnt */ + cntr7clk-cnt = <900>; + /* Field: cntr8clk.cnt */ + cntr8clk-cnt = <900>; + /* Field: cntr8clk.src */ + cntr8clk-src = <0>; + /* Field: cntr9clk.cnt */ + cntr9clk-cnt = <900>; + /* Field: emacctl.emac0sel */ + emacctl-emac0sel = <0>; + /* Field: emacctl.emac1sel */ + emacctl-emac1sel = <0>; + /* Field: emacctl.emac2sel */ + emacctl-emac2sel = <0>; + /* Field: gpiodiv.gpiodbclk */ + gpiodiv-gpiodbclk = <32000>; + }; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp + */ + alteragrp { + /* Register: nocclk */ + nocclk = <0x03840009>; + /* Register: mpuclk */ + mpuclk = <0x03840001>; + }; + }; + + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Version: 1.0 + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp + */ + shared { + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Register: pinmux_shared_io_q1_1 */ + <0x00000000 0x00000008>, + /* Register: pinmux_shared_io_q1_2 */ + <0x00000004 0x00000008>, + /* Register: pinmux_shared_io_q1_3 */ + <0x00000008 0x00000008>, + /* Register: pinmux_shared_io_q1_4 */ + <0x0000000c 0x00000008>, + /* Register: pinmux_shared_io_q1_5 */ + <0x00000010 0x00000008>, + /* Register: pinmux_shared_io_q1_6 */ + <0x00000014 0x00000008>, + /* Register: pinmux_shared_io_q1_7 */ + <0x00000018 0x00000008>, + /* Register: pinmux_shared_io_q1_8 */ + <0x0000001c 0x00000008>, + /* Register: pinmux_shared_io_q1_9 */ + <0x00000020 0x00000008>, + /* Register: pinmux_shared_io_q1_10 */ + <0x00000024 0x00000008>, + /* Register: pinmux_shared_io_q1_11 */ + <0x00000028 0x00000008>, + /* Register: pinmux_shared_io_q1_12 */ + <0x0000002c 0x00000008>, + /* Register: pinmux_shared_io_q2_1 */ + <0x00000030 0x00000004>, + /* Register: pinmux_shared_io_q2_2 */ + <0x00000034 0x00000004>, + /* Register: pinmux_shared_io_q2_3 */ + <0x00000038 0x00000004>, + /* Register: pinmux_shared_io_q2_4 */ + <0x0000003c 0x00000004>, + /* Register: pinmux_shared_io_q2_5 */ + <0x00000040 0x00000004>, + /* Register: pinmux_shared_io_q2_6 */ + <0x00000044 0x00000004>, + /* Register: pinmux_shared_io_q2_7 */ + <0x00000048 0x00000004>, + /* Register: pinmux_shared_io_q2_8 */ + <0x0000004c 0x00000004>, + /* Register: pinmux_shared_io_q2_9 */ + <0x00000050 0x00000004>, + /* Register: pinmux_shared_io_q2_10 */ + <0x00000054 0x00000004>, + /* Register: pinmux_shared_io_q2_11 */ + <0x00000058 0x00000004>, + /* Register: pinmux_shared_io_q2_12 */ + <0x0000005c 0x00000004>, + /* Register: pinmux_shared_io_q3_1 */ + <0x00000060 0x00000003>, + /* Register: pinmux_shared_io_q3_2 */ + <0x00000064 0x00000003>, + /* Register: pinmux_shared_io_q3_3 */ + <0x00000068 0x00000003>, + /* Register: pinmux_shared_io_q3_4 */ + <0x0000006c 0x00000003>, + /* Register: pinmux_shared_io_q3_5 */ + <0x00000070 0x00000003>, + /* Register: pinmux_shared_io_q3_6 */ + <0x00000074 0x0000000f>, + /* Register: pinmux_shared_io_q3_7 */ + <0x00000078 0x0000000d>, + /* Register: pinmux_shared_io_q3_8 */ + <0x0000007c 0x0000000d>, + /* Register: pinmux_shared_io_q3_9 */ + <0x00000080 0x0000000a>, + /* Register: pinmux_shared_io_q3_10 */ + <0x00000084 0x0000000a>, + /* Register: pinmux_shared_io_q3_11 */ + <0x00000088 0x00000001>, + /* Register: pinmux_shared_io_q3_12 */ + <0x0000008c 0x00000001>, + /* Register: pinmux_shared_io_q4_1 */ + <0x00000090 0x00000000>, + /* Register: pinmux_shared_io_q4_2 */ + <0x00000094 0x00000000>, + /* Register: pinmux_shared_io_q4_3 */ + <0x00000098 0x0000000f>, + /* Register: pinmux_shared_io_q4_4 */ + <0x0000009c 0x0000000c>, + /* Register: pinmux_shared_io_q4_5 */ + <0x000000a0 0x0000000f>, + /* Register: pinmux_shared_io_q4_6 */ + <0x000000a4 0x0000000f>, + /* Register: pinmux_shared_io_q4_7 */ + <0x000000a8 0x0000000a>, + /* Register: pinmux_shared_io_q4_8 */ + <0x000000ac 0x0000000a>, + /* Register: pinmux_shared_io_q4_9 */ + <0x000000b0 0x0000000c>, + /* Register: pinmux_shared_io_q4_10 */ + <0x000000b4 0x0000000c>, + /* Register: pinmux_shared_io_q4_11 */ + <0x000000b8 0x0000000c>, + /* Register: pinmux_shared_io_q4_12 */ + <0x000000bc 0x0000000c>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp + */ + dedicated { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Register: pinmux_dedicated_io_4 */ + <0x0000000c 0x0000000e>, + /* Register: pinmux_dedicated_io_5 */ + <0x00000010 0x0000000e>, + /* Register: pinmux_dedicated_io_6 */ + <0x00000014 0x0000000e>, + /* Register: pinmux_dedicated_io_7 */ + <0x00000018 0x0000000e>, + /* Register: pinmux_dedicated_io_8 */ + <0x0000001c 0x0000000e>, + /* Register: pinmux_dedicated_io_9 */ + <0x00000020 0x0000000e>, + /* Register: pinmux_dedicated_io_10 */ + <0x00000024 0x0000000e>, + /* Register: pinmux_dedicated_io_11 */ + <0x00000028 0x0000000e>, + /* Register: pinmux_dedicated_io_12 */ + <0x0000002c 0x0000000e>, + /* Register: pinmux_dedicated_io_13 */ + <0x00000030 0x0000000e>, + /* Register: pinmux_dedicated_io_14 */ + <0x00000034 0x0000000e>, + /* Register: pinmux_dedicated_io_15 */ + <0x00000038 0x0000000e>, + /* Register: pinmux_dedicated_io_16 */ + <0x0000003c 0x0000000e>, + /* Register: pinmux_dedicated_io_17 */ + <0x00000040 0x0000000e>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp + */ + dedicated_cfg { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + /* Register: configuration_dedicated_io_bank */ + <0x00000100 0x00000101>, + /* Register: configuration_dedicated_io_1 */ + <0x00000104 0x000b080a>, + /* Register: configuration_dedicated_io_2 */ + <0x00000108 0x000b080a>, + /* Register: configuration_dedicated_io_3 */ + <0x0000010c 0x000b080a>, + /* Register: configuration_dedicated_io_4 */ + <0x00000110 0x000a282a>, + /* Register: configuration_dedicated_io_5 */ + <0x00000114 0x000a282a>, + /* Register: configuration_dedicated_io_6 */ + <0x00000118 0x0008282a>, + /* Register: configuration_dedicated_io_7 */ + <0x0000011c 0x0008282a>, + /* Register: configuration_dedicated_io_8 */ + <0x00000120 0x000a282a>, + /* Register: configuration_dedicated_io_9 */ + <0x00000124 0x000a282a>, + /* Register: configuration_dedicated_io_10 */ + <0x00000128 0x0008282a>, + /* Register: configuration_dedicated_io_11 */ + <0x0000012c 0x0008282a>, + /* Register: configuration_dedicated_io_12 */ + <0x00000130 0x000a282a>, + /* Register: configuration_dedicated_io_13 */ + <0x00000134 0x0008282a>, + /* Register: configuration_dedicated_io_14 */ + <0x00000138 0x000a282a>, + /* Register: configuration_dedicated_io_15 */ + <0x0000013c 0x000a282a>, + /* Register: configuration_dedicated_io_16 */ + <0x00000140 0x000a282a>, + /* Register: configuration_dedicated_io_17 */ + <0x00000144 0x000a282a>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp + */ + fpga { + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + /* Register: pinmux_emac0_usefpga */ + <0x00000000 0x00000000>, + /* Register: pinmux_emac1_usefpga */ + <0x00000004 0x00000000>, + /* Register: pinmux_emac2_usefpga */ + <0x00000008 0x00000000>, + /* Register: pinmux_i2c0_usefpga */ + <0x0000000c 0x00000000>, + /* Register: pinmux_i2c1_usefpga */ + <0x00000010 0x00000000>, + /* Register: pinmux_i2c_emac0_usefpga */ + <0x00000014 0x00000000>, + /* Register: pinmux_i2c_emac1_usefpga */ + <0x00000018 0x00000000>, + /* Register: pinmux_i2c_emac2_usefpga */ + <0x0000001c 0x00000000>, + /* Register: pinmux_nand_usefpga */ + <0x00000020 0x00000000>, + /* Register: pinmux_qspi_usefpga */ + <0x00000024 0x00000000>, + /* Register: pinmux_sdmmc_usefpga */ + <0x00000028 0x00000000>, + /* Register: pinmux_spim0_usefpga */ + <0x0000002c 0x00000000>, + /* Register: pinmux_spim1_usefpga */ + <0x00000030 0x00000000>, + /* Register: pinmux_spis0_usefpga */ + <0x00000034 0x00000000>, + /* Register: pinmux_spis1_usefpga */ + <0x00000038 0x00000000>, + /* Register: pinmux_uart0_usefpga */ + <0x0000003c 0x00000000>, + /* Register: pinmux_uart1_usefpga */ + <0x00000040 0x00000000>; + }; + }; + + /* + * Driver: altera_arria10_soc_noc_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_noc: noc@0xffd10000 { + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + + firewall { + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.limit + */ + mpu0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit + */ + l3-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.limit + */ + fpga2sdram0-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.limit + */ + fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.limit + */ + fpga2sdram2-0 = <0x00000000 0x0000ffff>; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + init-val = <1>; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + init-val = <1>; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + init-val = <0>; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + init-val = <1>; + }; +}; -- 2.25.1

1 0

Please pull u-boot-marvell/master
by Stefan Roese 13 Sep '22

13 Sep '22

Hi Tom, please pull this next batch of Armada cache related fixes and some board specific enhancements: ---------------------------------------------------------------- - mvebu: Armada 32bit: Cache setup fixes (Pali) - cmd: mvebu/bubt: Misc enhancements (Pali) - kirkwood: Add CONFIG_SUPPORT_PASSING_ATAGS (Tony) - board: turris: Misc improvements (Pali) - tools: kwboot: Change KWBOOT_MSG_RSP_TIMEO_AXP to 10ms (Stefan) - tools: termios_linux.h: Fix compilation on non-glibc systems (Pali) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=259&view=results Thanks, Stefan The following changes since commit 0ba282e0eeaf29fd78f021fd2f95f7bc3109868d: Merge tag 'dm-pull-12sep22' of https://source.denx.de/u-boot/custodians/u-boot-dm (2022-09-12 09:47:16 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 5818198e6a184963c6afc82178b23a64435ace6a: arm: mvebu: Fix moving internal registers (2022-09-13 09:04:22 +0200) ---------------------------------------------------------------- Pali Rohár (14): cmd: mvebu/bubt: Check for A38x image data checksum cmd: mvebu/bubt: Check for A38x/A37xx OTP secure bits and secure boot arm: mvebu: Espressobin: When emmc is not present disable it also in OF_LIVE board: turris: Initialize serial# env arm: mvebu: turris_{omnia, mox}: Reset bootdelay env for rescue arm: mvebu: turris_mox: Add support for distroboot $fdt_addr tools: termios_linux.h: Fix compilation on non-glibc systems arm: mvebu: turris_omnia: Allow to use second serial port arm: mvebu: Mark constant data with const keyword arm: mvebu: Fix function enable_caches arm: mvebu: Guard non-AXP code by checking for AXP arm: mvebu: lowlevel.S: Use CR_M from asm/system.h arm: mvebu: Enable L2 cache also on Armada 38x arm: mvebu: Fix moving internal registers Stefan Roese (1): tools: kwboot: Change KWBOOT_MSG_RSP_TIMEO_AXP to 10ms Tony Dinh (1): arm: kirkwood: Add CONFIG_SUPPORT_PASSING_ATAGS arch/arm/include/asm/pl310.h | 9 +- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-kirkwood/include/mach/cpu.h | 2 +- arch/arm/mach-mvebu/cpu.c | 39 ++--- arch/arm/mach-mvebu/include/mach/cpu.h | 2 +- arch/arm/mach-mvebu/lowlevel.S | 30 +++- arch/arm/mach-mvebu/mbus.c | 2 +- .../mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +- arch/arm/mach-mvebu/system-controller.c | 2 +- board/CZ.NIC/turris_atsha_otp.c | 33 +++- board/CZ.NIC/turris_atsha_otp.h | 3 +- board/CZ.NIC/turris_mox/turris_mox.c | 53 ++++++- board/CZ.NIC/turris_omnia/turris_omnia.c | 16 +- board/Marvell/mvebu_armada-37xx/board.c | 2 + cmd/mvebu/Kconfig | 1 + cmd/mvebu/bubt.c | 174 +++++++++++++++++++-- configs/dockstar_defconfig | 3 + configs/dreamplug_defconfig | 3 + configs/goflexhome_defconfig | 3 + configs/iconnect_defconfig | 3 + configs/pogo_e02_defconfig | 3 + configs/sheevaplug_defconfig | 3 + configs/turris_omnia_defconfig | 2 + include/configs/turris_mox.h | 1 + tools/kwboot.c | 2 +- tools/termios_linux.h | 1 + 26 files changed, 340 insertions(+), 56 deletions(-)

2 1

[PATCH] HSD #1507500974: configs: arria10: Add bridge enable to CONFIG_BOOTCOMMAND
by teik.heng.chong＠intel.com 13 Sep '22

13 Sep '22

From: Ley Foon Tan <ley.foon.tan(a)intel.com> Add "bridge enable" command to CONFIG_BOOTCOMMAND. CONFIG_BOOTCOMMAND="bridge enable;run distro_bootcmd" defconfig is generated from "make savedefconfig". Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Teik Heng Chong <teik.heng.chong(a)intel.com> --- configs/socfpga_arria10_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 3eac3dfa5d..f79a0393d8 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -19,7 +19,7 @@ CONFIG_SPL_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" -# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOOTCOMMAND="bridge enable;run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -- 2.25.1

2 1

[PATCH 00/15] test: More work on parallel tests
by Simon Glass 13 Sep '22

13 Sep '22

This series makes a further attempt to get closer to having all tests run in parallel. It introduces a new 'make pcheck' option which runs tests in parallel, skipping those that are not compatible. A number of fixes are included for existing tests. The vboot test is updated to only run a single scenario in 'quick' mode. This makes use of pytest's parallel-testing features. The resulting times (including incremental building with LTO) on a 16-core machine are as follows: make pcheck - 1 minute 6 seconds make qcheck - 3 minutes make check - 5 minutes 15 seconds Note that this is not a fair comparison, since 'make pcheck' omits a number of tests, even more than 'make qcheck'. Simon Glass (15): test: Fix test_pinmux to run in parallel test: Fix bootm_test_subst_var() running independently test/py: Allow tests to be marked single-threaded only test: Make test_bind_unbind_with_uclass() single-threaded test: Update FIT tests to run in parallel test: Make test_sqfs_ls() single-threaded test: Make test_efi_bootmgr() single-threaded test: Mark all but the first vboot test as slow test: Mark test_gpt tests as slow test: Make test_gpio_read() independent test: Refactor arg parsing for the run script test/py: Move U-Boot building into a function test/py: Support --build when running tests in parallel dtoc: Drop sys.exit() in test_fdt Makefile: Add a pcheck option to run tests in parallel Makefile | 8 +- doc/develop/py_testing.rst | 37 ++++--- doc/develop/testing.rst | 6 +- test/bootm.c | 3 +- test/py/conftest.py | 104 +++++++++++++----- test/py/pytest.ini | 1 + test/py/requirements.txt | 2 + test/py/tests/test_bind.py | 1 + .../test_efi_bootmgr/test_efi_bootmgr.py | 1 + test/py/tests/test_fit_ecdsa.py | 4 +- test/py/tests/test_fit_hashes.py | 5 +- .../test_fs/test_squashfs/test_sqfs_ls.py | 1 + test/py/tests/test_gpio.py | 1 + test/py/tests/test_gpt.py | 3 + test/py/tests/test_pinmux.py | 1 + test/py/tests/test_vboot.py | 6 +- test/run | 51 +++++++-- tools/dtoc/test_fdt.py | 1 - 18 files changed, 173 insertions(+), 63 deletions(-) -- 2.37.1.559.g78731f0fdb-goog

2 16

[PATCH v2 0/3] rockpi4: Add capsule update support
by Sughosh Ganu 13 Sep '22

13 Sep '22

Changes since V1: * Move the capsule update related functions to a more common place under mach-rockchip to facilitate further reuse. * Split the board related declarations into a separate patch. * Split the enabling of the feature into a separate patch. * Enable config symbols needed access of EFI variables. Sughosh Ganu (3): rockpi4: capsule: Add functions needed for supporting capsule updates rockpi4: board: Add firmware image information needed for capsule updates rockpi4: capsule: Enable UEFI capsule update on RockPi4 boards arch/arm/mach-rockchip/Kconfig | 1 + arch/arm/mach-rockchip/board.c | 185 +++++++++++++++++++++++++ board/rockchip/evb_rk3399/evb-rk3399.c | 14 ++ configs/rock-pi-4-rk3399_defconfig | 8 ++ configs/rock-pi-4c-rk3399_defconfig | 8 ++ include/configs/rk3399_common.h | 16 +++ 6 files changed, 232 insertions(+) -- 2.34.1

2 7

[PATCH v2 1/1] video: simplefb: Add rotation support
by Takumi Sueda 13 Sep '22

13 Sep '22

Signed-off-by: Takumi Sueda <puhitaku(a)gmail.com> --- drivers/video/simplefb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 2b0d8835e3..235ec761f7 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -43,7 +43,11 @@ static int simple_video_probe(struct udevice *dev) uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0); uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0); - uc_priv->rot = 0; + uc_priv->rot = fdtdec_get_uint(blob, node, "rot", 0); + if (uc_priv->rot > 3) { + log_debug("%s: invalid rot\n", __func__); + return log_msg_ret("rot", -EINVAL); + } format = fdt_getprop(blob, node, "format", NULL); debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format); -- 2.20.1

1 1

[PATCH] video: simplefb: Add rotation support
by Takumi Sueda 13 Sep '22

13 Sep '22

It introduces the way to rotate the screen for boards with rotated screen. Signed-off-by: Takumi Sueda <puhitaku(a)gmail.com> --- drivers/video/simplefb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 2b0d8835e3..dbf55ba64d 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -43,7 +43,11 @@ static int simple_video_probe(struct udevice *dev) uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0); uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0); - uc_priv->rot = 0; + uc_priv->rot = fdtdec_get_uint(blob, node, "rot", 0); + if (uc_priv->rot > 3) { + printf("%s: invalid rot\n", __func__); + return -EINVAL; + } format = fdt_getprop(blob, node, "format", NULL); debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format); -- 2.20.1

2 2

[PATCH v17 00/10] enable menu-driven UEFI variable maintenance
by Masahisa Kojima 13 Sep '22

13 Sep '22

This series adds the menu-driven UEFI boot variable maintenance through the "eficonfig" new command. This series also adds the removable media support in bootmenu. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/eficonfig_upstream_v17 [Major Changes] - sort the directory and file name Masahisa Kojima (10): eficonfig: menu-driven addition of UEFI boot option eficonfig: add "Edit Boot Option" menu entry menu: add KEY_PLUS, KEY_MINUS and KEY_SPACE handling eficonfig: add "Delete Boot Option" menu entry bootmenu: add removable media entries eficonfig: scan media device in eficonfig startup eficonfig: add "Change Boot Order" menu entry doc:bootmenu: add description for UEFI boot support doc:eficonfig: add documentation for eficonfig command test: unit test for eficonfig cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/bootmenu.c | 22 +- cmd/eficonfig.c | 2502 +++++++++++++++++ common/menu.c | 9 + configs/sandbox_defconfig | 1 + doc/usage/cmd/bootmenu.rst | 74 + doc/usage/cmd/eficonfig.rst | 71 + doc/usage/index.rst | 1 + include/efi_config.h | 98 + include/efi_loader.h | 53 + include/menu.h | 3 + lib/efi_loader/efi_bootmgr.c | 7 + lib/efi_loader/efi_boottime.c | 52 +- lib/efi_loader/efi_console.c | 70 + lib/efi_loader/efi_disk.c | 50 + lib/efi_loader/efi_file.c | 75 +- test/py/tests/test_eficonfig/conftest.py | 40 + .../py/tests/test_eficonfig/test_eficonfig.py | 354 +++ 19 files changed, 3437 insertions(+), 53 deletions(-) create mode 100644 cmd/eficonfig.c create mode 100644 doc/usage/cmd/eficonfig.rst create mode 100644 include/efi_config.h create mode 100644 test/py/tests/test_eficonfig/conftest.py create mode 100644 test/py/tests/test_eficonfig/test_eficonfig.py -- 2.17.1

2 12

[PATCH] arm: mvebu: Mark constant data with const keyword
by Pali Rohár 13 Sep '22

13 Sep '22

Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/arm/mach-kirkwood/cpu.c | 2 +- arch/arm/mach-kirkwood/include/mach/cpu.h | 2 +- arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-mvebu/include/mach/cpu.h | 2 +- arch/arm/mach-mvebu/mbus.c | 2 +- arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +- arch/arm/mach-mvebu/system-controller.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 80f893ab369a..df3e8f11782a 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -52,7 +52,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) return (0x0000ffff & j); } -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ { KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index d8639c60352b..9eec786fe8fc 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -150,7 +150,7 @@ struct kwgpio_registers { unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_mbus_probe(const struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 9a80440d1a9e..1f8cdf8744e6 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -20,7 +20,7 @@ #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* SPI */ { MBUS_SPI_BASE, MBUS_SPI_SIZE, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 3de10de745ef..574a9264172c 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -139,7 +139,7 @@ extern u8 serdes_pex_pulse_width[]; unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_mbus_probe(const struct mbus_win windows[], int count); u32 mvebu_get_nand_clock(void); void __noreturn return_to_bootrom(void); diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 7092f6cc10c2..959ca8e92602 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -469,7 +469,7 @@ int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr) return 0; } -int mvebu_mbus_probe(struct mbus_win windows[], int count) +int mvebu_mbus_probe(const struct mbus_win windows[], int count) { int win; int ret; diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 4a4f93ccf93f..ac98dee2993d 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -108,7 +108,7 @@ struct serdes_unit_data { u8 serdes_unit_num; }; -static struct serdes_unit_data serdes_type_to_unit_info[] = { +static const struct serdes_unit_data serdes_type_to_unit_info[] = { {PEX_UNIT_ID, 0,}, {PEX_UNIT_ID, 1,}, {PEX_UNIT_ID, 2,}, diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index ea858b269e82..e90aff0c3379 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -86,7 +86,7 @@ static const struct udevice_id mvebu_reset_of_match[] = { { }, }; -static struct reset_ops mvebu_reset_ops = { +static const struct reset_ops mvebu_reset_ops = { .of_xlate = mvebu_reset_of_xlate, .request = mvebu_reset_request, .rfree = mvebu_reset_free, -- 2.20.1

2 2