December 2022 - U-Boot

[RFC PATCH] riscv: cpu: check U-Mode before counteren write
by Nikita Shubin 01 Feb '23

01 Feb '23

From: Nikita Shubin <n.shubin(a)yadro.com> The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by: Nikita Shubin <n.shubin(a)yadro.com> --- This seems obvious at first glance, but i've never seen 'u' extension enywhere in "riscv,isa" device tree property, even qemu doesn't set this, and if we simply enable this check - this will break existing board for sure. We can rely on MISA completely if we are in M-Mode, as we currently check only 'd', 'f' and 'u', which are standart and nothing fancy. --- arch/riscv/cpu/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 0f323b26b3..917f71c8d7 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -31,7 +31,9 @@ u32 available_harts_lock = 1; static inline bool supports_extension(char ext) { -#ifdef CONFIG_CPU +#if CONFIG_IS_ENABLED(RISCV_MMODE) + return csr_read(CSR_MISA) & (1 << (ext - 'a')); +#elif CONFIG_CPU struct udevice *dev; char desc[32]; @@ -48,13 +50,9 @@ static inline bool supports_extension(char ext) return false; #else /* !CONFIG_CPU */ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - return csr_read(CSR_MISA) & (1 << (ext - 'a')); -#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */ #warning "There is no way to determine the available extensions in S-mode." #warning "Please convert your board to use the RISC-V CPU driver." return false; -#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ #endif /* CONFIG_CPU */ } @@ -102,12 +100,14 @@ int riscv_cpu_setup(void *ctx, struct event *event) * Enable perf counters for cycle, time, * and instret counters only */ + if (supports_extension('u')) { #ifdef CONFIG_RISCV_PRIV_1_9 - csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); - csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); #else - csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); #endif + } /* Disable paging */ if (supports_extension('s')) -- 2.37.4

2 1

[PATCH 00/11] imx: convert to DM_SERIAL
by Peng Fan (OSS) 01 Feb '23

01 Feb '23

From: Peng Fan <peng.fan(a)nxp.com> This patchset is to convert mx6ull/z_evk, mx6sl[l]evk, mx6sxsbareauto, mx6sabreauto, mx6sabresd to DM_SERIAL Patch 1 is a fix found when testing mx6sllevk Peng Fan (11): imx: implement get_effective_memsize imx: mx6ull_14x14_evk: select DM_SERIAL imx: mx6ulz: select DM_SERIAL imx: mx6ull/z_14x14_evk: clean up UART iomux imx: mx6sllevk: correct pmic name imx: mx6sllevk: select DM_SERIAL imx: mx6slevk: select DM_SERIAL imx: mx6ul_evk: select DM_SERIAL imx: mx6sxsabreauto: select DM_SERIAL imx: mx6sabreauto_defconfig: select DM_SERIAL imx: mx6sabresd: select DM_SERIAL arch/arm/dts/imx6sll-evk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 4 ++++ arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi | 8 ++++++++ arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi | 8 ++++++++ arch/arm/mach-imx/cache.c | 14 ++++++++++++++ board/freescale/mx6sllevk/mx6sllevk.c | 18 +----------------- .../freescale/mx6sxsabreauto/mx6sxsabreauto.c | 16 ---------------- board/freescale/mx6ullevk/mx6ullevk.c | 16 ---------------- configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_defconfig | 1 + configs/mx6slevk_spinor_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sllevk_defconfig | 1 + configs/mx6sllevk_plugin_defconfig | 1 + configs/mx6sxsabreauto_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ulz_14x14_evk_defconfig | 1 + 21 files changed, 56 insertions(+), 49 deletions(-) create mode 100644 arch/arm/dts/imx6sll-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ulz-14x14-evk-u-boot.dtsi -- 2.36.0

9 42

[PATCH 0/2] board: gateworks: venice: poll I2C to wait for GSC
by Tim Harvey 31 Jan '23

31 Jan '23

The first patch brings the dts up to date with upstream Linux commits. The second patch implements polling the I2C lines to wait for the Gateworks System Controller to be ready before reading the board EEPROM. Tim Harvey (2): arm: dts: imx8m*-venice-*: add I2C GPIO bus recovery support board: gateworks: venice: poll I2C lines to wait for GSC firmware arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +++++++++++-- arch/arm/dts/imx8mm-venice-gw7901.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-gw7902.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-gw7903.dts | 36 +++++++++++++++++-- arch/arm/dts/imx8mm-venice-gw7904.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-venice.dts | 12 ++++++- arch/arm/dts/imx8mn-venice-gw7902.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-venice.dts | 12 ++++++- arch/arm/dts/imx8mp-venice-gw74xx.dts | 48 +++++++++++++++++++++++--- arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-venice.dts | 12 ++++++- board/gateworks/venice/spl.c | 39 +++++++++++++-------- 14 files changed, 345 insertions(+), 42 deletions(-) -- 2.25.1

3 8

[PATCH v1] imx8: scu_api: sync sc_rm_is_pad_owned api change
by Marcel Ziswiler 31 Jan '23

31 Jan '23

From: Ye Li <ye.li(a)nxp.com> SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This requires u-boot to update API implementation, since it will cause compatible issue. Otherwise all pad checking will have problem and cause pad setting not continue. Due to the compatible issue, the new u-boot only works with new SCFW (API version: 1.21 and later). old scfw + old u-boot: API overflow issue old scfw + new u-boot, or new scfw + old u-boot: API compatible issue new scfw + new u-boot: Working Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by : Jason Liu <Jason.hui.liu(a)nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- I stumbled over this one when working on the apalis-imx8 boot issue fix and support refresh [1] where I noticed that using the latest SCFW Ethernet won't come up. Through manual testing, I identified SCFW 1.3.1 to still work fine so I settled with that for the time being. Re-visiting this SCFW incompatibility issue again now I stumbled over this downstream commit [2] which I believe would be very suitable for upstreaming as well. With that latest SCFW 1.14.0 works fine again. So here it goes. [1] https://patchwork.ozlabs.org/project/uboot/cover/20221212000930.45505-1-mar… [2] https://github.com/nxp-imx/uboot-imx/commit/9be6761bccd008de16191aed325004b… arch/arm/include/asm/arch-imx8/sci/rpc.h | 2 +- drivers/misc/imx8/scu_api.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 9f55904f44..39de7f0e3e 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -11,7 +11,7 @@ /* Defines */ #define SCFW_API_VERSION_MAJOR 1U -#define SCFW_API_VERSION_MINOR 15U +#define SCFW_API_VERSION_MINOR 21U #define SC_RPC_VERSION 1U diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 27ecce710f..8f546e9b3f 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -788,7 +788,7 @@ sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) RPC_VER(&msg) = SC_RPC_VERSION; RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; RPC_FUNC(&msg) = (u8)RM_FUNC_IS_PAD_OWNED; - RPC_U8(&msg, 0U) = (u8)pad; + RPC_U16(&msg, 0U) = (u16)pad; RPC_SIZE(&msg) = 2U; ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); -- 2.35.1

3 2

[PATCH] configs: imx8m: Prepare imx8m-beacon boards for HAB support
by Adam Ford 31 Jan '23

31 Jan '23

In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index a0715e8091..eadb2234b0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -233,6 +233,9 @@ config TARGET_IMX8MM_BEACON select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_IMX8MN_BEACON bool "imx8mn Beacon Embedded devkit" @@ -240,6 +243,9 @@ config TARGET_IMX8MN_BEACON select IMX8MN select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select ARCH_MISC_INIT + select SPL_CRYPTO if SPL config TARGET_PHYCORE_IMX8MM bool "PHYTEC PHYCORE i.MX8MM" -- 2.34.1

2 1

[PATCH] arm64: dts: imx8m{m, n}-venice-gw7902: add gpio pins for new board revision
by Tim Harvey 31 Jan '23

31 Jan '23

Add gpio pins present on new board revision: * LTE modem support (imx8mm-gw7902 only) - lte_pwr# - lte_rst - lte_int * M2 power enable - m2_pwr_en * off-board 4.0V supply - vdd_4p0_en Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mm-venice-gw7902.dts | 12 ++++++++---- arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi | 14 ++++++++++++++ arch/arm/dts/imx8mn-venice-gw7902.dts | 8 ++++---- 4 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi index f21e46b12dd7..d58a7d14b631 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mm-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -96,6 +103,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts index 31f4c735fe4f..921bffae0cc9 100644 --- a/arch/arm/dts/imx8mm-venice-gw7902.dts +++ b/arch/arm/dts/imx8mm-venice-gw7902.dts @@ -261,7 +261,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -283,7 +283,8 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "lte_pwr#", "lte_rst", "lte_int", "", + "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -738,14 +739,19 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -779,8 +785,6 @@ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi index 17e6828c79f8..10656ce903a5 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi @@ -6,6 +6,13 @@ #include "imx8mn-venice-u-boot.dtsi" &gpio1 { + m2pwren { + gpio-hog; + output-low; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "m2_pwren"; + }; + m2rst { gpio-hog; output-low; @@ -54,6 +61,13 @@ line-name = "app_gpio1"; }; + vdd4p0en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "vdd_4p0_en"; + }; + uart1rs485 { gpio-hog; output-low; diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts index dd4302ac1de4..029ccdbee7d5 100644 --- a/arch/arm/dts/imx8mn-venice-gw7902.dts +++ b/arch/arm/dts/imx8mn-venice-gw7902.dts @@ -256,7 +256,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -278,7 +278,7 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -689,10 +689,12 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -726,8 +728,6 @@ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; -- 2.25.1

2 1

[PATCH] engicam: imx6: migrate to DM_SERIAL
by Suniel Mahesh 31 Jan '23

31 Jan '23

From: Michael Trimarchi <michael(a)amarulasolutions.com> Add the needed DT overrides and configs to enable UART in SPL. Cc: Fabio Estevam <festevam(a)gmail.com> Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> Tested-by: Suniel Mahesh <sunil(a)amarulasolutions.com> --- Note: Tested this patch on Engicam Starter Kit with I.CORE - M6 (MCIMX6Q7CVT08AC) SOM. --- arch/arm/dts/imx6qdl-icore-u-boot.dtsi | 16 ++++++++++++++++ arch/arm/dts/imx6ul-isiot-u-boot.dtsi | 16 ++++++++++++++++ board/engicam/common/spl.c | 20 +++----------------- configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6qdl_icore_mipi_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + 9 files changed, 41 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi index f95d49d00d..12e46e38f6 100644 --- a/arch/arm/dts/imx6qdl-icore-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-icore-u-boot.dtsi @@ -5,6 +5,22 @@ #include "imx6qdl-u-boot.dtsi" +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi index aa8e9804bf..7213e71989 100644 --- a/arch/arm/dts/imx6ul-isiot-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-isiot-u-boot.dtsi @@ -5,6 +5,22 @@ #include "imx6ul-u-boot.dtsi" +&soc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + &usdhc1 { u-boot,dm-spl; }; diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 6a0612481a..f1ccdc3343 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -26,20 +26,6 @@ #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/video.h> -#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -static iomux_v3_cfg_t const uart_pads[] = { -#ifdef CONFIG_MX6QDL - IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), -#elif CONFIG_MX6UL - IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)), - IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)), -#endif -}; - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { @@ -421,12 +407,12 @@ void board_init_f(ulong dummy) if (!(is_mx6ul())) gpr_init(); - /* iomux */ - SETUP_IOMUX_PADS(uart_pads); - /* setup GP timer */ timer_init(); + /* Enable device tree and early DM support*/ + spl_early_init(); + /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index fe4866e2f5..af5873a784 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -66,6 +66,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 2cb995e7ae..8535627049 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -67,6 +67,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index 90eb153c45..8dd5e89511 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -74,5 +74,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 9f6d29a268..46497fbde1 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -90,6 +90,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 2cb995e7ae..8535627049 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -67,6 +67,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_VIDEO=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index ee2c597bcb..3bab6739d0 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -72,4 +72,5 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -- 2.25.1

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[PATCH 0/1] configs: imx8mp_evk: revert to old ram settings
by Manoj Sai 31 Jan '23

31 Jan '23

revert the ram settings of imx8mp evk which are changed with commit id : 864ac2cf383e ("board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit") Manoj Sai (1): configs: imx8mp_evk: revert to old ram settings include/configs/imx8mp_evk.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1

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[PATCH 1/2] imx: mx6sabreauto: convert to DM_I2C
by Peng Fan (OSS) 31 Jan '23

31 Jan '23

From: Peng Fan <peng.fan(a)nxp.com> Convert to DM_I2C Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- configs/mx6sabreauto_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 2566f2a97fc..405f8f3d549 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -75,7 +75,7 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y -- 2.36.0

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[PATCH] configs: imx8mn_beacon_fspi: Add config for booting from QSPI
by Adam Ford 31 Jan '23

31 Jan '23

The imx8mn-beacon SOM has a QSPI part on it connected to the FlexSPI controller. Add a defconfig option which supports booting from the QSPI NOR flash instead of sd/mmc. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig new file mode 100644 index 0000000000..27b60824f3 --- /dev/null +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -0,0 +1,156 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit" +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_BEACON=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SYS_LOAD_ADDR=0x42000000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x44000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" +CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x950000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x980000 +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOOTM_NETBSD is not set +CONFIG_SYS_BOOTM_LEN=0x800000 +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="FEC" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_BD71837=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x0 +CONFIG_IMX_WATCHDOG=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FSPI_CONF_HEADER=y +CONFIG_FSPI_CONF_FILE="fspi_header.bin" -- 2.34.1

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