December 2022 - U-Boot

[PATCH 0/5] Support the required clocks to enable USB on SAM9X60
by Sergiu Moga 21 Jan '23

21 Jan '23

This patch series originates from a bigger patch series: https://lists.denx.de/pipermail/u-boot/2022-December/502865.html A driver for clock operations on SAM9X60's USB clock has been added as well as its registration on CCF. In order for USB to work properly, the UPLL and USBCK need an initial frequency before probing the OHCI/EHCI driver. Furthermore enable this driver in the defconfigs. Claudiu Beznea (1): clk: at91: pmc: export clock setup to pmc Sergiu Moga (4): clk: at91: Add support for sam9x60 USB clock clk: at91: sam9x60: Register the required clocks for USB clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates configs: at91: sam9x60: Add required configs for the USB clock configs/sam9x60_curiosity_mmc_defconfig | 1 + configs/sam9x60ek_mmc_defconfig | 1 + configs/sam9x60ek_nandflash_defconfig | 1 + configs/sam9x60ek_qspiflash_defconfig | 1 + drivers/clk/at91/Kconfig | 7 ++ drivers/clk/at91/Makefile | 1 + drivers/clk/at91/clk-sam9x60-usb.c | 157 ++++++++++++++++++++++++ drivers/clk/at91/pmc.c | 42 +++++++ drivers/clk/at91/pmc.h | 27 ++++ drivers/clk/at91/sam9x60.c | 63 ++++++++++ drivers/clk/at91/sama7g5.c | 48 +------- 11 files changed, 307 insertions(+), 42 deletions(-) create mode 100644 drivers/clk/at91/clk-sam9x60-usb.c -- 2.34.1

3 11

[PATCH v2] cmd: clk: probe the clock before dump them
by Patrick Delaunay 21 Jan '23

21 Jan '23

The clock UCLASS need to be probed to allow availability of the private data (struct clk *), get in show_clks() with dev_get_clk_ptr() before use them. Without this patch the clock dump can cause crash because all the private data are not available before calling the API clk_get_rate(). It is the case for the SCMI clocks, priv->channel is needed for scmi_clk_get_rate() and it is initialized only in scmi_clk_probe(). This issue causes a crash for "clk dump" command on STM32MP135F-DK board for SCMI clock not yet probed. Fixes: 1a725e229096 ("clk: fix clock tree dump to properly dump out every registered clock") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- Changes in v2: - simplify the patch after Simon review of V1: always probe the clk device before call to show_clks(), by using device_foreach_child_probe() and uclass_foreach_dev_probe() - test UCLASS_CLK only when show_clks is called for child device cmd/clk.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/cmd/clk.c b/cmd/clk.c index a483fd898122..ff7c7649a159 100644 --- a/cmd/clk.c +++ b/cmd/clk.c @@ -22,7 +22,7 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) u32 rate; clkp = dev_get_clk_ptr(dev); - if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) { + if (clkp) { parent = clk_get_parent(clkp); if (!IS_ERR(parent) && depth == -1) return; @@ -49,10 +49,11 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) printf("%s\n", dev->name); } - list_for_each_entry(child, &dev->child_head, sibling_node) { + device_foreach_child_probe(child, dev) { + if (device_get_uclass_id(child) != UCLASS_CLK) + continue; if (child == dev) continue; - is_last = list_is_last(&child->sibling_node, &dev->child_head); show_clks(child, depth, (last_flag << 1) | is_last); } @@ -61,17 +62,11 @@ static void show_clks(struct udevice *dev, int depth, int last_flag) int __weak soc_clk_dump(void) { struct udevice *dev; - struct uclass *uc; - int ret; - - ret = uclass_get(UCLASS_CLK, &uc); - if (ret) - return ret; printf(" Rate Usecnt Name\n"); printf("------------------------------------------\n"); - uclass_foreach_dev(dev, uc) + uclass_foreach_dev_probe(UCLASS_CLK, dev) show_clks(dev, -1, 0); return 0; -- 2.25.1

2 2

[PATCH v1] clk: nuvoton: fix bug for calculate pll clock
by Jim Liu 21 Jan '23

21 Jan '23

Fix bug for npcm7xx bmc calculate pll clock. PLLCON1 need to divide by 2. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/clk/nuvoton/clk_npcm7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/nuvoton/clk_npcm7xx.c b/drivers/clk/nuvoton/clk_npcm7xx.c index a12aaa2f4c..b23dd37af6 100644 --- a/drivers/clk/nuvoton/clk_npcm7xx.c +++ b/drivers/clk/nuvoton/clk_npcm7xx.c @@ -25,7 +25,7 @@ static const struct parent_data apb_parent[] = {{NPCM7XX_CLK_AHB, 0}}; static struct npcm_clk_pll npcm7xx_clk_plls[] = { {NPCM7XX_CLK_PLL0, NPCM7XX_CLK_REFCLK, PLLCON0, 0}, - {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, 0}, + {NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, POST_DIV2}, {NPCM7XX_CLK_PLL2, NPCM7XX_CLK_REFCLK, PLLCON2, 0}, {NPCM7XX_CLK_PLL2DIV2, NPCM7XX_CLK_REFCLK, PLLCON2, POST_DIV2} }; -- 2.17.1

2 2

[PATCH 0/3] clk: imx8mn: miscellaneous cleanups and bug fixes
by Dario Binacchi 21 Jan '23

21 Jan '23

This series is a backport of the linux seris [1]. Like that series, this one was also tested on the BSH SystemMaster (SMM) S2 board. [1] https://lore.kernel.org/all/20221117113637.1978703-1-dario.binacchi@amarula… Dario Binacchi (3): clk: imx8mn: rename vpu_pll to m7_alt_pll clk: imx: rename video_pll1 to video_pll clk: imx8mn: fix imx8mn_enet_phy_sels clocks list drivers/clk/imx/clk-imx8mn.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) -- 2.32.0

2 7

[PATCH v1 00/17] Basic StarFive JH7110 RISC-V SoC support
by Yanhong Wang 21 Jan '23

21 Jan '23

This series of patches base on the latest branch/master, and add support for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for this to be achieved, the respective DT nodes have been added, and the required defconfigs have been added to the boards' defconfig. What is more, the basic required DM drivers have been added, such as reset, clock, pinctrl, uart, ram etc. Note that the register base address of reset controller is same with the clock controller. Therefore, there is no device tree node alone for reset driver. It binds device node in the clock driver. The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which equip with JH7110 SoC and works normally. For more information and support, you can visit RVspace wiki[1]. [1] https://wiki.rvspace.org/ Jianlong Huang (1): dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions Kuan Lim Lee (1): pinctrl: starfive: Add StarFive JH7110 driver Yanhong Wang (15): riscv: cpu: jh7110: Add support for jh7110 SoC cache: starfive: Add StarFive JH7110 support dt-bindings: reset: Add StarFive JH7110 reset definitions reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC dt-bindings: clock: Add StarFive JH7110 clock definitions clk: starfive: Add StarFive JH7110 clock driver ram: starfive: add ddr driver board: starfive: add StarFive VisionFive v2 board support riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC board: starfive: Add Kconfig for StarFive VisionFive v2 Board board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig riscv: dts: jh7110: Add initial StarFive JH7110 device tree riscv: dts: jh7110: Add initial u-boot device tree riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree configs: starfive: add starfive_visionfive2_defconfig arch/riscv/Kconfig | 5 + arch/riscv/cpu/jh7110/Kconfig | 28 + arch/riscv/cpu/jh7110/Makefile | 10 + arch/riscv/cpu/jh7110/cpu.c | 23 + arch/riscv/cpu/jh7110/dram.c | 38 + arch/riscv/cpu/jh7110/spl.c | 56 + arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/jh7110-u-boot.dtsi | 86 + arch/riscv/dts/jh7110.dtsi | 497 +++++ .../dts/starfive_visionfive2-u-boot.dtsi | 66 + arch/riscv/dts/starfive_visionfive2.dts | 234 ++ .../include/asm/arch-jh7110/jh7110-regs.h | 20 + arch/riscv/include/asm/arch-jh7110/spl.h | 13 + board/starfive/visionfive2/Kconfig | 53 + board/starfive/visionfive2/MAINTAINERS | 7 + board/starfive/visionfive2/Makefile | 7 + board/starfive/visionfive2/spl.c | 119 + .../visionfive2/starfive_visionfive2.c | 39 + configs/starfive_visionfive2_defconfig | 72 + drivers/cache/cache-sifive-ccache.c | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/starfive/Kconfig | 15 + drivers/clk/starfive/Makefile | 4 + drivers/clk/starfive/clk-jh7110-pll.c | 362 +++ drivers/clk/starfive/clk-jh7110.c | 651 ++++++ drivers/clk/starfive/clk.h | 42 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/starfive/Kconfig | 16 + drivers/pinctrl/starfive/Makefile | 6 + drivers/pinctrl/starfive/pinctrl-jh7110-aon.c | 113 + drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 399 ++++ drivers/pinctrl/starfive/pinctrl-starfive.c | 428 ++++ drivers/pinctrl/starfive/pinctrl-starfive.h | 55 + drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 4 +- drivers/ram/starfive/Kconfig | 5 + drivers/ram/starfive/Makefile | 11 + drivers/ram/starfive/ddrcsr_boot.c | 340 +++ drivers/ram/starfive/ddrphy_start.c | 280 +++ drivers/ram/starfive/ddrphy_train.c | 384 ++++ drivers/ram/starfive/ddrphy_utils.c | 1956 +++++++++++++++++ drivers/ram/starfive/starfive_ddr.c | 162 ++ drivers/ram/starfive/starfive_ddr.h | 66 + drivers/reset/Kconfig | 16 + drivers/reset/Makefile | 1 + drivers/reset/reset-jh7110.c | 158 ++ include/configs/starfive-visionfive2.h | 18 + include/dt-bindings/clock/starfive-jh7110.h | 271 +++ .../pinctrl/pinctrl-starfive-jh7110.h | 427 ++++ include/dt-bindings/reset/starfive-jh7110.h | 183 ++ 52 files changed, 7752 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/jh7110/Kconfig create mode 100644 arch/riscv/cpu/jh7110/Makefile create mode 100644 arch/riscv/cpu/jh7110/cpu.c create mode 100644 arch/riscv/cpu/jh7110/dram.c create mode 100644 arch/riscv/cpu/jh7110/spl.c create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110.dtsi create mode 100644 arch/riscv/dts/starfive_visionfive2-u-boot.dtsi create mode 100644 arch/riscv/dts/starfive_visionfive2.dts create mode 100644 arch/riscv/include/asm/arch-jh7110/jh7110-regs.h create mode 100644 arch/riscv/include/asm/arch-jh7110/spl.h create mode 100644 board/starfive/visionfive2/Kconfig create mode 100644 board/starfive/visionfive2/MAINTAINERS create mode 100644 board/starfive/visionfive2/Makefile create mode 100644 board/starfive/visionfive2/spl.c create mode 100644 board/starfive/visionfive2/starfive_visionfive2.c create mode 100644 configs/starfive_visionfive2_defconfig create mode 100644 drivers/clk/starfive/Kconfig create mode 100644 drivers/clk/starfive/Makefile create mode 100644 drivers/clk/starfive/clk-jh7110-pll.c create mode 100644 drivers/clk/starfive/clk-jh7110.c create mode 100644 drivers/clk/starfive/clk.h create mode 100644 drivers/pinctrl/starfive/Kconfig create mode 100644 drivers/pinctrl/starfive/Makefile create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-aon.c create mode 100644 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.c create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive.h create mode 100644 drivers/ram/starfive/Kconfig create mode 100644 drivers/ram/starfive/Makefile create mode 100644 drivers/ram/starfive/ddrcsr_boot.c create mode 100644 drivers/ram/starfive/ddrphy_start.c create mode 100644 drivers/ram/starfive/ddrphy_train.c create mode 100644 drivers/ram/starfive/ddrphy_utils.c create mode 100644 drivers/ram/starfive/starfive_ddr.c create mode 100644 drivers/ram/starfive/starfive_ddr.h create mode 100644 drivers/reset/reset-jh7110.c create mode 100644 include/configs/starfive-visionfive2.h create mode 100644 include/dt-bindings/clock/starfive-jh7110.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h create mode 100644 include/dt-bindings/reset/starfive-jh7110.h base-commit: 8f170408774b30aa4ee91b3cc90ba09b564d4651 -- 2.17.1

4 30

[PATCH v2] net: eth-uclass: revalidate priv after stop() in eth_halt()
by Niel Fourie 20 Jan '23

20 Jan '23

In eth_halt(), reread and revalidate priv after calling stop(), as it may have been freed, leaving a dangling pointer. In the ethernet gadget implementation, the gadget device gets probed during start() and removed during stop(), which includes freeing `uclass_priv_` to which `priv` is pointing. Writing to `priv` after stop() may corrupt the `fd` member of `struct malloc_chunk`, which represents the freed block, and could cause hard-to-debug crashes on subsequent calls to malloc()/free(). Signed-off-by: Niel Fourie <lusus(a)denx.de> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Lukasz Majewski <lukma(a)denx.de> --- Changes for v2: - Revalidate priv instead of changing state before stop() - Added explanational comment This patch my be dropped if the patch which addresses the root cause ("usb: gadget: ether: split start/stop from init/halt") is accepted. net/eth-uclass.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/net/eth-uclass.c b/net/eth-uclass.c index f41da4b37b3..7d5783b5cab 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -341,8 +341,11 @@ void eth_halt(void) priv = dev_get_uclass_priv(current); if (!priv || !priv->running) return; - eth_get_ops(current)->stop(current); + /* Ethernet gadget frees priv during stop, workaround until fixed... */ + priv = dev_get_uclass_priv(current); + if (!priv || !priv->running) + return; priv->state = ETH_STATE_PASSIVE; priv->running = false; } -- 2.38.1

3 11

[PATCH 01/17] global: Move remaining CONFIG_SYS_NOR_* to CFG_SYS_NOR_*
by Tom Rini 20 Jan '23

20 Jan '23

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- board/freescale/ls1043aqds/ls1043aqds.c | 48 +++++++------- board/freescale/ls1043ardb/ls1043ardb.c | 32 +++++----- board/freescale/ls1046aqds/ls1046aqds.c | 48 +++++++------- board/freescale/ls1088a/ls1088a.c | 26 ++++---- include/configs/P1010RDB.h | 42 ++++++------- include/configs/T102xRDB.h | 38 +++++------ include/configs/T104xRDB.h | 48 +++++++------- include/configs/T208xQDS.h | 60 +++++++++--------- include/configs/T208xRDB.h | 36 +++++------ include/configs/T4240RDB.h | 48 +++++++------- include/configs/km/pg-wcom-ls102xa.h | 24 +++---- include/configs/kmcent2.h | 34 +++++----- include/configs/ls1021aqds.h | 60 +++++++++--------- include/configs/ls1021atwr.h | 24 +++---- include/configs/ls1043aqds.h | 84 ++++++++++++------------- include/configs/ls1043ardb.h | 64 +++++++++---------- include/configs/ls1046aqds.h | 84 ++++++++++++------------- include/configs/ls1088aqds.h | 66 +++++++++---------- include/configs/ls1088ardb.h | 26 ++++---- include/configs/ls2080aqds.h | 66 +++++++++---------- include/configs/ls2080ardb.h | 38 +++++------ 21 files changed, 498 insertions(+), 498 deletions(-) diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 481d3a5d9bd9..5fe40c4bdb25 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -59,13 +59,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, @@ -73,13 +73,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { @@ -128,26 +128,26 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 7f3212819885..a8a7263a6538 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -33,15 +33,15 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor", - CONFIG_SYS_NOR_CSPR, - CONFIG_SYS_NOR_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_CSPR, + CFG_SYS_NOR_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, @@ -89,15 +89,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor", - CONFIG_SYS_NOR_CSPR, - CONFIG_SYS_NOR_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_CSPR, + CFG_SYS_NOR_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index de6828673b50..97d71dbf2adb 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -43,13 +43,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, @@ -57,13 +57,13 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { @@ -112,26 +112,26 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nor1", CONFIG_SYS_NOR1_CSPR, CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index b70c198188bf..ff3abc830229 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -43,13 +43,13 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor0", CONFIG_SYS_NOR0_CSPR_EARLY, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, 0, CONFIG_SYS_NOR0_CSPR, @@ -59,17 +59,17 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { "nor1", CONFIG_SYS_NOR1_CSPR_EARLY, CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK_EARLY, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR_AMASK_EARLY, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, 0, CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR_AMASK, + CFG_SYS_NOR_AMASK, }, { "nand", diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 3288969ce8ca..154bf584f29f 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -144,22 +144,22 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) +#define CFG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5) -#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ +#define CFG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ FTIM1_NOR_TRAD_NOR(0x0f) -#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -244,21 +244,21 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6eaa4144959d..978cc6714ec6 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -139,26 +139,26 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) #endif -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -247,21 +247,21 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a9e6cfad4bc1..f26e9d6e8692 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -100,12 +100,12 @@ #define CONFIG_SYS_FLASH_BASE 0xe8000000 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR_EXT (0xf) +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* * TDM Definition @@ -113,18 +113,18 @@ #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -221,23 +221,23 @@ #define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 47f499031e89..62f07108126d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -109,21 +109,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -211,37 +211,37 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 111f2e6245f9..0616f8a86dff 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -98,22 +98,22 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -187,21 +187,21 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b8232986be68..2eb4e73efa9e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -175,21 +175,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 +#define CFG_SYS_NOR_FTIM3 0x0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -242,21 +242,21 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK @@ -268,12 +268,12 @@ #endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 /* CPLD on IFC */ #define CONFIG_SYS_CPLD_BASE 0xffdf0000 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index d883b188ce3a..cc8c37ec0bf5 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -41,25 +41,25 @@ CSPR_TE | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ CSOR_NOR_ADM_SHIFT(0x4) | \ CSOR_NOR_NOR_MODE_ASYNC_NOR | \ CSOR_NOR_TRHZ_20 | \ CSOR_NOR_BCTLD) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x7) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x21) | \ FTIM1_NOR_TSEQRAD_NOR(0x21)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TCH(0x1) | \ FTIM2_NOR_TWPH(0x6) | \ FTIM2_NOR_TWP(0xb)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -69,12 +69,12 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* NAND Flash Definitions */ #define CFG_SYS_NAND_BASE 0x68000000 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 51ee68655333..16fd6d562d41 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -193,38 +193,38 @@ #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR_CSPR_EXT (0x0f) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR_EXT (0x0f) +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NOR | /* MSEL = NOR */\ CSPR_V) /* valid */ -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ +#define CFG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\ CSOR_NOR_TRHZ_20 | \ CSOR_NOR_BCTLD) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x7) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x21) | \ FTIM1_NOR_TSEQRAD_NOR(0x21)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \ FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TWP(0xb) | \ FTIM2_NOR_TWPH(0x6)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CFG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* More NOR Flash params */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 7d89b5389522..6b23134ecc99 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -44,21 +44,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_WRITE_SWAPPED_DATA @@ -166,20 +166,20 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -191,20 +191,20 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 2c96b6f77895..1ac59a2d4597 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -74,23 +74,23 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWP(0x1c) | \ FTIM2_NOR_TWPH(0x0e)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -126,12 +126,12 @@ #define CONFIG_SYS_FPGA_FTIM3 0x0 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 21263705c803..3b51cb8f174a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -54,21 +54,21 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} @@ -174,20 +174,20 @@ #ifdef CONFIG_TFABOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK @@ -216,20 +216,20 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -241,20 +241,20 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 51667f202580..76251fde57cc 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -18,29 +18,29 @@ /* * NOR Flash Definitions */ -#define CONFIG_SYS_NOR_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSPR \ +#define CFG_SYS_NOR_CSPR_EXT (0x0) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) /* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x1) | \ FTIM0_NOR_TAVDS(0x0) | \ FTIM0_NOR_TEAHC(0xc)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ FTIM1_NOR_TRAD_NOR(0xb) | \ FTIM1_NOR_TSEQRAD_NOR(0x9)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x8) | \ FTIM2_NOR_TWP(0x10)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_SYS_IFC_CCR 0x01000000 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } @@ -117,14 +117,14 @@ /* IFC Timing Params */ #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR @@ -145,23 +145,23 @@ #define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d51209c60f2d..d565492f1d1c 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -69,22 +69,22 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} @@ -190,20 +190,20 @@ #ifdef CONFIG_TFABOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK @@ -232,20 +232,20 @@ #define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -257,20 +257,20 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index ae452075ac0d..b75d4ccf5cfd 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -23,8 +23,8 @@ */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) #define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -46,19 +46,19 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TAVDS(0x6) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ FTIM2_NOR_TCH(0x8) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH @@ -158,22 +158,22 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK @@ -214,22 +214,22 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 2ca1384c2315..27510adae677 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -21,8 +21,8 @@ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) #define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -34,16 +34,16 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ FTIM0_NOR_TEADC(0x1) | \ FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ FTIM2_NOR_TCH(0x0) | \ FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH @@ -153,12 +153,12 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index d9e11cc19179..7315790f1fe1 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -26,8 +26,8 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) #define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -49,18 +49,18 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH @@ -147,22 +147,22 @@ #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK @@ -178,22 +178,22 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 086c46902c86..daca3be16c51 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -33,8 +33,8 @@ #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) #define CONFIG_SYS_NOR0_CSPR \ (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ @@ -46,18 +46,18 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CFG_SYS_NOR_FTIM3 0x04000000 #define CONFIG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH @@ -140,12 +140,12 @@ #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK @@ -160,12 +160,12 @@ #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -- 2.25.1

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[PATCH 1/2] drivers: watchdog: Enhance watchdog support in SPL for Stratix 10 and Agilex
by Jit Loon Lim 18 Jan '23

18 Jan '23

From: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Change watchdog default timeout to 10 seconds and enable watchdog before initializing other component (example: DDR). Thus, watchdog need to be fully executed in onchip ram. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/spl_agilex.c | 17 +++++++++-------- arch/arm/mach-socfpga/spl_s10.c | 14 +++++++------- drivers/watchdog/Kconfig | 2 +- 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index ee5a9dc1e2..c279f97cea 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -20,7 +20,7 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> +#include <wdt.h> #include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,13 +40,6 @@ void board_init_f(ulong dummy) writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); -#ifdef CONFIG_HW_WATCHDOG - /* Enable watchdog before initializing the HW */ - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); - hw_watchdog_init(); -#endif - /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR); @@ -60,6 +53,14 @@ void board_init_f(ulong dummy) hang(); } + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary(); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index c20e87cdbe..4044dc335e 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -21,7 +21,7 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> +#include <wdt.h> #include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,12 +41,12 @@ void board_init_f(ulong dummy) writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); -#ifdef CONFIG_HW_WATCHDOG - /* Enable watchdog before initializing the HW */ - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); - hw_watchdog_init(); -#endif + /* + * Enable watchdog as early as possible before initializing other + * component. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); /* ensure all processors are not released prior Linux boot */ writeq(0, CPU_RELEASE_ADDR); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 50e6a1efba..a6c242ac9d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -27,7 +27,7 @@ config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 - default 30000 if ARCH_SOCFPGA + default 10000 if ARCH_SOCFPGA default 16000 if ARCH_SUNXI default 60000 help -- 2.26.2

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[PATCH] arm: kirkwood: Convert to DM Serial for various Kirkwood boards
by Tony Dinh 17 Jan '23

17 Jan '23

For Kirkwood boards, it is necessary to have early malloc in DRAM area when Driver Model for Serial is enabled. Please see Michael's patch here: https://lore.kernel.org/u-boot/20220817193809.1059688-20-michael@walle.cc/ This patch enables the early malloc in DRAM for all Kirkwood boards. Note that this will work for boards that have either non-DM serial and DM_SERIAL. Also, add the CONFIG_KIRKWOOD_COMMON option to enable DM_SERIAL as a common option for boards that have been tested. Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- arch/arm/mach-kirkwood/Kconfig | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index c8a193dd4c..45cc932636 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -12,6 +12,19 @@ config KW88F6281 config SHEEVA_88SV131 bool +config KIRKWOOD_COMMON + bool + select DM_SERIAL + +config HAS_CUSTOM_SYS_INIT_SP_ADDR + bool "Use a custom location for the initial stack pointer address" + default y + +config CUSTOM_SYS_INIT_SP_ADDR + hex "Static location for the initial stack pointer" + depends on HAS_CUSTOM_SYS_INIT_SP_ADDR + default 0x5ff000 + choice prompt "Marvell Kirkwood board select" optional @@ -25,6 +38,7 @@ config TARGET_DREAMPLUG bool "DreamPlug Board" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_DS109 bool "Synology DS109" @@ -40,6 +54,7 @@ config TARGET_SHEEVAPLUG bool "SheevaPlug Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_LSXL bool "lsxl Board" @@ -47,16 +62,19 @@ config TARGET_LSXL select KW88F6281 select BOARD_EARLY_INIT_R select MISC_INIT_R + select KIRKWOOD_COMMON config TARGET_POGO_E02 bool "pogo_e02 Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_POGO_V4 bool "Pogoplug V4 Board" select FEROCEON_88FR131 select KW88F6192 + select KIRKWOOD_COMMON config TARGET_DNS325 bool "dns325 Board" @@ -67,6 +85,7 @@ config TARGET_ICONNECT bool "iconnect Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_KM_KIRKWOOD bool "KM Kirkwood Board" @@ -92,11 +111,13 @@ config TARGET_DOCKSTAR bool "Dockstar Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_GOFLEXHOME bool "GoFlex Home Board" select FEROCEON_88FR131 select KW88F6281 + select KIRKWOOD_COMMON config TARGET_NAS220 bool "BlackArmor NAS220" @@ -107,6 +128,7 @@ config TARGET_NSA310S bool "Zyxel NSA310S" select FEROCEON_88FR131 select KW88F6192 + select KIRKWOOD_COMMON config TARGET_SBx81LIFKW bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16" -- 2.30.2

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[PATCH] dm: pinctrl: Revert "pinctrl: probe pinctrl drivers during post-bind"
by Simon Glass 17 Jan '23

17 Jan '23

This breaks chromebook_coral and it is also not how things should work. If a board needs to bind GPIOs as part of a pinctrl driver this can be done during the bind step, if needed. We cannot probe pinctrl devices when binding as a rule, since it cannot be supported on some platforms. The bind and probe steps are separate in U-Boot and they should remain separate. This reverts commit f9ec791b5e24378b71590877499f8683d5f54dac. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- drivers/pinctrl/pinctrl-uclass.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index ce2d5ddf6d9..a1b85ca87e5 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -403,13 +403,6 @@ static int __maybe_unused pinctrl_post_bind(struct udevice *dev) { const struct pinctrl_ops *ops = pinctrl_get_ops(dev); - /* - * Make sure that the pinctrl driver gets probed after binding - * as some pinctrl drivers also register the GPIO driver during - * probe, and if they are not probed GPIO-s are not registered. - */ - dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); - if (!ops) { dev_dbg(dev, "ops is not set. Do not bind.\n"); return -EINVAL; -- 2.39.0.314.g84b9a713c41-goog

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