December 2022 - U-Boot

[PATCH] spl: fit: Report fdt error for loading u-boot
by Su, Bao Cheng 19 Apr '23

19 Apr '23

Commit 71551055cbdb ("spl: fit: Load devicetree when a Linux payload is found") made a change to not report the spl_fit_append_fdt error at all if next-stage image is u-boot. However for u-boot image without CONFIG_OF_EMBED, the error should be reported to uplevel caller. Otherwise, uplevel caller would think the fdt is already loaded which is obviously not true. Signed-off-by: Baocheng Su <baocheng.su(a)siemens.com> --- common/spl/spl_fit.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index a35be52965..00404935cb 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -770,8 +770,12 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, */ if (os_takes_devicetree(spl_image->os)) { ret = spl_fit_append_fdt(spl_image, info, sector, &ctx); - if (ret < 0 && spl_image->os != IH_OS_U_BOOT) - return ret; + if (ret < 0) { + if (spl_image->os != IH_OS_U_BOOT) + return ret; + else if (!IS_ENABLED(CONFIG_OF_EMBED)) + return ret; + } } firmware_node = node; -- 2.30.2

3 9

[PATCH] mtd: nand: Allow full NAND framework in SPL
by Jit Loon Lim 17 Apr '23

17 Apr '23

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Add configuration option to compile the entire NAND framework into U-Boot SPL. This is required by some drivers, like the Denali NAND, which use a lot of functionality from the NAND core. Signed-off-by: Marek Vasut <marex(a)denx.de> Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/mtd/nand/raw/Kconfig | 7 +++++++ drivers/mtd/nand/raw/Makefile | 16 +++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde..a3bd45f24e 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -694,4 +694,11 @@ config SPL_NAND_SIMPLE expose the cmd_ctrl() interface. endif +config SPL_NAND_FRAMEWORK + bool "Compile the entire NAND framework into the SPL" + help + Some drivers require a lot of functionality from the NAND framework + core when used in SPL. This option allows compiling the full NAND + framework into the SPL instead of it's reduced version. + endif # if NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a398aa9d88..e0f7045fec 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -3,8 +3,16 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +nand-framework-objs := nand.o nand_bbt.o nand_ids.o nand_util.o \ + nand_ecc.o nand_base.o nand_timings.o + ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_NAND_FRAMEWORK +obj-y += $(nand-framework-objs) +NORMAL_DRIVERS=y +endif + ifdef CONFIG_SPL_NAND_DRIVERS NORMAL_DRIVERS=y endif @@ -27,19 +35,13 @@ else # not spl NORMAL_DRIVERS=y -obj-y += nand.o -obj-y += nand_bbt.o -obj-y += nand_ids.o -obj-y += nand_util.o -obj-y += nand_ecc.o -obj-y += nand_base.o obj-y += nand_amd.o obj-y += nand_hynix.o obj-y += nand_macronix.o obj-y += nand_micron.o obj-y += nand_samsung.o obj-y += nand_toshiba.o -obj-y += nand_timings.o +obj-y += $(nand-framework-objs) endif # not spl -- 2.26.2

3 2

[PATCH] arm: dts: rockchip: add support for ROCK 4C+
by FUKAUMI Naoki 08 Apr '23

08 Apr '23

this patch add support for Radxa ROCK 4C Plus. Signed-off-by: FUKAUMI Naoki <naoki(a)radxa.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi | 6 + arch/arm/dts/rk3399-rock-4c-plus.dts | 703 +++++++++++++++++++ arch/arm/dts/rk3399-t-opp.dtsi | 114 +++ configs/rock-4c-plus-rk3399_defconfig | 90 +++ 5 files changed, 914 insertions(+) create mode 100644 arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-rock-4c-plus.dts create mode 100644 arch/arm/dts/rk3399-t-opp.dtsi create mode 100644 configs/rock-4c-plus-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 965895bc2a..74904599d7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -156,6 +156,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ + rk3399-rock-4c-plus.dtb \ rk3399-rock-pi-4a.dtb \ rk3399-rock-pi-4b.dtb \ rk3399-rock-pi-4c.dtb \ diff --git a/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi new file mode 100644 index 0000000000..b7dcd2e05d --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4c-plus-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Radxa Limited + */ + +#include "rk3399-rock-pi-4-u-boot.dtsi" diff --git a/arch/arm/dts/rk3399-rock-4c-plus.dts b/arch/arm/dts/rk3399-rock-4c-plus.dts new file mode 100644 index 0000000000..f9884902f8 --- /dev/null +++ b/arch/arm/dts/rk3399-rock-4c-plus.dts @@ -0,0 +1,703 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2022 Amarula Solutions(India) + */ + +/dts-v1/; +#include <dt-bindings/leds/common.h> +#include "rk3399.dtsi" +#include "rk3399-t-opp.dtsi" + +/ { + model = "Radxa ROCK 4C+"; + compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1 &user_led2>; + + /* USER_LED1 */ + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + /* USER_LED2 */ + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_3v3: vcc-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_phy1: vcc3v3-phy1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_phy1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_host1: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_host0_s0>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_phy1>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x2a>; + rx_delay = <0x21>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vcc_0v9_s0>; + avdd-1v8-supply = <&vcc_1v8_s0>; + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-falling-time-ns = <30>; + i2c-scl-rising-time-ns = <180>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5_s3>; + vcc6-supply = <&vcc_buck5_s3>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5_s3: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_buck5_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_0v9_s3: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcc_0v9_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_0v9_s0: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcc_0v9_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_1v8_s0: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_mipi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5_s0: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0_s0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sdio_s0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_cam"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_host0_s0: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + lcd_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "lcd_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcc_1v8_s0>; + bt656-supply = <&vcc_3v0_s0>; + gpio1830-supply = <&vcc_3v0_s0>; + sdmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led1: user-led1 { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2: user-led2 { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>, + <4 9 1 &pcfg_pull_up_8ma>, + <4 10 1 &pcfg_pull_up_8ma>, + <4 11 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>; + }; + }; + + usb-typec { + vcc5v0_typec0_en: vcc5v0-typec-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0_s0>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s3>; +}; + +&sdhci { + max-frequency = <150000000>; + bus-width = <8>; + mmc-hs400-1_8v; + non-removable; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <800>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-t-opp.dtsi b/arch/arm/dts/rk3399-t-opp.dtsi new file mode 100644 index 0000000000..1ababadda9 --- /dev/null +++ b/arch/arm/dts/rk3399-t-opp.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Radxa Limited + */ + +/ { + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <875000 875000 1250000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <875000 875000 1250000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1250000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <975000 975000 1250000>; + }; + }; + + cluster1_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <875000 875000 1250000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <875000 875000 1250000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <875000 875000 1250000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000 925000 1250000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000 1000000 1250000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1075000 1075000 1250000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000 1150000 1250000>; + }; + }; + + gpu_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <875000 875000 1150000>; + }; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <875000 875000 1150000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000 875000 1150000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000 975000 1150000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig new file mode 100644 index 0000000000..5ed46d589a --- /dev/null +++ b/configs/rock-4c-plus-rk3399_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus" +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.35.1

2 3

[PATCH] renesas: rcar: Apply ATF overlay for reserved-memory
by Detlev Casanova 23 Mar '23

23 Mar '23

The function fdtdec_board_setup() is only called by fdtdec_setup() which needs to be called by the board file. This is not the case for the renesas boards so rename the fdtdec_board_setup() function to a local name and call it directly from ft_board_setup(), before cleaning up the memory nodes. Signed-off-by: Detlev Casanova <detlev.casanova(a)collabora.com> --- board/renesas/rcar-common/common.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index daa1beb14f..6eaa0d1a65 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -25,14 +25,12 @@ extern u64 rcar_atf_boot_args[]; #define FDT_RPC_PATH "/soc/spi@ee200000" -int fdtdec_board_setup(const void *fdt_blob) +void apply_atf_overlay(void *fdt_blob) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) - fdt_overlay_apply_node((void *)fdt_blob, 0, atf_fdt_blob, 0); - - return 0; + fdt_overlay_apply_node(fdt_blob, 0, atf_fdt_blob, 0); } int dram_init(void) @@ -159,6 +157,7 @@ static void update_rpc_status(void *blob) int ft_board_setup(void *blob, struct bd_info *bd) { + apply_atf_overlay(blob); scrub_duplicate_memory(blob); update_rpc_status(blob); -- 2.38.1

2 3

[PATCH] pci: Handle failed calloc in decode_regions()
by Pierre-Clément Tosi 22 Mar '23

22 Mar '23

Add a check for calloc() failing to allocate the requested memory. Make decode_regions() return an error code. Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefan Roese <sr(a)denx.de> Signed-off-by: Pierre-Clément Tosi <ptosi(a)google.com> --- drivers/pci/pci-uclass.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 970ee1adf1..2c85e78a13 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -954,7 +954,7 @@ int pci_bind_bus_devices(struct udevice *bus) return 0; } -static void decode_regions(struct pci_controller *hose, ofnode parent_node, +static int decode_regions(struct pci_controller *hose, ofnode parent_node, ofnode node) { int pci_addr_cells, addr_cells, size_cells; @@ -968,7 +968,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, prop = ofnode_get_property(node, "ranges", &len); if (!prop) { debug("%s: Cannot decode regions\n", __func__); - return; + return -EINVAL; } pci_addr_cells = ofnode_read_simple_addr_cells(node); @@ -986,6 +986,8 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS; hose->regions = (struct pci_region *) calloc(1, max_regions * sizeof(struct pci_region)); + if (!hose->regions) + return -ENOMEM; for (i = 0; i < max_regions; i++, len -= cells_per_record) { u64 pci_addr, addr, size; @@ -1053,7 +1055,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, /* Add a region for our local memory */ bd = gd->bd; if (!bd) - return; + return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { if (bd->bi_dram[i].size) { @@ -1068,7 +1070,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, } } - return; + return 0; } static int pci_uclass_pre_probe(struct udevice *bus) @@ -1097,7 +1099,10 @@ static int pci_uclass_pre_probe(struct udevice *bus) /* For bridges, use the top-level PCI controller */ if (!device_is_on_pci_bus(bus)) { hose->ctlr = bus; - decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus)); + ret = decode_regions(hose, dev_ofnode(bus->parent), + dev_ofnode(bus)); + if (ret) + return ret; } else { struct pci_controller *parent_hose; -- 2.36.1.124.g0e6072fb45-goog

5 7

kwboot: Marvell Dove UART booting
by Tony Dinh 20 Mar '23

20 Mar '23

Hi all, With great help from Pali, I've made some good progress on kwboot the HP Thin Client T5335z (Marvell Dove SoC) board. I had been unsuccessful running kwboot with this box until Pali pointed out a few important aspects of the Dove SoC, and how the BootROM commands work (my apology for forgetting to include the u-boot-mailing list and Marek on previous email exchanges). Here is the summary of the attempt to kwboot. HP Thin Client T5335z Marvell Dove SoC 88AP510 (A1) 1Ghz CPU 1 GB RAM - Reset Strapping: As with all Dove SoCs, there is no preamble when we send the u-boot image over the serial line. IOW, no magic handshake string to tell the BootROM that we are booting over UART. Instead, the hardware must explicitly set to UART mode booting. For boards like the Solidrun Cubox, there is a button, and some other board, a DIP switch, to enable this mode. For the T55335z, there is no button or DIP switch on the board for that purpose. Instead, there is a jumper (the exact purpose is unknown), but I found that this jumper will put the BootROM into debug mode. And from the BootROM debug prompt, we can execute a command to set the boot mode to UART with "x command. Here is the log and my commentary starting with *** <Begin log> *** With jumper inserted, serial console connected, start serial console # picocom --b 115200 --f n --p n --d 8 /dev/ttyUSB0 Terminal ready *** Hit <Enter> here to get to the prompt and execute "x 0x0E" Bootstrap 2.33> Bootstrap 2.33>x 0x0E *** No more input possible here, so Control-A-X to exit serial console Terminating... Thanks for using picocom *** Run kwboot # kwboot -t -p -B 115200 /dev/ttyUSB0 -D /localdisk/mtd0.t5335z Patching image boot signature to UART Aligning image header to Xmodem block size Waiting 2s and flushing tty Sending boot image header (512 bytes)... 25 % [.... ] Done Sending boot image data (607664 bytes)... 0 % [......................................................................] 1 % [......................................................................] 2 % [......................................................................] <snip> 95 % [......................................................................] 97 % [......................................................................] 98 % [.......................................................... ] Done Finishing transfer [Type Ctrl-\ + c to quit] *** Hung here! BootROM did not execute the image payload. *** *** The file mtd0.t5335z is a dd dump from the SPI flash mtd0 with *** this command: *** # dd if=/dev/mtd0 of=mtd0.t5335z bs=768k conv=sync <End log> - Pali's observation: It looks like Dove uses kwbimage v0 format with extensions, at least according to Function Spec. See 'Binary Code Extension' and 'Header Extension'. Currently kwboot and kwbimage supports v0 image only with one extension. - My comments in response: Indeed. I've seen that in the Functional Spec, too. The mdt0 binwalk also shows what looks like the extension header. DECIMAL HEXADECIMAL DESCRIPTION -------------------------------------------------------------------------------- 118161 0x1CD91 Certificate in DER format (x509 v3), header length: 4, sequence length: 3 199169 0x30A01 Certificate in DER format (x509 v3), header length: 4, sequence length: 5464 380652 0x5CEEC CRC32 polynomial table, little endian 387072 0x5E800 CRC32 polynomial table, little endian 608166 0x947A6 LZMA compressed data, properties: 0x66, dictionary size: 0 bytes, uncompressed size: 147351982848 bytes Thanks, Tony

3 29

[PATCH] dfu: mtd: mark bad the MTD block on erase error
by Patrick Delaunay 17 Mar '23

17 Mar '23

In the MTD DFU backend, it is needed to mark the NAND block bad when the erase failed with the -EIO error, as it is done in UBI and JFFS2 code. This operation is not done in the MTD framework, but the bad block tag (in BBM or in BBT) is required to avoid to write data on this block in the next DFU_OP_WRITE loop in mtd_block_op(): the code skip the bad blocks, tested by mtd_block_isbad(). Without this patch, when the NAND block become bad on DFU write operation - low probability on new NAND - the DFU write operation will always failed because the failing block is never marked bad. This patch also adds a test to avoid to request an erase operation on a block already marked bad; this test is not performed in MTD framework in mtd_erase(). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/dfu/dfu_mtd.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index c7075f12eca9..4fb02c4c806c 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -91,22 +91,32 @@ static int mtd_block_op(enum dfu_op op, struct dfu_entity *dfu, return -EIO; } + /* Skip the block if it is bad, don't erase it again */ + if (mtd_block_isbad(mtd, off)) { + erase_op.addr += mtd->erasesize; + continue; + } + ret = mtd_erase(mtd, &erase_op); if (ret) { - /* Abort if its not a bad block error */ - if (ret != -EIO) { - printf("Failure while erasing at offset 0x%llx\n", - erase_op.fail_addr); - return 0; + /* If this is not -EIO, we have no idea what to do. */ + if (ret == -EIO) { + printf("Marking bad block at 0x%08llx (%d)\n", + erase_op.fail_addr, ret); + ret = mtd_block_markbad(mtd, erase_op.addr); + } + /* Abort if it is not -EIO or can't mark bad */ + if (ret) { + printf("Failure while erasing at offset 0x%llx (%d)\n", + erase_op.fail_addr, ret); + return ret; } - printf("Skipping bad block at 0x%08llx\n", - erase_op.addr); } else { remaining -= mtd->erasesize; } - /* Continue erase behind bad block */ + /* Continue erase behind the current block */ erase_op.addr += mtd->erasesize; } } -- 2.25.1

3 2

[PATCH] board_r: Relocate OF_EMBED if NEEDS_MANUAL_RELOC only
by Pierre-Clément Tosi 16 Mar '23

16 Mar '23

When the embedded device tree is pointed to by the __dtb_dt_*begin symbols, it seems to be covered by the early relocation code and doesn't need to be manually patched. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Pierre-Clément Tosi <ptosi(a)google.com> --- common/board_r.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c index 56eb60fa27..00926dcb1e 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -150,13 +150,13 @@ static int initr_reloc_global_data(void) */ gd->env_addr += gd->reloc_off; #endif -#ifdef CONFIG_OF_EMBED /* * The fdt_blob needs to be moved to new relocation address * incase of FDT blob is embedded with in image */ - gd->fdt_blob += gd->reloc_off; -#endif + if (CONFIG_IS_ENABLED(OF_EMBED) && CONFIG_IS_ENABLED(NEEDS_MANUAL_RELOC)) + gd->fdt_blob += gd->reloc_off; + #ifdef CONFIG_EFI_LOADER /* * On the ARM architecture gd is mapped to a fixed register (r9 or x18). -- 2.37.2.789.g6183377224-goog

4 5

[PATCH] doc: Add documentation for CZ.NIC Turris routers
by Pali Rohár 04 Mar '23

04 Mar '23

This patch adds a new documentation for all released CZ.NIC Turris routers. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- doc/board/CZ.NIC/index.rst | 9 + doc/board/CZ.NIC/turris.rst | 323 ++++++++++++++++++++++++++++++++++++ doc/board/index.rst | 1 + 3 files changed, 333 insertions(+) create mode 100644 doc/board/CZ.NIC/index.rst create mode 100644 doc/board/CZ.NIC/turris.rst diff --git a/doc/board/CZ.NIC/index.rst b/doc/board/CZ.NIC/index.rst new file mode 100644 index 000000000000..19ec6af2f389 --- /dev/null +++ b/doc/board/CZ.NIC/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +CZ.NIC +====== + +.. toctree:: + :maxdepth: 2 + + turris diff --git a/doc/board/CZ.NIC/turris.rst b/doc/board/CZ.NIC/turris.rst new file mode 100644 index 000000000000..b82dea4e0786 --- /dev/null +++ b/doc/board/CZ.NIC/turris.rst @@ -0,0 +1,323 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +CZ.NIC Turris routers +===================== + +CZ.NIC develops open source Turris routers: Turris 1.0, Turris 1.1, Turris Omnia, and Turris Mox. This document describes a U-Boot deployment (compilation, flashing, resetting) on these routers. + +Turris 1.x +---------- + +Turris 1.0 and Turris 1.1 boards contain Freescale P2020 CPUs with two PowerPC e500v2 cores which BootROM (or CPU directly) can load and boot U-Boot bootloader from various locations. For Turris 1.x boards, only Flash NOR and SD cards are supported. P2020 CPU cannot download bootloader via UART like other platforms. For loading the U-Boot bootloader from Flash NOR (which is the default) it is needed to put SW1 dip switches on the board to position 11001010, and for the SD card to position 01101010 respectively. Note that this controls the source from which P2020 loads U-Boot, not from which U-Boot loads boot script or kernel. Boot procedures from SD card and Flash NOR are different, hence U-Boot binaries need to be compiled differently. + +More information about Turris 1.x, including the complete HW documentation (together with the SW1 dip switch options) and Altium design files, can be found on: https://docs.turris.cz/hw/turris-1x/turris-1x/ + +Compilation +^^^^^^^^^^^ + +To compile the Flash NOR version, run:: + + $ make CROSS_COMPILE=powerpc-linux-gnuspe- turris_1x_nor_defconfig + $ make CROSS_COMPILE=powerpc-linux-gnuspe- u-boot-with-dtb.bin + +It will produce a flashable binary file ``u-boot-with-dtb.bin``. + +To compile the SD card version, run:: + + $ make CROSS_COMPILE=powerpc-linux-gnuspe- turris_1x_sdcard_defconfig + $ make CROSS_COMPILE=powerpc-linux-gnuspe- u-boot-with-spl.bin + +It will produce a bootable binary file ``u-boot-with-spl.bin``. + +Flashing +^^^^^^^^ + +To flash the new U-Boot version into Flash NOR, load binary ``u-boot-with-dtb.bin`` (which must have exact size 0xc0000 bytes) to the ``$loadaddr`` address and run U-Boot commands:: + + => protect off 0xeff40000 +0xc0000 + => erase 0xeff40000 +0xc0000 + => cp.b $loadaddr 0xeff40000 0xc0000 + => protect on 0xeff40000 +0xc0000 + +To load the new U-Boot version to the SD card, just copy the ``u-boot-with-spl.bin`` binary image to sector 0 on the SD card. To preserve existing MBR partitions on the SD card, do not overwrite bytes 440-511 on sector 0. Do it for example via the ``dd`` command on Linux:: + + $ dd if=u-boot-with-spl.bin of=/dev/mmcblk0 bs=440 count=1 + $ dd if=u-boot-with-spl.bin of=/dev/mmcblk0 bs=512 skip=1 + +Boot source +^^^^^^^^^^^ + +By default P2020 CPU boots the U-Boot bootloader from the location configured by SW1 dip switches on Turris 1.x boards. But this configuration can be temporarily overridden by GPIOs (software configured) until the power supply is disconnected or the HW reset button is pressed. U-Boot environment provides commands ``run reboot_to_nor``, ``run reboot_to_sd`` and ``run reboot_to_def`` to force boot source location to Flash NOR, SD card, or default value (configured by SW1 dip switches) and initiate reboot (CPU reset). Overridden configuration is not lost after CPU reset. + +This can be useful to temporarily boot U-Boot from a different location (e.g. after flashing the new version) without the need to open the device and change the configuration of SW1 dip switches. + +Reset button +^^^^^^^^^^^^ + +When the HW reset button is pushed, then CPLD puts the main P2020 CPU into a reset state and the power led starts to blink in a one-second period. After 6 seconds, the power led stays powered on. After the HW reset button is released, CPLD releases the main P2020 CPU from the reset state and U-Boot starts booting on the main P2020 CPU. During startup, U-Boot sets the environment ``$turris_reset`` variable to the duration of the reset button being held in seconds, meaning the count of how many times the power led has blinked. The maximal value is therefore 6 seconds. + +If the HW reset button was held for 6 or more seconds then U-Boot sets ``$boot_targets`` to ``rescue`` which automatically starts booting the rescue system from Flash NOR, as defined in the ``$bootcmd_rescue`` variable. Note that U-Boot resets default values of these variables to ensure that booting into rescue mode would work correctly also when the custom U-Boot environment stored in permanent Flash NOR storage is damaged or overwritten. + +Environment variable ``$turris_reset`` can be used by boot scripts during the boot process for various purposes, like different boot modes. + +Turris Omnia +------------ + +Turris Omnia boards contain Marvell Armada 385 CPU with two ARM Cortex-A9 cores on which BootROM can load U-Boot bootloader from various locations. For Turris Omnia, only SPI NOR and UART are supported. The binary image is the same for both, SPI NOR and UART. For UART downloading and booting, a ``kwboot`` application is used (part of U-Boot). + +More information about Turris Omnia can be found on: https://docs.turris.cz/hw/omnia/omnia/ + +Compilation +^^^^^^^^^^^ + +To compile U-Boot for Turris Omnia, run:: + + $ make CROSS_COMPILE=arm-linux-gnueabi- turris_omnia_defconfig + $ make CROSS_COMPILE=arm-linux-gnueabi- u-boot-spl.kwb + +Flashing +^^^^^^^^ + +To flash the new U-Boot version into SPI NOR, load binary ``u-boot-spl.kwb`` to the ``$loadaddr`` address of size ``$filesize`` and run U-Boot commands:: + + => sf probe + => sf update $loadaddr 0x0 $filesize + +UART booting +^^^^^^^^^^^^ + +Run the ``kwboot`` command with the correct tty device:: + + $ ./tools/kwboot -b ./u-boot-spl.kwb -t /dev/ttyUSB0 + +After that, press the HW reset button on Omnia. ``kwboot`` should instruct Armada 385 CPU BootROM to enter into UART download mode, and transfer ``u-boot-spl.kwb`` binary over UART and boot it. + +Armada 385 UART supports speeds up to 5200000 bauds. With appropriate USB-UART converters which support higher speeds, it is possible to speed up transfer via the ``-B`` option. For example ``-B 5200000``. + +Reset button +^^^^^^^^^^^^ + +Like Turris 1.x boards, Turris Omnia has also a dedicated HW reset button. U-Boot during startup sets environment variable ``$omnia_reset`` to the reset mode selected by holding the reset button. + +If the HW reset button was held for about a second or more then U-Boot starts booting the rescue system from SPI NOR. Value from the ``$omnia_reset`` variable is put into the kernel command line, so the rescue system can choose different actions based on reset mode. + +mSATA slot configuration +^^^^^^^^^^^^^^^^^^^^^^^^ + +mSATA slot on Turris Omnia supports both SATA and PCIe modes. By default, it is in auto mode, which means that mode is detected based on the connected mSATA/mPCIe card's pin 43. mPCIe cards must have pin 43 connected to the ground and mSATA cards have this pin disconnected. There are some broken mPCIe cards that do not have grounded this pin and therefore autodetection does not work: the slot is switched to SATA mode and the mPCIe card does not work. + +To workaround this issue with buggy mPCIe cards in the mSATA slot, U-Boot provides a way to turn off autodetection and forces mode to PCIe (or also to SATA). U-Boot SPL during its init phase reads environment variable ``$omnia_msata_slot`` and when it is set to ``sata`` or ``pcie`` then it forces the specified slot mode. In all other cases, it configures mode based on the card's pin 43. + +To force mSATA slot mode to PCIe run commands:: + + => setenv omnia_msata_slot pcie + => saveenv + => reset + +To revert mSATA slot mode back to autodetect mode:: + + => setenv omnia_msata_slot + => saveenv + => reset + +WWAN slot configuration +^^^^^^^^^^^^^^^^^^^^^^^ + +WWAN mPCIe slot (that one with SIM slot) on Turris Omnia is compliant with PCIe Mini CEM 2.1 specification and supports both PCIe and USB 3.0 modes together with USB 2.0 mode. + +As defined in PCIe CEM 2.1 specification, PCIe and USB 3.0 functions share the same mPCIe slot pins (23, 25, 31, 33), and therefore only one of these two functions can be activated and configured at the same time. USB 2.0 function is on dedicated mPCIe slot pins. By default, the WWAN slot is in PCIe + USB 2.0 mode. U-Boot SPL during its init phase reads environment variable ``$omnia_wwan_slot`` and when it is set to ``usb3`` it changes the slot mode (slot pins 23, 25, 31, 33) to USB 3.0. + +To set WWAN slot mode to USB 3.0 run commands:: + + => setenv omnia_wwan_slot usb3 + => saveenv + => reset + +To revert WWAN slot back to PCIe + USB 2.0 mode:: + + => setenv omnia_wwan_slot + => saveenv + => reset + +Turris Mox +---------- + +Turris Mox is a modular router system. Its main Mox-A module contains Marvell Armada 3720 CPU with two 64-bit ARM Cortex-A53 cores and one 32-bit ARM Cortex-M3 on which BootROM can load U-Boot bootloader from various locations. Turris Mox supports only SPI NOR and UART. For UART downloading and booting a ``mox-imager`` application is used. The firmware itself consists of two parts: Secure firmware which runs on 32-bit ARM Cortex-M3 core and A53 firmware which is runs on 64-bit ARM Cortex-A53 cores. + +Application ``mox-imager`` is available at: https://gitlab.nic.cz/turris/mox-imager + +More information about Turris Mox can be found on: https://docs.turris.cz/hw/mox/intro/ + +Compilation +^^^^^^^^^^^ + +To compile U-Boot for Turris Mox, run on a Linux computer:: + + $ make CROSS_COMPILE=aarch64-linux-gnu- turris_mox_defconfig + $ make CROSS_COMPILE=aarch64-linux-gnu- u-boot.bin + +Note that standalone U-Boot cannot be flashed directly into SPI NOR. It can be replaced only as part of the whole A53 firmware which contains a concatenation of a Trusted-Firmware-A BL1 binary and a Trusted-Firmware-A FIT binary. Trusted-Firmware-A FIT binary contains Trusted-Firmware-A BL2 and BL3.1 binaries and also the U-Boot binary. + +To compile the final A53 firmware binary, compile the Trusted-Firmware-A project, specifying the path to the u-boot.bin binary in the ``BL33=`` option by commands:: + + $ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=a3700 CM3_SYSTEM_RESET=1 USE_COHERENT_MEM=0 FIP_ALIGN=0x100 BL33=u-boot.bin mrvl_bootimage + $ cp -a build/a3700/release/boot-image.bin a53-firmware.bin + $ od -v -tu8 -An -j 131184 -N 8 a53-firmware.bin | LC_ALL=C awk '{ for (i = 0; i < 64; i += 8) printf "%c", and(rshift(1441792-131072-$$1, i), 255) }' | dd of=a53-firmware.bin bs=1 seek=131192 count=8 conv=notrunc 2>/dev/null + +It will produce a ``a53-firmware.bin`` binary. + +Trusted-Firmware-A project is available at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ + +Flashing +^^^^^^^^ + +To flash new A53 firmware binary (which contains also U-Boot) into SPI NOR, load binary ``a53-firmware.bin`` to the ``$loadaddr`` address of size ``$filesize`` and run U-Boot commands:: + + => sf probe + => sf update $loadaddr 0x20000 $filesize + +Secure firmware +^^^^^^^^^^^^^^^ + +Secure firmware is running on Armada 3720 ARM CM3 core, separated from main ARM A53 cores (on which U-Boot and Linux kernel are running). + +Due to security reasons, it is not possible to flash one's own version of Secure firmware because it is signed and Armada 3720 CPU checks that signature is done by CZ.NIC signing key. Armada 3720 CPU refuses to boot binary which is not signed by CZ.NIC private key. +Released signed binaries of Secure firmware can be downloaded from CZ.NIC releases webpage: https://gitlab.nic.cz/turris/mox-boot-builder/-/releases +Secure firmware is open source and all sources can be downloaded from CZ.NIC repository webpage: https://gitlab.nic.cz/turris/mox-boot-builder/-/tree/master/wtmi + +To flash a new Secure firmware binary (which is signed by the CZ.NIC key) into SPI NOR, load the ``secure-firmware.bin`` binary to the ``$loadaddr`` address of the ``$filesize`` size and run U-Boot commands:: + + => sf probe + => sf update $loadaddr 0x0 $filesize + +UART booting +^^^^^^^^^^^^ + +Run command ``mox-imager`` with correct tty device:: + + $ mox-imager -D /dev/ttyUSB0 -E -t secure-firmware-uart.bin a53-firmware.bin + +And plug the power supply. If it fails, unplug the power supply and plug it in again. + +Armada 3720 UART supports speeds up to 6000000 bauds. With appropriate USB-UART converters which support higher speeds, it is possible to speed up transfer via the ``-b`` option. For example ``-b 6000000``. + +Rescue mode +----------- + +On All Turris boards, it is possible to boot the rescue system from U-Boot just by calling ``run bootcmd_rescue``. It is the same as pressing the HW reset button for a longer time. + +OTP (One Time Programming) +-------------------------- + +Every Turris board contains some OTP storage that is burned during factory programming and which cannot be later modified or erased. It contains information for device identification: the serial number, mac addresses, etc. + +Every Turris 1.0, 1.1, and Omnia board has allocated 3 MAC addresses from CZ.NIC OUI (D8:58:D7) and every Turris Mox board have allocated 2 MAC addresses from CZ.NIC OUI (D8:58:D7). But only the first address is stored in OTP, other MAC addresses can be calculated by numeric `plus one` and `plus two` operations. + +Atsha 204/204a OTP content +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +All Turris 1.0, Turris 1.1 and Turris Omnia boards store into Atsha 204/204a cryptochip OTP area at 32-bit words 0x00-0x03 following data:: + + word 0x00 - first half of 64-bit device serial number + [07:00] - first byte of hw-rev/version (MSB) + [15:08] - second byte of hw-rev/version + [23:16] - third byte of hw-rev/version + [31:24] - fourth byte of hw-rev/version (LSB) + + word 0x01 - second half of 64-bit device serial number + [07:00] - first byte of serial (MSB) + [15:08] - second byte of serial + [23:16] - third byte of serial + [31:24] - fourth byte of serial (LSB) + + word 0x02 - first half of 48-bit first MAC address with CZ.NIC OUI (D8:58:D7) + [07:00] - reserved (zero) + [15:08] - first byte - 0xD8 + [23:16] - second byte - 0x58 + [31:24] - third byte - 0xD7 + + word 0x03 - second half of 48-bit first MAC address + [07:00] - reserved (zero) + [15:08] - fourth byte + [23:16] - fifth byte + [31:24] - sixth byte + +Words 0x00 and 0x01 contain 64-bit device serial numbers in a big-endian format, and words 0x02 and 0x03 contain 48-bit first MAC addresses with CZ.NIC OUI (D8:58:D7) in a big-endian format. + +Armada 385 LD1 eFuse content +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Turris Omnia boards of revision 32 or higher store into 256-bit long Armada 385 LD1 eFuse OTP following data:: + + [047:000] - 48-bit first MAC address with CZ.NIC OUI (D8:58:D7) in big endian + [007:000] - first byte - 0xD8 + [015:008] - second byte - 0x58 + [023:016] - third byte - 0xD7 + [031:024] - fourth byte + [039:032] - fifth byte + [047:040] - sixth byte + [055:048] - board version + [063:056] - reserved (zeros) + [127:064] - 64-bit device serial number in big endian + [071:064] - first byte of hw-rev/version (MSB) + [079:072] - second byte of hw-rev/version + [087:080] - third byte of hw-rev/version + [095:088] - fourth byte of hw-rev/version (LSB) + [103:096] - first byte of serial (MSB) + [111:104] - second byte of serial + [119:112] - third byte of serial + [127:120] - fourth byte of serial (LSB) + [255:128] - reserved (zeros) + [256] - lock bit (1 - if above data are valid) + +Armada 385 LD1 eFuse is mapped to U-Boot fuse bank number 65. + +Read serial number:: + + => fuse read 65 2 1 + +Armada 3720 Secure OTP content +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +All Turris Mox boards store into Armada 3720 Secure OTP 64-bit rows 42 and 43 following data:: + + row 42 + [47:00] - 48-bit first MAC address with CZ.NIC OUI (D8:58:D7) in little endian + [07:00] - sixth byte + [15:08] - fifth byte + [23:16] - fourth byte + [31:24] - third byte - 0xD7 + [39:32] - second byte - 0x58 + [47:40] - first byte - 0xD8 + [53:48] - board version + [55:54] - board type + 0b00 - CZ.NIC Turris Mox + 0b01 - reserved (unassigned) + 0b10 - RIPE Atlas Probe + 0b11 - reserved (unassigned) + [57:56] - RAM size + 0b00 - 512M + 0b01 - 1024M + 0b10 - 2048M + 0b11 - 4096M + [63:58] - reserved (zeros) + [64] - lock bit (1 - if above data are valid) + + row 43 + [63:00] - 64-bit device serial number in big endian with swapped 32-bit words + [07:00] - first byte of serial (MSB) + [15:08] - second byte of serial + [23:16] - third byte of serial + [31:24] - fourth byte of serial (LSB) + [39:32] - first byte of hw-rev/version (MSB) + [47:40] - second byte of hw-rev/version + [55:48] - third byte of hw-rev/version + [63:56] - fourth byte of hw-rev/version (LSB) + [64] - lock bit (1 - if above data are valid) + +Armada 3720 Secure OTP rows are mapped 1:1 to U-Boot fuse bank numbers. + +Read serial number:: + + => fuse read 43 1 + => fuse read 43 0 diff --git a/doc/board/index.rst b/doc/board/index.rst index 53edd5301f25..90467a6bd944 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -18,6 +18,7 @@ Board-specific doc bsh/index congatec/index coreboot/index + CZ.NIC/index emulation/index google/index highbank/index -- 2.20.1

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[PATCH 00/17] patman: Convert camel case
by Simon Glass 01 Mar '23

01 Mar '23

Much of the Python code in U-Boot was written using the Chromium OS Python style. This series converts the patman class methods and functions from camel case to snake case. This fits with PEP8 and is one step along the way to making the code more compliant with that. Simon Glass (17): patman: Convert camel case in tools.py patman: Convert camel case in command.py patman: Convert camel case in checkpatch.py patman: Convert camel case in commit.py patman: Convert camel case in cros_subprocess.py patman: Convert camel case in func_test.py patman: Convert camel case in get_maintainer.py patman: Convert camel case in gitutil.py patman: Convert camel case in project.py patman: Convert camel case in test_checkpatch.py patman: Convert camel case in test_util.py patman: Convert camel case in tout.py patman: Rename Print() to Tprint() patman: Rename Color() method to build() patman: Convert camel case in terminal.py patman: Update with new pylint scores RFC: tools: Add a camel-case conversion script scripts/pylint.base | 26 +- scripts/style.py | 180 +++++++++++ tools/binman/bintool.py | 30 +- tools/binman/bintool_test.py | 34 +- tools/binman/btool/lz4.py | 8 +- tools/binman/btool/lzma_alone.py | 16 +- tools/binman/cbfs_util.py | 12 +- tools/binman/cbfs_util_test.py | 20 +- tools/binman/control.py | 74 ++--- tools/binman/elf.py | 20 +- tools/binman/elf_test.py | 20 +- tools/binman/entry.py | 42 +-- tools/binman/entry_test.py | 4 +- tools/binman/etype/atf_fip.py | 2 +- tools/binman/etype/blob.py | 4 +- tools/binman/etype/blob_ext_list.py | 2 +- tools/binman/etype/fdtmap.py | 2 +- tools/binman/etype/files.py | 2 +- tools/binman/etype/fill.py | 2 +- tools/binman/etype/fit.py | 20 +- tools/binman/etype/fmap.py | 6 +- tools/binman/etype/gbb.py | 10 +- tools/binman/etype/intel_ifwi.py | 12 +- tools/binman/etype/mkimage.py | 8 +- tools/binman/etype/section.py | 26 +- tools/binman/etype/text.py | 4 +- tools/binman/etype/u_boot_elf.py | 6 +- tools/binman/etype/u_boot_env.py | 4 +- tools/binman/etype/u_boot_spl_bss_pad.py | 4 +- tools/binman/etype/u_boot_spl_expanded.py | 2 +- tools/binman/etype/u_boot_tpl_bss_pad.py | 4 +- tools/binman/etype/u_boot_tpl_expanded.py | 2 +- tools/binman/etype/u_boot_ucode.py | 4 +- tools/binman/etype/u_boot_with_ucode_ptr.py | 2 +- tools/binman/etype/vblock.py | 10 +- tools/binman/fdt_test.py | 4 +- tools/binman/fip_util.py | 16 +- tools/binman/fip_util_test.py | 36 +-- tools/binman/fmap_util.py | 2 +- tools/binman/ftest.py | 324 ++++++++++---------- tools/binman/image.py | 16 +- tools/binman/main.py | 6 +- tools/binman/state.py | 34 +- tools/buildman/builder.py | 108 +++---- tools/buildman/builderthread.py | 12 +- tools/buildman/control.py | 46 +-- tools/buildman/func_test.py | 20 +- tools/buildman/test.py | 30 +- tools/buildman/toolchain.py | 26 +- tools/dtoc/fdt.py | 4 +- tools/dtoc/fdt_util.py | 12 +- tools/dtoc/main.py | 6 +- tools/dtoc/test_dtoc.py | 76 ++--- tools/dtoc/test_fdt.py | 34 +- tools/dtoc/test_src_scan.py | 12 +- tools/patman/checkpatch.py | 36 +-- tools/patman/command.py | 30 +- tools/patman/commit.py | 10 +- tools/patman/control.py | 20 +- tools/patman/cros_subprocess.py | 59 ++-- tools/patman/func_test.py | 74 ++--- tools/patman/get_maintainer.py | 8 +- tools/patman/gitutil.py | 176 +++++------ tools/patman/main.py | 8 +- tools/patman/patchstream.py | 12 +- tools/patman/project.py | 4 +- tools/patman/series.py | 32 +- tools/patman/settings.py | 4 +- tools/patman/status.py | 22 +- tools/patman/terminal.py | 56 ++-- tools/patman/test_checkpatch.py | 80 ++--- tools/patman/test_util.py | 8 +- tools/patman/tools.py | 86 +++--- tools/patman/tout.py | 58 ++-- tools/rmboard.py | 16 +- 75 files changed, 1214 insertions(+), 1033 deletions(-) create mode 100755 scripts/style.py -- 2.35.0.rc2.247.g8bbb082509-goog

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