November 2022 - U-Boot

[PATCH] rtc: add ht1380 driver
by Sergei Antonov 21 Nov '22

21 Nov '22

Support Holtek HT1380/HT1381 Serial Timekeeper Chip. Datasheet: https://www.holtek.com.tw/documents/10179/11842/ht1380_1v130.pdf Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- drivers/rtc/Kconfig | 7 + drivers/rtc/Makefile | 1 + drivers/rtc/ht1380.c | 303 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+) create mode 100644 drivers/rtc/ht1380.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 23963271928a..f62ee43b0f89 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -220,4 +220,11 @@ config RTC_ZYNQMP Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. +config RTC_HT1380 + bool "Enable Holtek HT1380/HT1381 RTC driver" + depends on DM_RTC && DM_GPIO + help + Say "yes" here to get support for Holtek HT1380/HT1381 + Serial Timekeeper Chip. + endmenu diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index d621be622848..d04ac8fb0938 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +obj-$(CONFIG_RTC_HT1380) += ht1380.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c new file mode 100644 index 000000000000..af28b5f25fcd --- /dev/null +++ b/drivers/rtc/ht1380.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Holtek HT1380/HT1381 Serial Timekeeper Chip + */ + +#include <common.h> +#include <dm.h> +#include <rtc.h> +#include <bcd.h> +#include <asm/gpio.h> +#include <linux/delay.h> + +struct ht1380_priv { + struct gpio_desc rst_desc; + struct gpio_desc clk_desc; + struct gpio_desc dat_desc; +}; + +enum registers { + SEC, + MIN, + HOUR, + MDAY, + MONTH, + WDAY, + YEAR, + WP, + N_REGS +}; + +static const int BURST = 0xBE; +static const int READ = 1; + +static void ht1380_half_period_delay(void) +{ + /* Delay for half a period. 1 us complies with the 500 KHz maximum + input serial clock limit given by the datasheet. */ + udelay(1); +} + +static int ht1380_send_byte(struct ht1380_priv *priv, int byte) +{ + int ret; + + for (int bit = 0; bit < 8; bit++) { + ret = dm_gpio_set_value(&priv->dat_desc, byte >> bit & 1); + if (ret) + break; + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 1); + if (ret) + break; + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + break; + } + + return ret; +} + +static int ht1380_reset_off(struct ht1380_priv *priv) +{ + const unsigned int T_CC = 4; /* us, Reset to Clock Setup */ + int ret; + + /* Go out of RESET state. + Make sure we make the minimal delay required by the datasheet. */ + ret = dm_gpio_set_value(&priv->rst_desc, 1); + udelay(T_CC); + return ret; +} + +static int ht1380_reset_on(struct ht1380_priv *priv) +{ + const unsigned int T_CWH = 4; /* us, Reset Inactive Time */ + int ret; + + /* Enter RESET state. + Make sure we make the minimal delay required by the datasheet. */ + ret = dm_gpio_set_value(&priv->rst_desc, 0); + udelay(T_CWH); + return ret; +} + +static int ht1380_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + int ret, i, bit, reg[N_REGS]; + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + return ret; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = ht1380_reset_off(priv); + if (ret) + goto exit; + + ret = ht1380_send_byte(priv, BURST + READ); + if (ret) + goto exit; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_IN); + if (ret) + goto exit; + + for (i = 0; i < N_REGS; i++) { + reg[i] = 0; + + for (bit = 0; bit < 8; bit++) { + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 1); + if (ret) + goto exit; + ht1380_half_period_delay(); + + reg[i] |= dm_gpio_get_value(&priv->dat_desc) << bit; + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + goto exit; + } + } + + ret = -EINVAL; + + /* Correctness check: some bits are always zero */ + if ((reg[MIN] & 0x80) || (reg[HOUR] & 0x40) || (reg[MDAY] & 0xC0) || + (reg[MONTH] & 0xE0) || (reg[WDAY] & 0xF8) || (reg[WP] & 0x7F)) + goto exit; + + /* Correctness check: some registers are always > 0 */ + if (!reg[MDAY] || !reg[MONTH] || !reg[WDAY]) + goto exit; + + tm->tm_sec = bcd2bin(reg[SEC]); + tm->tm_min = bcd2bin(reg[MIN]); + if (reg[HOUR] & 0x80) { + /* AM-PM Mode, range is 01-12 */ + tm->tm_hour = bcd2bin(reg[HOUR] & 0x1F) % 12; + if (reg[HOUR] & 0x20) { + /* it is PM (otherwise AM) */ + tm->tm_hour += 12; + } + } else { + /* 24-hour Mode, range is 0-23 */ + tm->tm_hour = bcd2bin(reg[HOUR]); + } + tm->tm_mday = bcd2bin(reg[MDAY]); + tm->tm_mon = bcd2bin(reg[MONTH]); + tm->tm_year = 2000 + bcd2bin(reg[YEAR]); + tm->tm_wday = bcd2bin(reg[WDAY]) - 1; + tm->tm_yday = 0; + tm->tm_isdst = 0; + + ret = 0; + +exit: + ht1380_reset_on(priv); + return ret; +} + +static int ht1380_write_protection_off(struct ht1380_priv *priv) +{ + int ret; + const int PROTECT = 0x8E; + + ret = ht1380_reset_off(priv); + if (ret) + return ret; + + ret = ht1380_send_byte(priv, PROTECT); + if (ret) + return ret; + ret = ht1380_send_byte(priv, 0); /* WP bit is 0 */ + if (ret) + return ret; + + return ht1380_reset_on(priv); +} + +static int ht1380_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + int ret, i, reg[N_REGS]; + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + return ret; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT); + if (ret) + goto exit; + + ret = ht1380_write_protection_off(priv); + if (ret) + goto exit; + + reg[SEC] = bin2bcd(tm->tm_sec); + reg[MIN] = bin2bcd(tm->tm_min); + reg[HOUR] = bin2bcd(tm->tm_hour); + reg[MDAY] = bin2bcd(tm->tm_mday); + reg[MONTH] = bin2bcd(tm->tm_mon); + reg[WDAY] = bin2bcd(tm->tm_wday) + 1; + reg[YEAR] = bin2bcd(tm->tm_year - 2000); + reg[WP] = 0x80; /* WP bit is 1 */ + + ret = ht1380_reset_off(priv); + if (ret) + goto exit; + + ret = ht1380_send_byte(priv, BURST); + for (i = 0; i < N_REGS && ret; i++) + ret = ht1380_send_byte(priv, reg[i]); + +exit: + ht1380_reset_on(priv); + return ret; +} + +static int ht1380_probe(struct udevice *dev) +{ + int ret; + struct ht1380_priv *priv; + + priv = dev_get_priv(dev); + if (!priv) + return -EINVAL; + + ret = gpio_request_by_name(dev, "rst-gpio", 0, + &priv->rst_desc, 0); + if (ret) + goto fail_rst; + + ret = gpio_request_by_name(dev, "clk-gpio", 0, + &priv->clk_desc, 0); + if (ret) + goto fail_clk; + + ret = gpio_request_by_name(dev, "dat-gpio", 0, + &priv->dat_desc, 0); + if (ret) + goto fail_dat; + + ret = dm_gpio_set_dir_flags(&priv->clk_desc, GPIOD_IS_OUT); + if (ret) + goto fail; + + ret = dm_gpio_set_dir_flags(&priv->rst_desc, GPIOD_IS_OUT); + if (ret) + goto fail; + + ret = ht1380_reset_on(priv); + if (ret) + goto fail; + + return 0; + +fail: + dm_gpio_free(dev, &priv->dat_desc); +fail_dat: + dm_gpio_free(dev, &priv->clk_desc); +fail_clk: + dm_gpio_free(dev, &priv->rst_desc); +fail_rst: + return ret; +} + +static int ht1380_remove(struct udevice *dev) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + + dm_gpio_free(dev, &priv->rst_desc); + dm_gpio_free(dev, &priv->clk_desc); + dm_gpio_free(dev, &priv->dat_desc); + return 0; +} + +static const struct rtc_ops ht1380_rtc_ops = { + .get = ht1380_rtc_get, + .set = ht1380_rtc_set, +}; + +static const struct udevice_id ht1380_rtc_ids[] = { + { .compatible = "holtek,ht1380" }, + { } +}; + +U_BOOT_DRIVER(rtc_ht1380) = { + .name = "rtc-ht1380", + .id = UCLASS_RTC, + .probe = ht1380_probe, + .remove = ht1380_remove, + .of_match = ht1380_rtc_ids, + .ops = &ht1380_rtc_ops, + .priv_auto = sizeof(struct ht1380_priv), +}; -- 2.34.1

3 4

[PATCH] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_nand_atf_defconfig | 2 +- configs/socfpga_agilex_qspi_atf_defconfig | 2 +- configs/socfpga_stratix10_nand_atf_defconfig | 2 +- configs/socfpga_stratix10_qspi_atf_defconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index 558dda1a2e..fb92ff2514 100755 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -26,7 +26,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run nandfitload; run linux_qspi_enable; run rsu_status; run nandfitboot" +CONFIG_BOOTCOMMAND="run nandfitload; run rsu_status; run nandfitboot" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_CACHE=y diff --git a/configs/socfpga_agilex_qspi_atf_defconfig b/configs/socfpga_agilex_qspi_atf_defconfig index 745aac3c5c..9d97d34c77 100755 --- a/configs/socfpga_agilex_qspi_atf_defconfig +++ b/configs/socfpga_agilex_qspi_atf_defconfig @@ -27,7 +27,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe;run qspifitload;run linux_qspi_enable;run rsu_status;run qspifitboot" +CONFIG_BOOTCOMMAND="sf probe;run qspifitload;run rsu_status;run qspifitboot" CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig index 7eb956733c..a3fd9742e8 100755 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -27,7 +27,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run nandfitload; run linux_qspi_enable; run rsu_status; run nandfitboot" +CONFIG_BOOTCOMMAND="run nandfitload; run rsu_status; run nandfitboot" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/socfpga_stratix10_qspi_atf_defconfig b/configs/socfpga_stratix10_qspi_atf_defconfig index 5f42c17d47..d9e55de4dc 100755 --- a/configs/socfpga_stratix10_qspi_atf_defconfig +++ b/configs/socfpga_stratix10_qspi_atf_defconfig @@ -27,7 +27,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe;run qspifitload;run linux_qspi_enable;run rsu_status;run qspifitboot" +CONFIG_BOOTCOMMAND="sf probe;run qspifitload;run rsu_status;run qspifitboot" CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -- 2.26.2

1 0

[PATCH] configs: defconfig: Load OS via FIT image in QSPI ATF boot for Stratix 10 and Agilex
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Update to load OS via FIT image in Stratix 10 and Agilex QSPI ATF boot flow. And, enable FIT signature checking with crc32 algorithm. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_qspi_atf_defconfig | 6 +++++- configs/socfpga_stratix10_qspi_atf_defconfig | 6 +++++- include/configs/socfpga_soc64_common.h | 3 +++ 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_agilex_qspi_atf_defconfig b/configs/socfpga_agilex_qspi_atf_defconfig index 0e82873bc1..745aac3c5c 100755 --- a/configs/socfpga_agilex_qspi_atf_defconfig +++ b/configs/socfpga_agilex_qspi_atf_defconfig @@ -15,6 +15,10 @@ CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_qspi" CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -23,7 +27,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" +CONFIG_BOOTCOMMAND="sf probe;run qspifitload;run linux_qspi_enable;run rsu_status;run qspifitboot" CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y diff --git a/configs/socfpga_stratix10_qspi_atf_defconfig b/configs/socfpga_stratix10_qspi_atf_defconfig index 16ee4896d0..5f42c17d47 100755 --- a/configs/socfpga_stratix10_qspi_atf_defconfig +++ b/configs/socfpga_stratix10_qspi_atf_defconfig @@ -15,6 +15,10 @@ CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_qspi" CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -23,7 +27,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" +CONFIG_BOOTCOMMAND="sf probe;run qspifitload;run linux_qspi_enable;run rsu_status;run qspifitboot" CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 2343a315b9..12da770077 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -59,6 +59,9 @@ "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ + "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \ + "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ -- 2.26.2

1 0

[PATCH] configs: defconfig: Remove duplicated CONFIG in socfpga_n5x_defconfig
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Remove duplicated CONFIG in socfpga_n5x_defconfig. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_n5x_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 4971acab8c..30747e389b 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -20,8 +20,6 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" CONFIG_USE_BOOTCOMMAND=y -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" CONFIG_BOOTCOMMAND="run fatscript;run mmcload;run linux_qspi_enable;run rsu_status;run mmcboot" CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -- 2.26.2

1 0

[PATCH] configs: defconfig: Load OS via FIT image in Stratix 10 and Agilex NAND boot
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Update to load OS via FIT image in Stratix 10 and Agilex NAND boot flow. And, enable FIT signature checking with crc32 algorithm. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_nand_atf_defconfig | 6 +++++- configs/socfpga_stratix10_nand_atf_defconfig | 6 +++++- include/configs/socfpga_soc64_common.h | 4 ++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index 0beec3d8dd..558dda1a2e 100755 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -14,6 +14,10 @@ CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand" CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -22,7 +26,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run nandboot" +CONFIG_BOOTCOMMAND="run nandfitload; run linux_qspi_enable; run rsu_status; run nandfitboot" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_CACHE=y diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig index cbb3f88ec2..7eb956733c 100755 --- a/configs/socfpga_stratix10_nand_atf_defconfig +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -14,6 +14,10 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_nand" +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 @@ -23,7 +27,7 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; rsu dtb; run nandboot" +CONFIG_BOOTCOMMAND="run nandfitload; run linux_qspi_enable; run rsu_status; run nandfitboot" CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_LOAD=y diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 8a9f4dc4c9..2343a315b9 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -85,6 +85,10 @@ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ "then source ${scriptaddr}; fi\0" \ + "nandfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${nandroot} rw rootwait rootfstype=jffs2; " \ + "bootm ${loadaddr}\0" \ + "nandfitload=nand read ${loadaddr} kernel\0" \ "socfpga_legacy_reset_compat=1\0" /* -- 2.26.2

1 0

[PATCH] arm: socfpga: n5x: Enable all features as in exisiting devices
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Enable more configurations and features as in Agilex device since all these hardware peripherals no change in N5X compare with Agilex. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_n5x_atf_defconfig | 2 ++ configs/socfpga_n5x_defconfig | 7 +++++-- configs/socfpga_n5x_vab_defconfig | 4 +++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 37c8436318..d2598b9fb3 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -55,6 +55,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y +CONFIG_CMD_MTD=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -70,6 +71,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SPL_ALTERA_SDRAM=y CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 5f415b7ad4..4971acab8c 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -20,7 +20,9 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1 earlyprintk=ttyS0,115200" +CONFIG_BOOTCOMMAND="run fatscript;run mmcload;run linux_qspi_enable;run rsu_status;run mmcboot" CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x3ff00000 @@ -44,9 +46,9 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_WDT=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -79,6 +81,7 @@ CONFIG_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_CMD_WDT=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index a57d54a7f2..977a90d493 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_WDT=y +CONFIG_CMD_MTD=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -71,6 +71,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SPL_ALTERA_SDRAM=y CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 @@ -90,5 +91,6 @@ CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_CMD_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -- 2.26.2

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[PATCH] configs/agilex: enable FPGA Partial Reconfiguration command
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: "Chew, Chiau Ee" <chiau.ee.chew(a)intel.com> This is to enable config to support FPGA Partial Reconfiguration command in agilex ATF and non-ATF uboot build. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_nand_atf_defconfig | 1 + ..._atf_defconfig => socfpga_agilex_nand_defconfig} | 12 +++++------- configs/socfpga_agilex_qspi_atf_defconfig | 1 + ..._atf_defconfig => socfpga_agilex_qspi_defconfig} | 13 ++++++------- configs/socfpga_agilex_vab_defconfig | 1 + 7 files changed, 16 insertions(+), 14 deletions(-) copy configs/{socfpga_agilex_nand_atf_defconfig => socfpga_agilex_nand_defconfig} (89%) copy configs/{socfpga_agilex_qspi_atf_defconfig => socfpga_agilex_qspi_defconfig} (88%) diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index bdfe764d9e..cc11fc1912 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -68,6 +68,7 @@ CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index e2d869610c..f7e767fbbe 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -62,6 +62,7 @@ CONFIG_BOOTFILE="Image" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig index a3b272d771..0beec3d8dd 100755 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -54,6 +54,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_defconfig similarity index 89% copy from configs/socfpga_agilex_nand_atf_defconfig copy to configs/socfpga_agilex_nand_defconfig index a3b272d771..5613237ae5 100755 --- a/configs/socfpga_agilex_nand_atf_defconfig +++ b/configs/socfpga_agilex_nand_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x20000 @@ -12,11 +12,10 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand" -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 -# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y @@ -27,8 +26,6 @@ CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_CMD_MEMTEST=y @@ -54,6 +51,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_agilex_qspi_atf_defconfig b/configs/socfpga_agilex_qspi_atf_defconfig index 8956abae36..0e82873bc1 100755 --- a/configs/socfpga_agilex_qspi_atf_defconfig +++ b/configs/socfpga_agilex_qspi_atf_defconfig @@ -49,6 +49,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BLK=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_agilex_qspi_atf_defconfig b/configs/socfpga_agilex_qspi_defconfig similarity index 88% copy from configs/socfpga_agilex_qspi_atf_defconfig copy to configs/socfpga_agilex_qspi_defconfig index 8956abae36..ee6b7b8660 100755 --- a/configs/socfpga_agilex_qspi_atf_defconfig +++ b/configs/socfpga_agilex_qspi_defconfig @@ -1,7 +1,8 @@ CONFIG_ARM=y +CONFIG_ARM_SMCCC=y CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" CONFIG_ARCH_SOCFPGA=y -CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_TEXT_BASE=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x1000 @@ -13,11 +14,10 @@ CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_qspi" -CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 -# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y @@ -26,8 +26,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " CONFIG_CMD_MEMTEST=y @@ -49,6 +47,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BLK=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 6f15b3e962..3c41f16162 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -69,6 +69,7 @@ CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y -- 2.26.2

1 0

[PATCH] configs: Enable ATF support for QSPI & NAND boot
by Jit Loon Lim 21 Nov '22

21 Nov '22

From: Chee Hong Ang <chee.hong.ang(a)intel.com> HSD #1508277418: Add defconfigs with ATF support for QSPI and NAND boot on Stratix10 and Agilex platforms. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- configs/socfpga_agilex_nand_atf_defconfig | 88 +++++++++++++++++++ configs/socfpga_agilex_qspi_atf_defconfig | 76 +++++++++++++++++ configs/socfpga_stratix10_nand_atf_defconfig | 90 ++++++++++++++++++++ configs/socfpga_stratix10_qspi_atf_defconfig | 77 +++++++++++++++++ include/configs/socfpga_soc64_common.h | 22 +++++ 5 files changed, 353 insertions(+) create mode 100755 configs/socfpga_agilex_nand_atf_defconfig create mode 100755 configs/socfpga_agilex_qspi_atf_defconfig create mode 100755 configs/socfpga_stratix10_nand_atf_defconfig create mode 100755 configs/socfpga_stratix10_qspi_atf_defconfig diff --git a/configs/socfpga_agilex_nand_atf_defconfig b/configs/socfpga_agilex_nand_atf_defconfig new file mode 100755 index 0000000000..a3b272d771 --- /dev/null +++ b/configs/socfpga_agilex_nand_atf_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x00200000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xffe00000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_nand" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; run nandboot" +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND_DENALI_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set \ No newline at end of file diff --git a/configs/socfpga_agilex_qspi_atf_defconfig b/configs/socfpga_agilex_qspi_atf_defconfig new file mode 100755 index 0000000000..8956abae36 --- /dev/null +++ b/configs/socfpga_agilex_qspi_atf_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x020C0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk_qspi" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" +CONFIG_SPL_CACHE=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BLK=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y \ No newline at end of file diff --git a/configs/socfpga_stratix10_nand_atf_defconfig b/configs/socfpga_stratix10_nand_atf_defconfig new file mode 100755 index 0000000000..cbb3f88ec2 --- /dev/null +++ b/configs/socfpga_stratix10_nand_atf_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x00200000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_nand" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; rsu dtb; run nandboot" +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND_DENALI_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y \ No newline at end of file diff --git a/configs/socfpga_stratix10_qspi_atf_defconfig b/configs/socfpga_stratix10_qspi_atf_defconfig new file mode 100755 index 0000000000..16ee4896d0 --- /dev/null +++ b/configs/socfpga_stratix10_qspi_atf_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x200000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x020C0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_qspi" +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x2000000 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe;run qspiload;run linux_qspi_enable;rsu dtb;run qspiboot" +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BLK=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y \ No newline at end of file diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 06198ddd82..8a9f4dc4c9 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -33,10 +33,32 @@ * U-Boot environment configurations */ + /* + * NAND support + */ +#ifdef CONFIG_NAND_DENALI +#ifndef CONFIG_SPL_FIT +#define CONFIG_SPL_NAND_RAW_ONLY +#endif +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (1 * 1024 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#endif /* CONFIG_NAND_DENALI */ + /* * Environment variable */ #define CONFIG_EXTRA_ENV_SETTINGS \ + "qspibootimageaddr=0x020E0000\0" \ + "qspifdtaddr=0x020D0000\0" \ + "bootimagesize=0x01F00000\0" \ + "fdtimagesize=0x00010000\0" \ + "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \ + "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \ + "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \ + "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ -- 2.26.2

1 0

[PATCH v2 0/3] Introduce STM32MP13 RCC driver
by Gabriel Fernandez 21 Nov '22

21 Nov '22

This serie adds support of clock and reset for STM32MP13. Changes in v2: - deference check_security() call back - use of ccf_clk_(enable/disable/get_rate/set_rate) ops - fix gate refcounting - documented structures in clock-core API - remove useless spinlocks - cosmetic changes - remove useless defines Gabriel Fernandez (3): dt-bindings: stm32mp13: add clock & reset support for STM32MP13 clk: stm32mp13: introduce STM32MP13 RCC driver arm: dts: stm32mp13: add support of RCC driver MAINTAINERS | 2 + arch/arm/dts/stm32mp13-u-boot.dtsi | 4 + arch/arm/dts/stm32mp131.dtsi | 119 +-- arch/arm/dts/stm32mp133.dtsi | 4 +- arch/arm/dts/stm32mp13xc.dtsi | 3 +- arch/arm/dts/stm32mp13xf.dtsi | 3 +- drivers/clk/stm32/Kconfig | 15 + drivers/clk/stm32/Makefile | 2 + drivers/clk/stm32/clk-stm32-core.c | 271 ++++++ drivers/clk/stm32/clk-stm32-core.h | 223 +++++ drivers/clk/stm32/clk-stm32mp13.c | 841 +++++++++++++++++++ drivers/clk/stm32/stm32mp13_rcc.h | 288 +++++++ include/dt-bindings/clock/stm32mp13-clks.h | 229 +++++ include/dt-bindings/reset/stm32mp13-resets.h | 100 +++ 14 files changed, 2025 insertions(+), 79 deletions(-) create mode 100644 drivers/clk/stm32/clk-stm32-core.c create mode 100644 drivers/clk/stm32/clk-stm32-core.h create mode 100644 drivers/clk/stm32/clk-stm32mp13.c create mode 100644 drivers/clk/stm32/stm32mp13_rcc.h create mode 100644 include/dt-bindings/clock/stm32mp13-clks.h create mode 100644 include/dt-bindings/reset/stm32mp13-resets.h -- 2.25.1

3 6

problem with reading the NV memory index of TPM slb9670
by Tasos Terzidis 21 Nov '22

21 Nov '22

Hello, I tried to use a tpm2 command for reading the NV memory index of an slb9670 TPM. I noticed in file cmd/tpm-v2.c, that the command tpm2 nv_read_value (as tpm nv_read_value) is not implemented. In file lib/tpm-v2.c there is the tpm2_nv_read_value function. Do you plan to implement the command tpm2 nv_read_value in the future ? Then I used the tpm nv_read_value index addr count "Read <count> bytes from space <index> to memory address <addr>". The syntax I used is tpm nv_read_value 0x100000000 0x30000000 20 I’m trying to read 32 bytes from 0x100000000 index nv memory of TPM to 0x30000000 memory of u-boot U-boot can’t understand the command and returns the help listing all the commands for tpm. I also used tpm nv_read_value 0x0 0x30000000 20 0x0 as an offset to 0x100000000 index of NV memory (following the syntax of tpm2_nvread command o TSS tpm –tools) Same result, list of commands for tpm Other commands of tpm such as tpm2 pcr read or extend functions as expected in u-boot environment I can’t understand what I do wrong Thank you Tasos Terzids

3 2