November 2022 - U-Boot

[PATCH] xilinx: versal-net: Disable LMB for mini configuration
by Michal Simek 22 Nov '22

22 Nov '22

There is no reason to have LMB enabled on mini configuration because it is only consuming space that's why disable it. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/xilinx_versal_net_mini_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig index 03a63288acdc..c5fa431a8c9d 100644 --- a/configs/xilinx_versal_net_mini_defconfig +++ b/configs/xilinx_versal_net_mini_defconfig @@ -70,3 +70,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y # CONFIG_GZIP is not set +# CONFIG_LMB is not set -- 2.36.1

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[PATCH] arm64: zynqmp: Describe TI phy as ethernet-phy-id with reset on zcu106
by Michal Simek 22 Nov '22

22 Nov '22

zcu106 also connects ethernet phy reset via tca6416 chip as is done on other evaluation boards. That's why describe this connection to make sure that ethernet phy is reset before it's use. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-zcu106-revA.dts | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 3e137676feb6..4858b4d1f5e9 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -200,12 +200,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + reg = <0xc>; + compatible = "ethernet-phy-id2000.a231"; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; -- 2.36.1

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[PATCH 0/3] efi_loader: Fix buffer underflow in FatToStr
by Heinrich Schuchardt 22 Nov '22

22 Nov '22

Fix a buffer underflow in the FatToStr implementation. Add a unit test to detect incorrect conversion of characters >= 0x80. v2: Reformat commit message Add unit test Heinrich Schuchardt (2): efi_selftest: unsigned char parameter for efi_st_strcmp_16_8() efi_selftest: Improve the FatToStr() unit test Mikhail Ilin (1): efi_loader: Fix buffer underflow include/efi_selftest.h | 2 +- lib/efi_loader/efi_unicode_collation.c | 2 +- lib/efi_selftest/efi_selftest_unicode_collation.c | 13 +++++++++++++ lib/efi_selftest/efi_selftest_util.c | 2 +- 4 files changed, 16 insertions(+), 3 deletions(-) -- 2.37.2

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[PATCH] efi_loader: Fix buffer underflow If the array index 'i' < 128, the 'codepage' array is accessed using [-128...-1] in efi_unicode_collation.c:262. This can lead to a buffer overflow. Negative index in efi_unicode_collation.c:262. The index of the 'codepage' array should be c-0x80 instead of i-0x80.
by Mikhail Ilin 22 Nov '22

22 Nov '22

Fixes: 0bc4b0da7b59 ("efi_loader: EFI_UNICODE_COLLATION_PROTOCOL") Signed-off-by: Mikhail Ilin <ilin.mikhail.ol(a)gmail.com> --- lib/efi_loader/efi_unicode_collation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c index c700be8756..282045b556 100644 --- a/lib/efi_loader/efi_unicode_collation.c +++ b/lib/efi_loader/efi_unicode_collation.c @@ -259,7 +259,7 @@ static void EFIAPI efi_fat_to_str(struct efi_unicode_collation_protocol *this, for (i = 0; i < fat_size; ++i) { c = (unsigned char)fat[i]; if (c > 0x80) - c = codepage[i - 0x80]; + c = codepage[c - 0x80]; string[i] = c; if (!c) break; -- 2.17.1

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[PATCH] watchdog: Drop GD_FLG_WDT_READY as it's not used any more
by Stefan Roese 22 Nov '22

22 Nov '22

Since commit c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic framework") GD_FLG_WDT_READY has become write-only. This patch now removes this flag completely. The vacant spot in gd_flags is filled with the newly introduced GD_FLG_CYCLIC_RUNNING flag. Suggested-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/watchdog/wdt-uclass.c | 1 - include/asm-generic/global_data.h | 8 ++------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 82df0ff0be5a..509896a1b808 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -105,7 +105,6 @@ int initr_watchdog(void) init_watchdog_dev(dev); } - gd->flags |= GD_FLG_WDT_READY; return 0; } diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 88829126fb2a..da17ac8cbc88 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -635,9 +635,9 @@ enum gd_flags { */ GD_FLG_LOG_READY = 0x10000, /** - * @GD_FLG_WDT_READY: watchdog is ready for use + * @GD_FLG_CYCLIC_RUNNING: cyclic_run is in progress */ - GD_FLG_WDT_READY = 0x20000, + GD_FLG_CYCLIC_RUNNING = 0x20000, /** * @GD_FLG_SKIP_LL_INIT: don't perform low-level initialization */ @@ -650,10 +650,6 @@ enum gd_flags { * @GD_FLG_FDT_CHANGED: Device tree change has been detected by tests */ GD_FLG_FDT_CHANGED = 0x100000, - /** - * @GD_FLG_CYCLIC_RUNNING: cyclic_run is in progress - */ - GD_FLG_CYCLIC_RUNNING = 0x200000, }; #endif /* __ASSEMBLY__ */ -- 2.38.1

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[PATCH v2] watchdog: designware: make reset really optional
by Quentin Schulz 22 Nov '22

22 Nov '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> Checking for DM_RESET is not enough since not all watchdog implementations use a reset lane. Such is the case for Rockchip implementation for example. Since reset_assert_bulk will only succeed if the resets property exists in the watchdog DT node, it needs to be called only if a reset property is present. This adds a condition on the resets property presence in the watchdog DT node before assuming a reset lane needs to be fetched with reset_assert_bulk, by calling ofnode_read_prop. Cc: Quentin Schulz <foss+uboot(a)0leil.net> Reviewed-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- To: Stefan Roese <sr(a)denx.de> Cc: u-boot(a)lists.denx.de --- Changes in v2: - added Rb, - changed indentation from space to tabs while adding condition, - Link to v1: https://lore.kernel.org/r/20221114-dw-wdt-no-reset-v1-0-15a62faba4cc@theobr… --- drivers/watchdog/designware_wdt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index cad756aeaf..f8df1916b5 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -72,13 +72,13 @@ static int designware_wdt_reset(struct udevice *dev) static int designware_wdt_stop(struct udevice *dev) { struct designware_wdt_priv *priv = dev_get_priv(dev); + __maybe_unused int ret; designware_wdt_reset(dev); writel(0, priv->base + DW_WDT_CR); - if (CONFIG_IS_ENABLED(DM_RESET)) { - int ret; - + if (CONFIG_IS_ENABLED(DM_RESET) && + ofnode_read_prop(dev_ofnode(dev), "resets", &ret)) { ret = reset_assert_bulk(&priv->resets); if (ret) return ret; @@ -135,7 +135,8 @@ static int designware_wdt_probe(struct udevice *dev) priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ; #endif - if (CONFIG_IS_ENABLED(DM_RESET)) { + if (CONFIG_IS_ENABLED(DM_RESET) && + ofnode_read_prop(dev_ofnode(dev), "resets", &ret)) { ret = reset_get_bulk(dev, &priv->resets); if (ret) goto err; --- base-commit: 0cbeed4f6648e0e4966475e3544280a69ecb59d3 change-id: 20221114-dw-wdt-no-reset-2296a2bf37b3 Best regards, -- Quentin Schulz <quentin.schulz(a)theobroma-systems.com>

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[PATCH] Subject: [patch]SPI: GD SPI: Add Gigadevice SPI NOR part numbers
by Victor lim 22 Nov '22

22 Nov '22

added gigadevice in the defconfig file and ID in the ids.c file Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + drivers/mtd/spi/spi-nor-ids.c | 137 +++++++++++++++------- 3 files changed, 94 insertions(+), 45 deletions(-) diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index c6401c2a54..75014117f1 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -78,3 +78,4 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set +CONFIG_SPI_FLASH_GIGADEVICE=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 60f0d7cac4..cd245906ab 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -76,3 +76,4 @@ CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y # CONFIG_GZIP is not set # CONFIG_LMB is not set +CONFIG_SPI_FLASH_GIGADEVICE=y diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7d66f9ef36..7cb183c1a3 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -87,51 +87,98 @@ const struct flash_info spi_nor_ids[] = { { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - /* GigaDevice */ - { - INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) - }, +/* GigaDevice - GD25Q or B series */ + {INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)}, + {INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)}, + {INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)}, + {INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)}, + {INFO("gd25b series 256Mbit", 0xc84019, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, + {INFO("gd25b series 512Mbit", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55b series 1Gbit", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55b series 2Gbit", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25F series */ + {INFO("gd25f series 64Mbit", 0xc84317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25f series 128Mbit", 0xc84318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25f series 256Mbit", 0xc84319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55f series 512Mbit", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25T series */ + {INFO("gd25t series 512Mbit", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t series 1Gbit", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55t02ge", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25X series */ + {INFO("gd25x series 512Mbit", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x series 1Gbit", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55x series 2Gbit", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25LB series */ + {INFO("gd25lb series 16Mbit", 0xc86015, 0, 64 * 1024, 32, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lb series 32Mbit", 0xc86016, 0, 64 * 1024, 64, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lb series 64Mbit", 0xc86017, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lb series 128Mbit", 0xc86018, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lb series 256Mbit", 0xc86019, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lb series 256Mbit", 0xc86719, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lb series 512Mbit", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb series 1Gbit", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lb series 2Gbit", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25LF series */ + {INFO("gd25lf series 8Mbit", 0xc86314, 0, 64 * 1024, 16, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf series 16Mbit", 0xc86315, 0, 64 * 1024, 32, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)}, + {INFO("gd25lf series 32Mbit", 0xc86316, 0, 64 * 1024, 64, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf series 64Mbit", 0xc86317, 0, 64 * 1024, 128, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf series 128Mbit", 0xc86318, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) }, + {INFO("gd25lf series 256Mbit", 0xc86319, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lf series 512Mbit", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25LT series */ + {INFO("gd25lt256e", 0xc86619, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lt512me", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt01ge", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lt02ge", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, +/* GigaDevice - GD25LX series */ + {INFO("gd25lx series 256Mbit", 0xc86819, 0, 64 * 1024, 512, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lx series 512Mbit", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lx series 1Gbit", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + {INFO("gd55lx series 2Gbit", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ -- 2.25.1

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[PATCH] SPI: GD SPI, enable GIGADEVICE in the config file
by Victor Lim 22 Nov '22

22 Nov '22

Added GIGADEVICE=y in the defconfig files Signed-off-by: Victor Lim <vlim(a)gigadevice.com> --- configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index c6401c2a54..75014117f1 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -78,3 +78,4 @@ CONFIG_ZYNQMP_GQSPI=y CONFIG_PANIC_HANG=y # CONFIG_GZIP is not set # CONFIG_LMB is not set +CONFIG_SPI_FLASH_GIGADEVICE=y diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 60f0d7cac4..cd245906ab 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -76,3 +76,4 @@ CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y # CONFIG_GZIP is not set # CONFIG_LMB is not set +CONFIG_SPI_FLASH_GIGADEVICE=y -- 2.25.1

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[PATCH] arm: socfpga: n5x: Remove invalid configuration for N5X
by Jit Loon Lim 22 Nov '22

22 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> These configurations no longer valid for N5X, remove them. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/Kconfig | 1 - arch/arm/mach-socfpga/Makefile | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index df44530e83..4e366e5413 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -97,7 +97,6 @@ config TARGET_SOCFPGA_N5X select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select CLK - select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index ec38b64dd4..58a486f6de 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -64,11 +64,22 @@ obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += smmu_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +ifndef CONFIG_SPL_BUILD +obj-y += rsu.o +obj-y += rsu_ll_qspi.o +obj-y += rsu_misc.o +obj-y += rsu_s10.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o +obj-$(CONFIG_ARMV8_PSCI) += smc_ecc_dbe_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_registers_s10.o +obj-$(CONFIG_ARMV8_PSCI) += smc_rsu_s10.o +endif endif ifdef CONFIG_SPL_BUILD -- 2.26.2

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[PATCH] ddr: altera: n5x: Enhance driver to support LPDDR4
by Jit Loon Lim 22 Nov '22

22 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Enhance driver to common DDR driver for supporting both DDR4 and LPDDR4. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi index 502da36bd8..6c1d25fa05 100644 --- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -15,7 +15,11 @@ memory { /* +<<<<<<< HEAD * Memory type: DDR4 (non-interleaving mode) +======= + * Memory type: DDR4 +>>>>>>> ddr: altera: n5x: Enhance driver to support LPDDR4 * 16GB * <0 0x00000000 0 0x80000000>, * <4 0x80000000 3 0x80000000>; -- 2.26.2

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