November 2022 - U-Boot

[PATCH] ddr: altera: n5x: Return error if invalid DDR type is detected in argument
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Return error immediately if invalid DDR type is detected in argument so that uninitialized local variables such val and upd_val would not be used. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 5117a5c4cf..8d28cdbc03 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2430,6 +2430,9 @@ static int set_cal_res_to_umctl2(struct ddr_handoff *handoff, upd_val = GET_LOWB_DATA(readw((uintptr_t)(handoff->phy_base + DMEM_MB_CDD_CHB_WW_0_1_OFFSET))); + } else { + debug("%s: Invalid DDR controller type\n", __func__); + return -ENXIO; } upd_val = max(val, upd_val); -- 2.26.2

1 0

[PATCH] arm: socfpga: soc64: Fix with correct header file
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> HSD #18016722456: Includes only required header for mdelay function. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/secure_vab.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index 02ebf89b85..797e60d12f 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -5,13 +5,13 @@ */ #include <common.h> -#include <exports.h> #include <log.h> #include <malloc.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/secure_vab.h> #include <asm/arch/smc_api.h> #include <asm/unaligned.h> +#include <linux/delay.h> #include <linux/errno.h> #include <linux/intel-smc.h> -- 2.26.2

1 0

[PATCH] ddr: altera: n5x: Checking DDR init hang before reset due to watchdog
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> DDR need to be initialized and running calibration if DDR init hang before reset due to watchdog. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 7d4225e471..5117a5c4cf 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -428,6 +428,17 @@ enum data_process { LOADING }; +bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK) + return true; + + return false; +} + bool is_ddr_dbe_triggered(void) { u32 reg = readl(socfpga_get_sysmgr_addr() + @@ -491,13 +502,13 @@ void reset_type_print(enum reset_type reset_t) } } -bool is_ddr_init_skipped(u32 reg) +bool is_ddr_init_skipped(u32 reg, bool is_ddr_hang_be4_rst) { enum reset_type reset_t = get_reset_type(reg); reset_type_print(reset_t); - if (!is_ddr_dbe_triggered()) { + if (!is_ddr_dbe_triggered() && !is_ddr_hang_be4_rst) { if (reset_t == WARM_RESET) { debug("%s: DDR init is skipped\n", __func__); return true; @@ -517,13 +528,13 @@ bool is_ddr_init_skipped(u32 reg) return false; } -bool is_ddr_calibration_skipped(u32 reg) +bool is_ddr_calibration_skipped(u32 reg, bool is_ddr_hang_be4_rst) { enum reset_type reset_t = get_reset_type(reg); if ((reset_t == NCONFIG || reset_t == JTAG_CONFIG || reset_t == RSU_RECONFIG) && is_ddr_retention_enabled(reg) && - !is_ddr_dbe_triggered()) { + !is_ddr_dbe_triggered() && !is_ddr_hang_be4_rst) { debug("%s: DDR retention bit is set\n", __func__); return true; } @@ -1579,7 +1590,8 @@ static bool is_cal_bak_data_valid(void) return true; } -static int init_phy(struct ddr_handoff *ddr_handoff_info) +static int init_phy(struct ddr_handoff *ddr_handoff_info, + bool *need_calibrate, bool is_ddr_hang_be4_rst) { u32 handoff_table[ddr_handoff_info->phy_handoff_length]; u32 i, value; @@ -1609,7 +1621,7 @@ static int init_phy(struct ddr_handoff *ddr_handoff_info) handoff_process(ddr_handoff_info, ddr_handoff_info->phy_handoff_base, ddr_handoff_info->phy_handoff_length, ddr_handoff_info->phy_base); - if (is_ddr_calibration_skipped(reg)) { + if (is_ddr_calibration_skipped(reg, is_ddr_hang_be4_rst)) { if (is_cal_bak_data_valid()) *need_calibrate = false; else @@ -2848,6 +2860,7 @@ int sdram_mmr_init_full(struct udevice *dev) u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); int ret; + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); bool need_calibrate = true; ulong ddr_offset; char *endptr; @@ -2873,7 +2886,7 @@ int sdram_mmr_init_full(struct udevice *dev) */ writel(SOC64_CRAM_PHY_BACKUP_SKIP_MAGIC, SOC64_OCRAM_PHY_BACKUP_BASE); - if (!is_ddr_init_skipped(reg)) { + if (!is_ddr_init_skipped(reg, is_ddr_hang_be4_rst)) { printf("SDRAM init in progress ...\n"); ddr_init_inprogress(true); @@ -2915,7 +2928,8 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR controller configuration is completed\n"); /* Initialize DDR PHY */ - ret = init_phy(&ddr_handoff_info, &need_calibrate); + ret = init_phy(&ddr_handoff_info, &need_calibrate, + is_ddr_hang_be4_rst); if (ret) { debug("%s: Failed to inilialize DDR PHY\n", __func__); return ret; -- 2.26.2

1 0

[PATCH] ddr: altera: n5x: Checking DDR DBE
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> DDR need to be initialized and running calibration if DBE is triggered Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index d707bba862..7d4225e471 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -428,6 +428,17 @@ enum data_process { LOADING }; +bool is_ddr_dbe_triggered(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK) + return true; + + return false; +} + void ddr_init_inprogress(bool start) { if (start) @@ -486,17 +497,20 @@ bool is_ddr_init_skipped(u32 reg) reset_type_print(reset_t); - if (reset_t == WARM_RESET) { - debug("%s: DDR init is skipped\n", __func__); - return true; - } - - if (reset_t == COLD_RESET) { - if (is_ddr_retention_enabled(reg)) { - debug("%s: DDR retention bit is set\n", __func__); + if (!is_ddr_dbe_triggered()) { + if (reset_t == WARM_RESET) { debug("%s: DDR init is skipped\n", __func__); return true; } + + if (reset_t == COLD_RESET) { + if (is_ddr_retention_enabled(reg)) { + debug("%s: DDR retention bit is set\n", + __func__); + debug("%s: DDR init is skipped\n", __func__); + return true; + } + } } debug("%s: DDR init is required\n", __func__); @@ -508,7 +522,8 @@ bool is_ddr_calibration_skipped(u32 reg) enum reset_type reset_t = get_reset_type(reg); if ((reset_t == NCONFIG || reset_t == JTAG_CONFIG || - reset_t == RSU_RECONFIG) && is_ddr_retention_enabled(reg)) { + reset_t == RSU_RECONFIG) && is_ddr_retention_enabled(reg) && + !is_ddr_dbe_triggered()) { debug("%s: DDR retention bit is set\n", __func__); return true; } -- 2.26.2

1 0

[PATCH] arm: socfpga: n5x: Update DDR init progress bit
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> The bit[30] of boot scratch cold 8 register is used as DDR init progress tracking by SDM when watchdog is triggered due to ddr init hang, so that SDM can run a clean reset to DDR subsystem. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 135bc8fd7d..d707bba862 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -428,6 +428,18 @@ enum data_process { LOADING }; +void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); +} + bool is_ddr_retention_enabled(u32 reg) { if (reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK) @@ -2848,6 +2860,7 @@ int sdram_mmr_init_full(struct udevice *dev) if (!is_ddr_init_skipped(reg)) { printf("SDRAM init in progress ...\n"); + ddr_init_inprogress(true); /* * Polling reset complete, must be high to ensure DDR @@ -2994,6 +3007,10 @@ int sdram_mmr_init_full(struct udevice *dev) priv->info.size = gd->ram_size; sdram_size_check(&bd); + + /* Marking end of ddr init with passing basic memory test */ + ddr_init_inprogress(false); + sdram_set_firewall(&bd); ddr_offset = simple_strtoul(offset, &endptr, 16); -- 2.26.2

1 0

[PATCH] arm: socfpga: Define the usage of boot scratch cold reg 8
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> The boot scratch cold reg 8 is shared between DBE, DDR init progress update and Linux EDAC. This patch defines how the bits are used by respective features above and their macro names used in U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- .../include/mach/system_manager_soc64.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c2d1f8e4b9..4441649a31 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -102,6 +102,19 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK GENMASK(30, 28) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) -- 2.26.2

1 0

[PATCH] arm: socfpga: soc64: Add malloc.h
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> HSD #1308580006: Some compilers complaint implicit declaration of malloc function, and some compilers have no this issue. Adding malloc.h to resolve this issue. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- arch/arm/mach-socfpga/secure_vab.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index e2db588506..02ebf89b85 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -1,18 +1,19 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> * */ +#include <common.h> +#include <exports.h> +#include <log.h> +#include <malloc.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/secure_vab.h> #include <asm/arch/smc_api.h> #include <asm/unaligned.h> -#include <common.h> -#include <exports.h> #include <linux/errno.h> #include <linux/intel-smc.h> -#include <log.h> #define CHUNKSZ_PER_WD_RESET (256 * SZ_1K) -- 2.26.2

1 0

[PATCH 1/2] arm: socfpga: soc64: Add mask support when enable/disable bridges
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Ley Foon Tan <ley.foon.tan(a)intel.com> HSD #18016042797-1: The existing ignore the "mask" value when call to socfpga_bridges_reset(). This patch add the mask support when bridge enable/disable. Mask value: BIT0: soc2fpga BIT1: lwhps2fpga BIT2: fpga2soc These bridges available only in Stratix 10: BIT3: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- .../include/mach/reset_manager_soc64.h | 9 +- arch/arm/mach-socfpga/misc_soc64.c | 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 154 +++++++++++------- 3 files changed, 101 insertions(+), 64 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 9589b61749..b662b4450d 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -9,7 +9,8 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); void print_reset_info(void); -void socfpga_bridges_reset(int enable); +void socfpga_bridges_reset(int enable, unsigned int mask); +void socfpga_bridges_reset_psci(int enable, unsigned int mask); #define RSTMGR_SOC64_STATUS 0x00 #define RSTMGR_SOC64_HDSKEN 0x10 @@ -29,12 +30,6 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_F2SDRAM1_MASK BIT(4) #define RSTMGR_BRGMODRST_F2SDRAM2_MASK BIT(5) #define RSTMGR_BRGMODRST_DDRSCH_MASK BIT(6) -#define BRGMODRST_SOC2FPGA_BRIDGES (RSTMGR_BRGMODRST_SOC2FPGA_MASK | \ - RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) -#define BRGMODRST_FPGA2SOC_BRIDGES (RSTMGR_BRGMODRST_FPGA2SOC_MASK | \ - RSTMGR_BRGMODRST_F2SDRAM0_MASK | \ - RSTMGR_BRGMODRST_F2SDRAM1_MASK | \ - RSTMGR_BRGMODRST_F2SDRAM2_MASK) #define RSTMGR_HDSKEN_FPGAHSEN BIT(2) #define RSTMGR_HDSKREQ_FPGAHSREQ BIT(2) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 2acdfad07b..49b241b7b8 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -87,5 +87,5 @@ void do_bridge_reset(int enable, unsigned int mask) return; } - socfpga_bridges_reset(enable); + socfpga_bridges_reset(enable, mask); } diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 0274c4dbdb..128cdbbbe3 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -24,30 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; #define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 #define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54 -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 -#define FLAGINSTATUS0_MPFE_NOC_IDLE (BIT(0) | BIT(4) | BIT(8)) -#define FLAGINSTATUS0_MPFE_NOC_IDLEACK (BIT(1) | BIT(5) | BIT(9)) -#define FLAGINSTATUS0_F2S_CMD_EMPTY (BIT(2) | BIT(6) | BIT(10)) -#define FLAGINSTATUS0_F2S_RESP_EMPTY (BIT(3) | BIT(7) | BIT(11)) - -#define FLGAOUTSET0_MPFE_NOC_IDLEREQ (BIT(0) | BIT(3) | BIT(6)) -#define FLGAOUTSET0_F2S_EN (BIT(1) | BIT(4) | BIT(7)) -#define FLGAOUTSET0_F2S_FORCE_DRAIN (BIT(2) | BIT(5) | BIT(8)) - -#define FLGAOUTCLR0_F2S_IDLEREQ (BIT(0) | BIT(3) | BIT(6)) -#else -#define FLAGINSTATUS0_MPFE_NOC_IDLE BIT(0) -#define FLAGINSTATUS0_MPFE_NOC_IDLEACK BIT(1) -#define FLAGINSTATUS0_F2S_CMD_EMPTY BIT(2) -#define FLAGINSTATUS0_F2S_RESP_EMPTY BIT(3) - -#define FLGAOUTSET0_MPFE_NOC_IDLEREQ BIT(0) -#define FLGAOUTSET0_F2S_EN BIT(1) -#define FLGAOUTSET0_F2S_FORCE_DRAIN BIT(2) - -#define FLGAOUTCLR0_F2S_IDLEREQ BIT(0) -#endif - #define POLL_FOR_ZERO(expr, timeout_ms) \ { \ int timeout = (timeout_ms); \ @@ -110,26 +86,79 @@ void socfpga_per_reset_all(void) writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST); } -static __always_inline void socfpga_f2s_bridges_reset(int enable) +static __always_inline void socfpga_f2s_bridges_reset(int enable, + unsigned int mask) { int timeout_ms = 300; u32 empty; + u32 brg_mask; + u32 flagout_idlereq = 0; + u32 flagoutset_fdrain = 0; + u32 flagoutset_en = 0; + u32 flaginstatus_idleack = 0; + u32 flaginstatus_respempty = 0; + + if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + /* Support fpga2soc and f2sdram */ + brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | + RSTMGR_BRGMODRST_F2SDRAM0_MASK | + RSTMGR_BRGMODRST_F2SDRAM1_MASK | + RSTMGR_BRGMODRST_F2SDRAM2_MASK); + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM0_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM1_MASK) { + flagout_idlereq |= BIT(3); + flaginstatus_idleack |= BIT(5); + flagoutset_fdrain |= BIT(5); + flagoutset_en |= BIT(4); + flaginstatus_respempty |= BIT(7); + } + + if (brg_mask & RSTMGR_BRGMODRST_F2SDRAM2_MASK) { + flagout_idlereq |= BIT(6); + flaginstatus_idleack |= BIT(9); + flagoutset_fdrain |= BIT(8); + flagoutset_en |= BIT(7); + flaginstatus_respempty |= BIT(11); + } + } else { + /* Support fpga2soc only */ + brg_mask = mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK; + if (brg_mask & RSTMGR_BRGMODRST_FPGA2SOC_MASK) { + flagout_idlereq |= BIT(0); + flaginstatus_idleack |= BIT(1); + flagoutset_fdrain |= BIT(2); + flagoutset_en |= BIT(1); + flaginstatus_respempty |= BIT(3); + } + } + + /* mask is not set, return here */ + if (!brg_mask) + return; if (enable) { clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_FPGA2SOC_BRIDGES); + brg_mask); clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, - FLGAOUTSET0_MPFE_NOC_IDLEREQ); + flagout_idlereq); POLL_FOR_ZERO((readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & - FLAGINSTATUS0_MPFE_NOC_IDLEACK), timeout_ms); + flaginstatus_idleack), timeout_ms); clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, - FLGAOUTSET0_F2S_FORCE_DRAIN); + flagoutset_fdrain); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN); + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); __socfpga_udelay(1); /* wait 1us */ } else { @@ -140,11 +169,11 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable) POLL_FOR_SET(readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKACK), timeout_ms); clrbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + - F2SDRAM_SIDEBAND_FLAGOUTSET0, FLGAOUTSET0_F2S_EN); + F2SDRAM_SIDEBAND_FLAGOUTSET0, flagoutset_en); __socfpga_udelay(1); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTSET0, - FLGAOUTSET0_F2S_FORCE_DRAIN); + flagoutset_fdrain); __socfpga_udelay(1); do { @@ -154,11 +183,11 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable) */ empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & - FLAGINSTATUS0_F2S_RESP_EMPTY; + flaginstatus_respempty; if (empty) { empty = readl(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGINSTATUS0) & - FLAGINSTATUS0_F2S_RESP_EMPTY; + flaginstatus_respempty; if (empty) break; } @@ -168,60 +197,73 @@ static __always_inline void socfpga_f2s_bridges_reset(int enable) } while (timeout_ms); setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_FPGA2SOC_BRIDGES & - ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); + brg_mask & ~RSTMGR_BRGMODRST_FPGA2SOC_MASK); clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_HDSKREQ, RSTMGR_HDSKREQ_FPGAHSREQ); setbits_le32(SOCFPGA_F2SDRAM_MGR_ADDRESS + F2SDRAM_SIDEBAND_FLAGOUTCLR0, - FLGAOUTCLR0_F2S_IDLEREQ); + flagout_idlereq); } } -static __always_inline void socfpga_s2f_bridges_reset(int enable) +static __always_inline void socfpga_s2f_bridges_reset(int enable, + unsigned int mask) { + unsigned int noc_mask = 0; + unsigned int brg_mask = 0; + + if (mask & RSTMGR_BRGMODRST_SOC2FPGA_MASK) { + noc_mask = SYSMGR_NOC_H2F_MSK; + brg_mask = RSTMGR_BRGMODRST_SOC2FPGA_MASK; + } + + if (mask & RSTMGR_BRGMODRST_LWSOC2FPGA_MASK) { + noc_mask |= SYSMGR_NOC_LWH2F_MSK; + brg_mask |= RSTMGR_BRGMODRST_LWSOC2FPGA_MASK; + } + + /* s2f mask is not set, return here */ + if (!brg_mask) + return; + if (enable) { /* clear idle request to all bridges */ setbits_le32(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); + SYSMGR_SOC64_NOC_IDLEREQ_CLR, noc_mask); /* Release SOC2FPGA bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_SOC2FPGA_BRIDGES); + brg_mask); /* Poll until all idleack to 0 */ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK), 300); } else { /* set idle request to all bridges */ - writel(~0, - socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEREQ_SET); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_NOC_IDLEREQ_SET, noc_mask); /* Enable the NOC timeout */ writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */ POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLEACK) ^ - (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK), - 300); + SYSMGR_SOC64_NOC_IDLEACK) ^ noc_mask, 300); POLL_FOR_ZERO(readl(socfpga_get_sysmgr_addr() + - SYSMGR_SOC64_NOC_IDLESTATUS) ^ - (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK), + SYSMGR_SOC64_NOC_IDLESTATUS) ^ noc_mask, 300); - /* Reset all SOC2FPGA bridges (except NOR DDR scheduler & F2S) */ + /* Reset SOC2FPGA bridges */ setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST, - BRGMODRST_SOC2FPGA_BRIDGES); + brg_mask); /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } } -void socfpga_bridges_reset(int enable) +void socfpga_bridges_reset(int enable, unsigned int mask) { if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) { u64 arg = enable; @@ -233,15 +275,15 @@ void socfpga_bridges_reset(int enable) printf("Failed to %s the HPS bridges, error %d\n", enable ? "enable" : "disable", ret); } else { - socfpga_s2f_bridges_reset(enable); - socfpga_f2s_bridges_reset(enable); + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); } } -void __secure socfpga_bridges_reset_psci(int enable) +void __secure socfpga_bridges_reset_psci(int enable, unsigned int mask) { - socfpga_s2f_bridges_reset(enable); - socfpga_f2s_bridges_reset(enable); + socfpga_s2f_bridges_reset(enable, mask); + socfpga_f2s_bridges_reset(enable, mask); } /* -- 2.26.2

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[PATCH v3 0/2] tools: mkimage: cleanups + allow to create legacy image with type flat_dt
by Marc Kleine-Budde 23 Nov '22

23 Nov '22

Hello, the first patch cleans up the error message output if struct image_type_params::set_header is set, the other adds support for creating legacy images with type flat_dt. regards, Marc Changes since v2: - renamed new image type to "fdt_legacy" (suggested by Sean Anderson) Changes since v1: - introduce new image type (suggested by Sean Anderson) instead of adding new cmd line parameter

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[PATCH] spi: zynqmp_gqspi: Update tapdelay value
by Ashok Reddy Soma 23 Nov '22

23 Nov '22

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Update GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay value for Versal for frequencies above 100MHz. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)amd.com> --- drivers/spi/zynqmp_gqspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 48eff777df..83a5c8aebf 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -94,7 +94,7 @@ #define GQSPI_BAUD_DIV_SHIFT 2 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 -#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 #define GQSPI_USE_DATA_DLY 0x1 -- 2.17.1

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