November 2022 - U-Boot

Re: [PATCH 5/6] pogo_v4: Disable LTO
by Tony Dinh 23 Nov '22

23 Nov '22

Resend to include the mailing list! Tony On Tue, Nov 22, 2022 at 11:58 AM Tony Dinh <mibodhi(a)gmail.com> wrote: > > Hi Tom, > > On Tue, Nov 22, 2022 at 9:32 AM Tom Rini <trini(a)konsulko.com> wrote: > > > > With gcc-12.2 we now get: > > lib/zlib/inflate.c:360: undefined reference to `__gnu_thumb1_case_si' > > when building this platform. This seems like some odd problem with LTO > > and Thumb, but since the platform continues to link, I assume it's > > within size constraints, so lets just disable LTO for now. > > We don't have a hard size constraint for this board. Thumb and LTO > were to help keep the image 512K or less (by convention, for some > downstream scripts). > > Thanks, > Acked-by: Tony Dinh <mibodhi(a)gmail.com> > > > > > Cc: Tony Dinh <mibodhi(a)gmail.com> > > Signed-off-by: Tom Rini <trini(a)konsulko.com> > > --- > > configs/pogo_v4_defconfig | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig > > index 3b08cb7b1d14..c4b7f7c31471 100644 > > --- a/configs/pogo_v4_defconfig > > +++ b/configs/pogo_v4_defconfig > > @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4" > > CONFIG_SYS_PROMPT="Pogo_V4> " > > CONFIG_IDENT_STRING="\nPogoplug V4" > > CONFIG_SYS_LOAD_ADDR=0x800000 > > -CONFIG_LTO=y > > CONFIG_DISTRO_DEFAULTS=y > > CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y > > CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 > > -- > > 2.25.1 > >

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[PATCH 1/2] pwm: sunxi: enable pwm0 support on sun7i
by Giulio Benetti 23 Nov '22

23 Nov '22

sun7i pwm is equal to sun4i and sun5i so enable pwm0 the same way for sun7i. Signed-off-by: Giulio Benetti <giulio.benetti(a)benettiengineering.com> --- arch/arm/include/asm/arch-sunxi/pwm.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h index b89bddd2e8..1a1c6e0c54 100644 --- a/arch/arm/include/asm/arch-sunxi/pwm.h +++ b/arch/arm/include/asm/arch-sunxi/pwm.h @@ -26,7 +26,8 @@ #define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 -#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I || \ + defined CONFIG_MACH_SUN7I #define SUNXI_PWM_PIN0 SUNXI_GPB(2) #define SUNXI_PWM_MUX SUN4I_GPB_PWM #endif -- 2.34.1

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[PATCH v4 0/1] Makefile: rework u-boot-initial-env target
by Max Krummenacher 23 Nov '22

23 Nov '22

From: Max Krummenacher <max.krummenacher(a)toradex.com> With CONFIG_LTO enabled the current way of extracting the configured environment no longer works, i.e. the object file content changes due to LTO. Build a host tool which prints the configured environment instead of using objcopy and friends to achive the same. The code and Makefile changes were mostly stolen from tools/env/ i.e. the target userspace tools to access the environment. Changes in v4: - add '(objtree)/' when calling the tool. Suggested by Pali Rohár. - renamed patch, as more than just the Makefile has changes Changes in v3: - moved the tool from scripts/ to tools/. Suggested by Tom Rini - changed the dependencies to '$(env_h)' and 'tools'. Suggested by Tom Rini and Pali Rohár. - removed the sed rule which replaces \x00 with \x0A as this is already done by the tool. Suggested by Pali Rohár. Changes in v2: - reworked to build a host tool which prints the configured environment as proposed by Pali Rohár https://lore.kernel.org/u-boot/20221018174827.1393211-1-max.oss.09@gmail.co… - renamed patch, v1 used "Makefile: fix u-boot-initial-env target if lto is enabled" Max Krummenacher (1): u-boot-initial-env: rework make target Makefile | 9 +++++---- tools/.gitignore | 1 + tools/Makefile | 3 +++ tools/printinitialenv.c | 44 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 tools/printinitialenv.c -- 2.35.3

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[GIT PULL] Please pull u-boot-amlogic-20221122
by Neil Armstrong 23 Nov '22

23 Nov '22

Hi Tom, Here's changes for next release: - Implement setbrg op to meson serial device - Re-add the old PHY reset binding for nanopi-k2 The CI job is at https://source.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/14199 Thanks, Neil The following changes since commit 536c642ffef545b4b5b02d065a0c1de9785549d7: Merge tag 'efi-2023-01-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-11-22 08:30:53 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20221122 for you to fetch changes up to e0638f1d09b9e9caead4e3909e7dc8aaa41febe1: arm64: dts: meson: nanopi-k2: readd PHY reset properties (2022-11-22 18:53:21 +0100) ---------------------------------------------------------------- - Implement setbrg op to meson serial device - Re-add the old PHY reset binding for nanopi-k2 ---------------------------------------------------------------- Christian Hewitt (1): arm64: dts: meson: nanopi-k2: readd PHY reset properties Edoardo Tomelleri (1): arm: amlogic: add setbrg op to serial device arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi | 7 +++ drivers/serial/serial_meson.c | 70 +++++++++++++++++++++++++++ include/configs/meson64.h | 7 +++ 3 files changed, 84 insertions(+)

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[PATCH v2 0/2] fastboot/mach-meson: release usb_gadget on reboot commands
by Mattijs Korpershoek 23 Nov '22

23 Nov '22

When host issues "fastboot reboot fastboot", it's expected that the board drops the USB connection before resetting. On some boards, such as Khadas VIM3L and SEI610, this is not the case. We observe the following error: $ fastboot reboot fastboot Rebooting into fastboot OKAY [ 0.004s] fastboot: error: Failed to boot into userspace fastboot; one or more components might be unbootable. This does not happen when we use the RST button on the board. It can be reproduced in linux with: $ echo b > /proc/sysrq-trigger In this case, we hit a undefined hardware behavior, where D+ and D- are in an unknown state. Therefore the host can't detect usb disconnection. This series proposes 2 approaches for this problem: * generic fix, which ensures that usb_gadget_disconnect() is called when the board receives any "fastboot reboot" commands * platform specific reset implementation for g12a to ensure that the usb controller gets properly reset. Changes in v2: * Transformed into a series to provide both generic and platform specific fix (Marek) * Simplified generic fix via g_dnl_trigger_detach() (Marek) * Link to v1: https://lore.kernel.org/r/20220721135955.360195-1-mkorpershoek@baylibre.com Signed-off-by: Mattijs Korpershoek <mkorpershoek(a)baylibre.com> --- Mattijs Korpershoek (2): usb: gadget: fastboot: detach usb on reboot commands mach-meson: g12a: reset usb controller in reset_misc() arch/arm/mach-meson/board-g12a.c | 14 ++++++++++++++ cmd/fastboot.c | 2 +- configs/bananapi-m5_defconfig | 2 ++ configs/beelink-gsking-x_defconfig | 2 ++ configs/beelink-gtking_defconfig | 2 ++ configs/beelink-gtkingpro_defconfig | 2 ++ configs/khadas-vim3_android_ab_defconfig | 2 ++ configs/khadas-vim3_android_defconfig | 2 ++ configs/khadas-vim3_defconfig | 2 ++ configs/khadas-vim3l_android_ab_defconfig | 2 ++ configs/khadas-vim3l_android_defconfig | 2 ++ configs/khadas-vim3l_defconfig | 2 ++ configs/odroid-c4_defconfig | 2 ++ configs/odroid-hc4_defconfig | 2 ++ configs/odroid-n2_defconfig | 2 ++ configs/radxa-zero_defconfig | 2 ++ configs/u200_defconfig | 2 ++ drivers/usb/gadget/f_fastboot.c | 1 + 18 files changed, 46 insertions(+), 1 deletion(-) --- base-commit: 2d4591353452638132d711551fec3495b7644731 change-id: 20220728-reset-usb-controller-1b54be54b9d8 Best regards, -- Mattijs Korpershoek <mkorpershoek(a)baylibre.com>

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[PATCH] drivers: fpga: Add FPGA configuration during bootm for Intel SOCFPGA
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Yau Wai Gan <yau.wai.gan(a)intel.com> This enable the capability to automatically perform FPGA configuration when booting Linux FIT image via bootm command. The FPGA configuration bitstream shall be packed within the FIT image. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/fpga/altera.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 10c0475d25..35eb95544d 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -10,6 +10,10 @@ /* * Altera FPGA support */ +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include <asm/arch/misc.h> +#endif #include <common.h> #include <errno.h> #include <ACEX1K.h> @@ -49,6 +53,43 @@ static const struct altera_fpga { #endif }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +int fpga_is_partial_data(int devnum, size_t img_len) +{ + /* + * The FPGA data (full or partial) is checked by + * the SDM hardware, for Intel SDM Mailbox based + * devices. Hence always return full bitstream. + * + * For Cyclone V and Arria 10 family, the bitstream + * type paramater is not handled by the driver. + */ + return 0; +} + +int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, + bitstream_type bstype) +{ + int ret_val; + int flags = 0; + + ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags); + + /* + * Enable the HPS to FPGA bridges when FPGA load is completed + * successfully. This is to ensure the FPGA is accessible + * by the HPS. + */ + if (!ret_val) { + printf("Enable FPGA bridges\n"); + do_bridge_reset(1, ~0); + } + + return ret_val; +} +#endif + static int altera_validate(Altera_desc *desc, const char *fn) { if (!desc) { -- 2.26.2

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[PATCH] ddr: altera: n5x: Ensure 'cal->header.data_len' is validated
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Klocwork reported the unvalidated integer value 'cal->header.data_len' is used but this is not a issue because the proper value is calculated before assigning 'cal->header.data_len' and CRC32 is generated before saving this value into QSPI to ensure data integrity when reading this variable. Adding checking on 'cal->header.data_len' to ensure the value is valid for the sake of good coding practice. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 44 +++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 0e944b7a15..8a5f0a3df4 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -1109,8 +1109,8 @@ static void phy_ocram(phys_addr_t phy_base, phys_addr_t phy_offset, } } -static void cal_data_ocram(phys_addr_t phy_base, u32 addr, - enum data_process proc) +static int cal_data_ocram(phys_addr_t phy_base, u32 addr, + enum data_process proc) { /* * This array variable contains a list of PHY registers required for @@ -1435,6 +1435,13 @@ static void cal_data_ocram(phys_addr_t phy_base, u32 addr, cal->header.ddrconfig_hash, CHUNKSZ_PER_WD_RESET); + if (SOC64_HANDOFF_BASE < ((uintptr_t)(&cal->data) + + cal->header.data_len)) { + debug("%s: Backup cal data overflow HPS handoff\n", + __func__); + return -ENOEXEC; + } + crc32_wd_buf((u8 *)&cal->data, cal->header.data_len, (u8 *)&cal->header.caldata_crc32, CHUNKSZ_PER_WD_RESET); @@ -1443,6 +1450,8 @@ static void cal_data_ocram(phys_addr_t phy_base, u32 addr, /* Isolate the APB access from internal CSRs */ setbits_le16(phy_base + DDR_PHY_APBONLY0_OFFSET, DDR_PHY_MICROCONTMUXSEL); + + return 0; } static bool is_ddrconfig_hash_match(const void *buffer) @@ -1559,6 +1568,12 @@ static bool is_cal_bak_data_valid(void) return false; } + if (SOC64_HANDOFF_BASE < (SOC64_OCRAM_PHY_BACKUP_BASE + + cal->header.data_len + sizeof(struct cal_header_t))) { + debug("%s: Backup cal data overflow HPS handoff\n", __func__); + return false; + } + /* Load header + DDR bak cal into OCRAM buffer */ ret = request_firmware_into_buf(dev, qspi_offset, @@ -1571,6 +1586,12 @@ static bool is_cal_bak_data_valid(void) return false; } + if (SOC64_HANDOFF_BASE < ((uintptr_t)(&cal->data) + + cal->header.data_len)) { + debug("%s: Backup cal data overflow HPS handoff\n", __func__); + return false; + } + crc32_wd_buf((u8 *)&cal->data, cal->header.data_len, (u8 *)&crc32, CHUNKSZ_PER_WD_RESET); debug("%s: crc32 %x for bak calibration data from QSPI\n", __func__, @@ -1636,8 +1657,11 @@ static int init_phy(struct ddr_handoff *ddr_handoff_info, ddr_handoff_info->phy_handoff_length, ddr_handoff_info->phy_base); } else { - cal_data_ocram(ddr_handoff_info->phy_base, - SOC64_OCRAM_PHY_BACKUP_BASE, LOADING); + ret = cal_data_ocram(ddr_handoff_info->phy_base, + SOC64_OCRAM_PHY_BACKUP_BASE, LOADING); + + if (ret) + return ret; /* * Invalidate the section used for processing the PHY @@ -2955,10 +2979,14 @@ int sdram_mmr_init_full(struct udevice *dev) * Backup calibration data to OCRAM first, these data * might be permanant stored to flash in later */ - if (is_ddr_retention_enabled(reg)) - cal_data_ocram(ddr_handoff_info.phy_base, - SOC64_OCRAM_PHY_BACKUP_BASE, - STORE); + if (is_ddr_retention_enabled(reg)) { + ret = cal_data_ocram(ddr_handoff_info.phy_base, + SOC64_OCRAM_PHY_BACKUP_BASE, + STORE); + + if (ret) + return ret; + } } else { /* Updating training result to DDR controller */ -- 2.26.2

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Please pull u-boot-dm
by Simon Glass 23 Nov '22

23 Nov '22

Hi Tom, The following changes since commit 521277ec15eb794229403ec24b8c00a4ff02b0b6: Merge tag 'xilinx-for-v2023.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2022-11-22 12:33:48 -0500) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-22nov22 for you to fetch changes up to b4574c0e750bee39cc2448952f127040a37a8e0b: test: Disable part of the setexpr test for now (2022-11-22 15:14:25 -0700) ---------------------------------------------------------------- buildman /binman improvements for handling missing blobs fix for long-standing image.h warning minor fixes ---------------------------------------------------------------- Heinrich Schuchardt (1): sandbox: check lseek return value in handle_ufi_command Marek Vasut (2): cmd: fdt: Fix iteration over elements above index 1 in fdt get test: cmd: fdt: Add fdt get value test case Quentin Schulz (2): binman: bintool: remove btool_ prefix from btool names Revert "binman: btool: gzip: fix packer name so that binary can be found" Simon Glass (15): image: Correct strncpy() warning with image_set_name() Makefile: Correct the binman rule doc: Correct the path to the Makefile documentation binman: Use an exit code when blobs are missing buildman: Convert documentation to rST buildman: Drop mention of MAKEALL buildman: Update the arc toolchain buildman: Update the default settings file buildman: Drop mention of old architectures buildman: Detect binman reporting missing blobs binman: Add a separate section about environment variables buildman: Ensure config_fname is inited buildman: Reinstate removal of temp output dir in tests binman: Add documentation for the command line args test: Disable part of the setexpr test for now Sughosh Ganu (1): sandbox: Move the capsule GUID declarations to board file Tom Rini (2): global: Do not default to faking missing binaries for buildman buildman: Add --allow-missing flag to allow missing blobs .azure-pipelines.yml | 2 +- .gitlab-ci.yml | 6 +- Makefile | 15 +- board/sandbox/sandbox.c | 13 + cmd/fdt.c | 9 +- doc/build/buildman.rst | 1 + doc/build/index.rst | 1 + drivers/usb/emul/sandbox_flash.c | 10 +- include/configs/sandbox.h | 13 - include/image.h | 8 +- scripts/Kbuild.include | 2 +- test/cmd/fdt.c | 53 ++ test/cmd/setexpr.c | 6 +- tools/binman/binman.rst | 352 +++++++++++++- tools/binman/bintool.py | 3 +- tools/binman/btool/btool_gzip.py | 4 +- tools/binman/cmdline.py | 5 +- tools/binman/control.py | 9 +- tools/binman/ftest.py | 19 +- tools/buildman/README | 1349 --------------------------------------------------- tools/buildman/README.rst | 1 + tools/buildman/bsettings.py | 17 +- tools/buildman/builder.py | 5 +- tools/buildman/builderthread.py | 8 +- tools/buildman/buildman.rst | 1328 ++++++++++++++++++++++++++++++++++++++++++++++++++ tools/buildman/cmdline.py | 6 + tools/buildman/control.py | 28 +- tools/buildman/func_test.py | 112 ++++- 28 files changed, 1981 insertions(+), 1404 deletions(-) create mode 120000 doc/build/buildman.rst delete mode 100644 tools/buildman/README create mode 120000 tools/buildman/README.rst create mode 100644 tools/buildman/buildman.rst Regards, Simon

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[PATCH] ddr: altera: n5x: Ensure correct size of result for correct type casting
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Klockwork reported there is potential value overflow with incorrect typecast, but this is not valid in this arithmetic implementation because result is never over 32-bit size. The code is improved to ensure correct size of result returned with correct type casting for the sake of good coding practice. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 72c231b3f1..0e944b7a15 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2898,9 +2898,9 @@ int sdram_mmr_init_full(struct udevice *dev) * subsystem in complete reset state before init DDR clock * and DDR controller */ - ret = wait_for_bit_le32((const void *)((uintptr_t)(readl + ret = wait_for_bit_le32((const void *)((uintptr_t)readl (ddr_handoff_info.mem_reset_base) + - MEM_RST_MGR_STATUS)), + MEM_RST_MGR_STATUS), MEM_RST_MGR_STATUS_RESET_COMPLETE, true, TIMEOUT_200MS, false); if (ret) { @@ -2923,8 +2923,8 @@ int sdram_mmr_init_full(struct udevice *dev) /* Release the controller from reset */ setbits_le32((uintptr_t) - (readl(ddr_handoff_info.mem_reset_base) + - MEM_RST_MGR_STATUS), MEM_RST_MGR_STATUS_AXI_RST | + readl(ddr_handoff_info.mem_reset_base) + + MEM_RST_MGR_STATUS, MEM_RST_MGR_STATUS_AXI_RST | MEM_RST_MGR_STATUS_CONTROLLER_RST | MEM_RST_MGR_STATUS_RESET_COMPLETE); -- 2.26.2

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[PATCH] ddr: altera: n5x: Copies calibration data to DDR when DDR retention is set
by Jit Loon Lim 23 Nov '22

23 Nov '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Ensure the PHY calibration data is copied to DDR only when DDR retention is set. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/ddr/altera/sdram_n5x.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 8d28cdbc03..72c231b3f1 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -3045,10 +3045,13 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_set_firewall(&bd); - ddr_offset = simple_strtoul(offset, &endptr, 16); - if (!(offset == endptr || *endptr != '\0')) - memcpy((void *)ddr_offset, - (const void *)SOC64_OCRAM_PHY_BACKUP_BASE, SZ_4K); + if (is_ddr_retention_enabled(reg)) { + ddr_offset = simple_strtoul(offset, &endptr, 16); + if (!(offset == endptr || *endptr != '\0')) + memcpy((void *)ddr_offset, + (const void *)SOC64_OCRAM_PHY_BACKUP_BASE, + SZ_4K); + } return 0; } -- 2.26.2

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