July 2019 - U-Boot

[U-Boot] [PATCH] dm: mmc: remove unused U_BOOT_DRIVER(mmc)
by Andy Yan 27 Aug '19

27 Aug '19

From: Andy Yan <andyshrk(a)gmail.com> When look through the code, I found this bare metal drives is not used, so remove it. Signed-off-by: Andy Yan <andy.yan(a)rock-chips.com> --- drivers/mmc/mmc-uclass.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index a9c8f335c1..7e641ed5a6 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -404,10 +404,6 @@ U_BOOT_DRIVER(mmc_blk) = { }; #endif /* CONFIG_BLK */ -U_BOOT_DRIVER(mmc) = { - .name = "mmc", - .id = UCLASS_MMC, -}; UCLASS_DRIVER(mmc) = { .id = UCLASS_MMC, -- 2.17.1

3 2

[U-Boot] [PATCH 00/47] powerpc: Enable PCIe DM drvier for some platforms
by Hou Zhiqiang 27 Aug '19

27 Aug '19

Enable PCIe DM driver for some PowerPC platforms which has supported device tree. Depends on the following 2 series: http://patchwork.ozlabs.org/project/uboot/list/?series=120960 http://patchwork.ozlabs.org/project/uboot/list/?series=115008 Hou Zhiqiang (47): powerpc: T208xRDB: Compile legacy PCIe routines conditionally powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T2080RDB: Enable PCIe driver powerpc: T4RDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T4240 PCIe support t4240: dts: Added PCIe DT nodes powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T4240RDB: Enable PCIe driver powerpc: T102xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T102x PCIe support t102x: dts: Added PCIe DT nodes powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040 powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1024RDB: Enable PCIe driver powerpc: T104xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T104x PCIe support t104x: dts: Added PCIe DT nodes powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1042D4RDB: Enable PCIe driver powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs P1020: dts: Added PCIe DT nodes powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled configs: P1020RDB: Enable PCIe driver P2020: dts: Added PCIe DT nodes configs: P2020RDB: Enable PCIe driver powerpc: p_corenet: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add P2041 PCIe support P2041: dts: Added PCIe DT nodes powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: P2041RDB: Enable PCIe driver dm: pcie_fsl: Add P3041 PCIe support P3041: dts: Added PCIe DT nodes powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled configs: P3041DS: Enable PCIe driver dm: pcie_fsl: Add P4080 PCIe support P4080: dts: Added PCIe DT nodes configs: P4080DS: Enable PCIe driver dm: pcie_fsl: Add P5040 PCIe support P5040: dts: Added PCIe DT nodes configs: P5040DS: Enable PCIe driver powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected dm: pcie_fsl: Add MPC8548 PCIe support MPC8548: dts: Added PCIe DT node powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled configs: MPC8548CDS: Enable PCIe driver arch/powerpc/dts/mpc8548-post.dtsi | 9 ++++ arch/powerpc/dts/mpc8548cds.dts | 6 +++ arch/powerpc/dts/mpc8548cds_36b.dts | 6 +++ arch/powerpc/dts/p1020-post.dtsi | 20 +++++++ arch/powerpc/dts/p1020rdb-pc.dts | 12 +++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 +++++ arch/powerpc/dts/p1020rdb-pd.dts | 12 +++++ arch/powerpc/dts/p2020-post.dtsi | 30 +++++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 17 ++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 ++++++ arch/powerpc/dts/p2041.dtsi | 36 +++++++++++++ arch/powerpc/dts/p3041.dtsi | 48 +++++++++++++++++ arch/powerpc/dts/p4080.dtsi | 36 +++++++++++++ arch/powerpc/dts/p5040.dtsi | 36 +++++++++++++ arch/powerpc/dts/t102x.dtsi | 36 +++++++++++++ arch/powerpc/dts/t104x.dtsi | 48 +++++++++++++++++ arch/powerpc/dts/t4240.dtsi | 48 +++++++++++++++++ board/freescale/common/cds_pci_ft.c | 4 +- board/freescale/common/p_corenet/pci.c | 2 + board/freescale/mpc8548cds/mpc8548cds.c | 6 ++- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +- board/freescale/t102xrdb/pci.c | 2 + board/freescale/t104xrdb/pci.c | 2 + board/freescale/t208xrdb/pci.c | 2 + board/freescale/t4rdb/pci.c | 2 + configs/MPC8548CDS_36BIT_defconfig | 4 ++ configs/MPC8548CDS_defconfig | 4 ++ configs/MPC8548CDS_legacy_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++ configs/P1020RDB-PC_36BIT_defconfig | 4 ++ configs/P1020RDB-PC_NAND_defconfig | 4 ++ configs/P1020RDB-PC_SDCARD_defconfig | 4 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 4 ++ configs/P1020RDB-PC_defconfig | 4 ++ configs/P1020RDB-PD_NAND_defconfig | 4 ++ configs/P1020RDB-PD_SDCARD_defconfig | 4 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 4 ++ configs/P1020RDB-PD_defconfig | 4 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++ configs/P2020RDB-PC_36BIT_defconfig | 4 ++ configs/P2020RDB-PC_NAND_defconfig | 4 ++ configs/P2020RDB-PC_SDCARD_defconfig | 4 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 4 ++ configs/P2020RDB-PC_defconfig | 4 ++ configs/P2041RDB_NAND_defconfig | 4 ++ configs/P2041RDB_SDCARD_defconfig | 4 ++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++ configs/P2041RDB_defconfig | 4 ++ configs/P3041DS_NAND_defconfig | 4 ++ configs/P3041DS_SDCARD_defconfig | 4 ++ configs/P3041DS_SPIFLASH_defconfig | 4 ++ configs/P3041DS_defconfig | 4 ++ configs/P4080DS_SDCARD_defconfig | 4 ++ configs/P4080DS_SPIFLASH_defconfig | 4 ++ configs/P4080DS_defconfig | 4 ++ configs/P5040DS_NAND_defconfig | 4 ++ configs/P5040DS_SDCARD_defconfig | 4 ++ configs/P5040DS_SPIFLASH_defconfig | 4 ++ configs/P5040DS_defconfig | 4 ++ configs/T1024RDB_NAND_defconfig | 4 ++ configs/T1024RDB_SDCARD_defconfig | 4 ++ configs/T1024RDB_SPIFLASH_defconfig | 4 ++ configs/T1024RDB_defconfig | 4 ++ configs/T1042D4RDB_NAND_defconfig | 4 ++ configs/T1042D4RDB_SDCARD_defconfig | 4 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 4 ++ configs/T1042D4RDB_defconfig | 4 ++ configs/T2080RDB_NAND_defconfig | 4 ++ configs/T2080RDB_SDCARD_defconfig | 4 ++ configs/T2080RDB_SPIFLASH_defconfig | 4 ++ configs/T2080RDB_defconfig | 4 ++ configs/T4240RDB_SDCARD_defconfig | 4 ++ configs/T4240RDB_defconfig | 4 ++ drivers/pci/pcie_fsl.c | 21 ++++++++ include/configs/MPC8548CDS.h | 22 +++++--- include/configs/P2041RDB.h | 55 ++++++-------------- include/configs/T102xRDB.h | 78 ++++++---------------------- include/configs/T104xRDB.h | 38 +++++++------- include/configs/T208xRDB.h | 36 +++++++------ include/configs/T4240RDB.h | 35 +++++++------ include/configs/corenet_ds.h | 63 +++++++--------------- include/configs/p1_p2_rdb_pc.h | 36 ++++++++----- 86 files changed, 822 insertions(+), 223 deletions(-) -- 2.9.5

3 113

[U-Boot] [PATCH] rtc: stm32: manage 2 digit limitation on year
by Patrick Delaunay 26 Aug '19

26 Aug '19

STM32 RTC manages only 2 digits for YEAR (Year tens and units in BCD format in RTC_DR register). With this patch, RTC driver assumes that tm->tm_years is between 2000 and 2099; tm->tm_year - 2000 have only 2 digit (0 > and <= 99). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- drivers/rtc/stm32_rtc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/stm32_rtc.c b/drivers/rtc/stm32_rtc.c index abd3390..2674714 100644 --- a/drivers/rtc/stm32_rtc.c +++ b/drivers/rtc/stm32_rtc.c @@ -72,7 +72,8 @@ static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm) tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT); tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT); - tm->tm_year = bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT); + tm->tm_year = 2000 + + bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT); tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT); tm->tm_yday = 0; tm->tm_isdst = 0; @@ -174,6 +175,9 @@ static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm) tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec); + if (tm->tm_year < 2000 || tm->tm_year > 2099) + return -EINVAL; + /* Time in BCD format */ t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC; t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN; @@ -182,7 +186,8 @@ static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm) /* Date in BCD format */ d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE; d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH; - d |= (bin2bcd(tm->tm_year) << STM32_RTC_YEAR_SHIFT) & STM32_RTC_YEAR; + d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) & + STM32_RTC_YEAR; d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY; return stm32_rtc_set_time(dev, t, d); -- 2.7.4

2 1

[U-Boot] [PATCH v2] mmc: sti_sdhci: Fix sdhci_setup_cfg() call.
by Patrice Chotard 26 Aug '19

26 Aug '19

host->mmc, host->mmc->dev and host->mmc->priv must be set before calling sdhci_setup_cfg() to avoid hang during mmc initialization. Thanks to commit 3d296365e4e8 ("mmc: sdhci: Add support for sdhci-caps-mask") which put this issue into evidence. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- Changes in v2: - move host->mmc->priv initialization before sdhci_setup_cfg() call drivers/mmc/sti_sdhci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 8ed47e113d..d6c75ea601 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -97,14 +97,14 @@ static int sti_sdhci_probe(struct udevice *dev) SDHCI_QUIRK_NO_HISPD_BIT; host->host_caps = MMC_MODE_DDR_52MHz; + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000); if (ret) return ret; - host->mmc = &plat->mmc; - host->mmc->priv = host; - host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); -- 2.17.1

3 2

[U-Boot] [PATCH] ARM: dts: stih410-b2260: Sync DT with kernel v5.2
by Patrice Chotard 26 Aug '19

26 Aug '19

Synchronize U-boot DT with kernel v5.2 for stih410-b2260. Update stih410-b2260-u-boot.dtsi accordingly. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- arch/arm/dts/stih407-clock.dtsi | 113 ++++++------ arch/arm/dts/stih407-family.dtsi | 200 ++++++++++++---------- arch/arm/dts/stih407-pinctrl.dtsi | 129 +++++--------- arch/arm/dts/stih410-b2260-u-boot.dtsi | 17 ++ arch/arm/dts/stih410-b2260.dts | 128 +++++++------- arch/arm/dts/stih410-clock.dtsi | 110 ++++++------ arch/arm/dts/stih410-pinctrl.dtsi | 7 +- arch/arm/dts/stih410.dtsi | 227 ++++--------------------- 8 files changed, 370 insertions(+), 561 deletions(-) diff --git a/arch/arm/dts/stih407-clock.dtsi b/arch/arm/dts/stih407-clock.dtsi index 13029c03d7..1ab40db7c9 100644 --- a/arch/arm/dts/stih407-clock.dtsi +++ b/arch/arm/dts/stih407-clock.dtsi @@ -1,38 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/stih407-clks.h> / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; ranges; - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - /* * A9 PLL. */ @@ -62,35 +53,22 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; - }; - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -101,6 +79,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-a0-pll-ofd-0"; + clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */ }; clk_s_a0_flexgen: clk-s-a0-flexgen { @@ -112,6 +91,7 @@ <&clk_sysin>; clock-output-names = "clk-ic-lmi0"; + clock-critical = <CLK_IC_LMI0>; }; }; @@ -126,9 +106,10 @@ "clk-s-c0-fs0-ch1", "clk-s-c0-fs0-ch2", "clk-s-c0-fs0-ch3"; + clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -139,6 +120,7 @@ clocks = <&clk_sysin>; clock-output-names = "clk-s-c0-pll0-odf-0"; + clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */ }; clk_s_c0_pll1: clk-s-c0-pll1 { @@ -194,6 +176,27 @@ "clk-main-disp", "clk-aux-disp", "clk-compo-dvp"; + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, + <CLK_TX_ICN_DMU>, + <CLK_EXT2F_A9>, + <CLK_ICN_LMI>, + <CLK_ICN_SBC>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -210,7 +213,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; @@ -244,13 +247,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; diff --git a/arch/arm/dts/stih407-family.dtsi b/arch/arm/dts/stih407-family.dtsi index 6c6de58029..7c36c37260 100644 --- a/arch/arm/dts/stih407-family.dtsi +++ b/arch/arm/dts/stih407-family.dtsi @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Giuseppe Cavallaro <peppe.cavallaro(a)st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "stih407-pinctrl.dtsi" #include <dt-bindings/mfd/st-lpc.h> @@ -20,7 +17,13 @@ #size-cells = <1>; ranges; - dmu_reserved: rproc@44000000 { + gp0_reserved: rproc@45000000 { + compatible = "shared-dma-pool"; + reg = <0x45000000 0x00400000>; + no-map; + }; + + delta_reserved: rproc@44000000 { compatible = "shared-dma-pool"; reg = <0x44000000 0x01000000>; no-map; @@ -47,6 +50,7 @@ clocks = <&clk_m_a9>; clock-names = "cpu"; clock-latency = <100000>; + cpu0-supply = <&pwm_regulator>; st,syscfg = <&syscfg_core 0x8e0>; }; cpu@1 { @@ -65,19 +69,19 @@ }; }; - intc: interrupt-controller@08761000 { + intc: interrupt-controller@8761000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x08761000 0x1000>, <0x08760100 0x100>; }; - scu@08760000 { + scu@8760000 { compatible = "arm,cortex-a9-scu"; reg = <0x08760000 0x1000>; }; - timer@08760200 { + timer@8760200 { interrupt-parent = <&intc>; compatible = "arm,cortex-a9-global-timer"; reg = <0x08760200 0x100>; @@ -85,7 +89,7 @@ clocks = <&arm_periph_clk>; }; - l2: cache-controller { + l2: cache-controller@8762000 { compatible = "arm,pl310-cache"; reg = <0x08762000 0x1000>; arm,data-latency = <3 3 3>; @@ -118,24 +122,28 @@ ranges; compatible = "simple-bus"; - restart { + restart: restart-controller@0 { compatible = "st,stih407-restart"; + reg = <0 0>; st,syscfg = <&syscfg_sbc_reg>; status = "okay"; }; - powerdown: powerdown-controller { + powerdown: powerdown-controller@0 { compatible = "st,stih407-powerdown"; + reg = <0 0>; #reset-cells = <1>; }; - softreset: softreset-controller { + softreset: softreset-controller@0 { compatible = "st,stih407-softreset"; + reg = <0 0>; #reset-cells = <1>; }; - picophyreset: picophyreset-controller { + picophyreset: picophyreset-controller@0 { compatible = "st,stih407-picophyreset"; + reg = <0 0>; #reset-cells = <1>; }; @@ -167,6 +175,13 @@ syscfg_core: core-syscfg@92b0000 { compatible = "st,stih407-core-syscfg", "syscon"; reg = <0x92b0000 0x1000>; + + sti_sasg_codec: sti-sasg-codec { + compatible = "st,stih407-sas-codec"; + #sound-dai-cells = <1>; + status = "disabled"; + st,syscfg = <&syscfg_core>; + }; }; syscfg_lpm: lpm-syscfg@94b5100 { @@ -174,8 +189,9 @@ reg = <0x94b5100 0x1000>; }; - irq-syscfg { + irq-syscfg@0 { compatible = "st,stih407-irq-syscfg"; + reg = <0 0>; st,syscfg = <&syscfg_core>; st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, <ST_IRQ_SYSCFG_PMU_1>; @@ -187,22 +203,21 @@ vtg_main: sti-vtg-main@8d02800 { compatible = "st,vtg"; reg = <0x8d02800 0x200>; - interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; }; vtg_aux: sti-vtg-aux@8d00200 { compatible = "st,vtg"; reg = <0x8d00200 0x100>; - interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; }; serial@9830000 { compatible = "st,asc"; reg = <0x9830000 0x2c>; - interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_serial0>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; + /* Pinctrl moved out to a per-board configuration */ status = "disabled"; }; @@ -210,7 +225,7 @@ serial@9831000 { compatible = "st,asc"; reg = <0x9831000 0x2c>; - interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial1>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; @@ -221,7 +236,7 @@ serial@9832000 { compatible = "st,asc"; reg = <0x9832000 0x2c>; - interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; @@ -233,7 +248,7 @@ sbc_serial0: serial@9530000 { compatible = "st,asc"; reg = <0x9530000 0x2c>; - interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial0>; clocks = <&clk_sysin>; @@ -244,7 +259,7 @@ serial@9531000 { compatible = "st,asc"; reg = <0x9531000 0x2c>; - interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&clk_sysin>; @@ -374,8 +389,9 @@ status = "disabled"; }; - usb2_picophy0: phy1 { + usb2_picophy0: phy1@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0x100 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -383,12 +399,13 @@ reset-names = "global", "port"; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { compatible = "st,miphy28lp-phy"; st,syscfg = <&syscfg_core>; #address-cells = <1>; #size-cells = <1>; ranges; + reg = <0 0>; phy_port0: port@9b22000 { reg = <0x9b22000 0xff>, @@ -458,6 +475,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -470,6 +489,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -482,6 +503,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi3_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -494,6 +517,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -507,6 +532,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi10_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -519,6 +546,8 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi11_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -531,16 +560,18 @@ clock-names = "ssc"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi12_default>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09060000 0x7ff>, <0x9061008 0x20>; reg-names = "mmc", "top-mmc-delay"; - interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mmcirq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0>; @@ -550,12 +581,12 @@ bus-width = <8>; }; - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { compatible = "st,sdhci-stih407", "st,sdhci"; status = "disabled"; reg = <0x09080000 0x7ff>; reg-names = "mmc"; - interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mmcirq"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd1>; @@ -563,7 +594,6 @@ clocks = <&clk_s_c0_flexgen CLK_MMC_1>, <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; resets = <&softreset STIH407_MMC1_SOFTRESET>; - reset-names = "softreset"; bus-width = <4>; }; @@ -590,7 +620,7 @@ compatible = "st,ahci"; reg = <0x9b20000 0x1000>; - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hostc"; phys = <&phy_port0 PHY_TYPE_SATA>; @@ -613,7 +643,7 @@ compatible = "st,ahci"; reg = <0x9b28000 0x1000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hostc"; phys = <&phy_port1 PHY_TYPE_SATA>; @@ -654,11 +684,12 @@ dwc3: dwc3@9900000 { compatible = "snps,dwc3"; reg = <0x09900000 0x100000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; - dr_mode = "peripheral"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; phy-names = "usb2-phy", "usb3-phy"; phys = <&usb2_picophy0>, <&phy_port2 PHY_TYPE_USB3>; + snps,dis_u3_susphy_quirk; }; }; @@ -667,7 +698,7 @@ compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9810000 0x68>; - interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default>; clock-names = "pwm"; @@ -682,6 +713,7 @@ compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9510000 0x68>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1_chan0_default &pinctrl_pwm1_chan1_default @@ -694,14 +726,14 @@ status = "disabled"; }; - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; @@ -720,8 +752,8 @@ resets = <&softreset STIH407_ETH1_SOFTRESET>; reset-names = "stmmaceth"; - interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, - <GIC_SPI 99 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq", "eth_wake_irq"; /* DMA Bus Mode */ @@ -735,26 +767,14 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - cec: sti-cec@094a087c { - compatible = "st,stih-cec"; - reg = <0x94a087c 0x64>; - clocks = <&clk_sysin>; - clock-names = "cec-clk"; - interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>; - interrupt-names = "cec-irq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cec0_default>; - resets = <&softreset STIH407_LPM_SOFTRESET>; - }; - - rng10: rng@08a89000 { + rng10: rng@8a89000 { compatible = "st,rng"; reg = <0x08a89000 0x1000>; clocks = <&clk_sysin>; status = "okay"; }; - rng11: rng@08a8a000 { + rng11: rng@8a8a000 { compatible = "st,rng"; reg = <0x08a8a000 0x1000>; clocks = <&clk_sysin>; @@ -764,7 +784,7 @@ mailbox0: mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; mbox-name = "a9"; status = "okay"; @@ -794,9 +814,24 @@ status = "okay"; }; - st231_delta: st231-delta@44000000 { + st231_gp0: st231-gp0@0 { compatible = "st,st231-rproc"; - memory-region = <&dmu_reserved>; + reg = <0 0>; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; + }; + + st231_delta: st231-delta@0 { + compatible = "st,st231-rproc"; + reg = <0 0>; + memory-region = <&delta_reserved>; resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; reset-names = "sw_reset"; clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; @@ -819,7 +854,7 @@ <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <3>; }; @@ -837,9 +872,11 @@ <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; - interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <3>; + + status = "disabled"; }; /* fdma free running */ @@ -850,20 +887,15 @@ <0x8e77000 0x1000>, <0x8e78000 0x8000>; reg-names = "slimcore", "dmem", "peripherals", "imem"; - interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; dma-channels = <16>; #dma-cells = <3>; clocks = <&clk_s_c0_flexgen CLK_FDMA>, <&clk_s_c0_flexgen CLK_EXT2F_A9>, <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; - }; - sti_sasg_codec: sti-sasg-codec { - compatible = "st,stih407-sas-codec"; - #sound-dai-cells = <1>; status = "disabled"; - st,syscfg = <&syscfg_core>; }; sti_uni_player0: sti-uni-player@8d80000 { @@ -875,7 +907,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; assigned-clock-rates = <50000000>; reg = <0x8d80000 0x158>; - interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 2 0 1>; dma-names = "tx"; @@ -891,7 +923,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; assigned-clock-rates = <50000000>; reg = <0x8d81000 0x158>; - interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 3 0 1>; dma-names = "tx"; @@ -907,7 +939,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; assigned-clock-rates = <50000000>; reg = <0x8d82000 0x158>; - interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 4 0 1>; dma-names = "tx"; @@ -923,7 +955,7 @@ assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; assigned-clock-rates = <50000000>; reg = <0x8d85000 0x158>; - interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 7 0 1>; dma-names = "tx"; @@ -935,7 +967,7 @@ #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d83000 0x158>; - interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 5 0 1>; dma-names = "rx"; @@ -947,32 +979,22 @@ #sound-dai-cells = <0>; st,syscfg = <&syscfg_core>; reg = <0x8d84000 0x158>; - interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; dmas = <&fdma0 6 0 1>; dma-names = "rx"; status = "disabled"; }; - rc: rc@09518000 { - compatible = "st,comms-irb"; - reg = <0x09518000 0x234>; - interrupts = <GIC_SPI 132 IRQ_TYPE_NONE>; - rx-mode = "infrared"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir - &pinctrl_uhf - &pinctrl_tx - &pinctrl_tx_od>; - clocks = <&clk_sysin>; - resets = <&softreset STIH407_IRB_SOFTRESET>; - - status = "disabled"; - }; - - socinfo { - compatible = "st,stih407-socinfo"; - st,syscfg = <&syscfg_core>; + delta0@0 { + compatible = "st,st-delta"; + reg = <0 0>; + clock-names = "delta", + "delta-st231", + "delta-flash-promip"; + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; }; }; }; diff --git a/arch/arm/dts/stih407-pinctrl.dtsi b/arch/arm/dts/stih407-pinctrl.dtsi index f27ae21f67..2cf335714c 100644 --- a/arch/arm/dts/stih407-pinctrl.dtsi +++ b/arch/arm/dts/stih407-pinctrl.dtsi @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Giuseppe Cavallaro <peppe.cavallaro(a)st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "st-pincfg.h" #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -45,18 +42,18 @@ }; soc { - pin-controller-sbc { + pin-controller-sbc@961f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-sbc-pinctrl"; st,syscfg = <&syscfg_sbc>; reg = <0x0961f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09610000 0x6000>; - pio0: gpio@09610000 { + pio0: gpio@9610000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -64,7 +61,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO0"; }; - pio1: gpio@09611000 { + pio1: gpio@9611000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -72,7 +69,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - pio2: gpio@09612000 { + pio2: gpio@9612000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -80,7 +77,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - pio3: gpio@09613000 { + pio3: gpio@9613000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -88,7 +85,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - pio4: gpio@09614000 { + pio4: gpio@9614000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -97,7 +94,7 @@ st,bank-name = "PIO4"; }; - pio5: gpio@09615000 { + pio5: gpio@9615000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -369,18 +366,18 @@ }; }; - pin-controller-front0 { + pin-controller-front0@920f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-front-pinctrl"; st,syscfg = <&syscfg_front>; reg = <0x0920f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09200000 0x10000>; - pio10: pio@09200000 { + pio10: pio@9200000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -388,7 +385,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO10"; }; - pio11: pio@09201000 { + pio11: pio@9201000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -396,7 +393,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO11"; }; - pio12: pio@09202000 { + pio12: pio@9202000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -404,7 +401,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO12"; }; - pio13: pio@09203000 { + pio13: pio@9203000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -412,7 +409,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO13"; }; - pio14: pio@09204000 { + pio14: pio@9204000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -420,7 +417,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO14"; }; - pio15: pio@09205000 { + pio15: pio@9205000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -428,7 +425,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO15"; }; - pio16: pio@09206000 { + pio16: pio@9206000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -436,7 +433,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO16"; }; - pio17: pio@09207000 { + pio17: pio@9207000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -444,7 +441,7 @@ reg = <0x7000 0x100>; st,bank-name = "PIO17"; }; - pio18: pio@09208000 { + pio18: pio@9208000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -452,7 +449,7 @@ reg = <0x8000 0x100>; st,bank-name = "PIO18"; }; - pio19: pio@09209000 { + pio19: pio@9209000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -465,19 +462,16 @@ serial0 { pinctrl_serial0: serial0-0 { st,pins { - tx = <&pio17 0 ALT1 OUT>; - rx = <&pio17 1 ALT1 IN>; + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; }; }; - pinctrl_serial0_rts: serial0_rts { - st,pins { - rts = <&pio17 3 ALT1 OUT>; - }; - }; - - pinctrl_serial0_cts: serial0_cts { + pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl { st,pins { + tx = <&pio17 0 ALT1 OUT>; + rx = <&pio17 1 ALT1 IN>; cts = <&pio17 2 ALT1 IN>; + rts = <&pio17 3 ALT1 OUT>; }; }; }; @@ -932,18 +926,18 @@ }; }; - pin-controller-front1 { + pin-controller-front1@921f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-front-pinctrl"; st,syscfg = <&syscfg_front>; reg = <0x0921f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09210000 0x10000>; - pio20: pio@09210000 { + pio20: pio@9210000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -965,18 +959,18 @@ }; }; - pin-controller-rear { + pin-controller-rear@922f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-rear-pinctrl"; st,syscfg = <&syscfg_rear>; reg = <0x0922f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irqmux"; ranges = <0 0x09220000 0x6000>; - pio30: gpio@09220000 { + pio30: gpio@9220000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -984,7 +978,7 @@ reg = <0x0 0x100>; st,bank-name = "PIO30"; }; - pio31: gpio@09221000 { + pio31: gpio@9221000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -992,7 +986,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO31"; }; - pio32: gpio@09222000 { + pio32: gpio@9222000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1000,7 +994,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO32"; }; - pio33: gpio@09223000 { + pio33: gpio@9223000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1008,7 +1002,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO33"; }; - pio34: gpio@09224000 { + pio34: gpio@9224000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1016,7 +1010,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO34"; }; - pio35: gpio@09225000 { + pio35: gpio@9225000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1026,41 +1020,6 @@ st,retime-pin-mask = <0x7f>; }; - dvo { - pinctrl_dvo: dvo { - st,pins { - hs = <&pio30 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - vs = <&pio30 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - de = <&pio30 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - ck = <&pio30 3 ALT2 (OE | CLKNOTDATA) 0>; - d0 = <&pio30 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d1 = <&pio30 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d2 = <&pio30 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d3 = <&pio30 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d4 = <&pio31 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d5 = <&pio31 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d6 = <&pio31 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d7 = <&pio31 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d8 = <&pio31 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d9 = <&pio31 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d10 = <&pio31 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d11 = <&pio31 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d12 = <&pio32 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d13 = <&pio32 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d14 = <&pio32 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d15 = <&pio32 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d16 = <&pio32 4 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d17 = <&pio32 5 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d18 = <&pio32 6 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d19 = <&pio32 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d20 = <&pio33 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d21 = <&pio33 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d22 = <&pio33 2 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - d23 = <&pio33 3 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - }; - }; - }; - i2c4 { pinctrl_i2c4_default: i2c4-default { st,pins { @@ -1195,18 +1154,18 @@ }; }; - pin-controller-flash { + pin-controller-flash@923f080 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stih407-flash-pinctrl"; st,syscfg = <&syscfg_flash>; reg = <0x0923f080 0x4>; reg-names = "irqmux"; - interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>; - interrupts-names = "irqmux"; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irqmux"; ranges = <0 0x09230000 0x3000>; - pio40: gpio@09230000 { + pio40: gpio@9230000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1214,7 +1173,7 @@ reg = <0 0x100>; st,bank-name = "PIO40"; }; - pio41: gpio@09231000 { + pio41: gpio@9231000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1222,7 +1181,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO41"; }; - pio42: gpio@09232000 { + pio42: gpio@9232000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi index 83916319fc..897c42146a 100644 --- a/arch/arm/dts/stih410-b2260-u-boot.dtsi +++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi @@ -9,8 +9,25 @@ soc { st_dwc3: dwc3@8f94000 { dwc3: dwc3@9900000 { + dr_mode = "peripheral"; phys = <&usb2_picophy0>; }; }; + + ohci0: usb@9a03c00 { + compatible = "generic-ohci"; + }; + + ehci0: usb@9a03e00 { + compatible = "generic-ehci"; + }; + + ohci1: usb@9a83c00 { + compatible = "generic-ohci"; + }; + + ehci1: usb@9a83e00 { + compatible = "generic-ehci"; + }; }; }; diff --git a/arch/arm/dts/stih410-b2260.dts b/arch/arm/dts/stih410-b2260.dts index 54250e2518..4fbd8e9eb5 100644 --- a/arch/arm/dts/stih410-b2260.dts +++ b/arch/arm/dts/stih410-b2260.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2016 STMicroelectronics (R&D) Limited. * Author: Patrice Chotard <patrice.chotard(a)st.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ /dts-v1/; #include "stih410.dtsi" @@ -15,68 +12,79 @@ compatible = "st,stih410-b2260", "st,stih410"; chosen { - bootargs = "console=ttyAS1,115200"; - linux,stdout-path = &uart1; + bootargs = "clk_ignore_unused"; stdout-path = &uart1; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; aliases { - ttyAS1 = &uart1; + serial1 = &uart1; ethernet0 = &ethernet0; }; - soc { - - leds { - compatible = "gpio-leds"; - user_green_1 { - label = "User_green_1"; - gpios = <&pio1 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; + leds { + compatible = "gpio-leds"; + user_green_1 { + label = "User_green_1"; + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; - user_green_2 { - label = "User_green_2"; - gpios = <&pio4 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_2 { + label = "User_green_2"; + gpios = <&pio4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; - user_green_3 { - label = "User_green_3"; - gpios = <&pio2 1 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_3 { + label = "User_green_3"; + gpios = <&pio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; - user_green_4 { - label = "User_green_4"; - gpios = <&pio2 5 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + user_green_4 { + label = "User_green_4"; + gpios = <&pio2 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; - wifi_yellow { - label = "Wifi_yellow"; - gpios = <&pio4 0 GPIO_ACTIVE_LOW>; - linux,default-trigger = "wifi-activity"; - default-state = "off"; + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "STI-B2260"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + /* DAC */ + format = "i2s"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player0>; }; - bt_blue { - label = "Bluetooth_blue"; - gpios = <&pio3 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "hci0-power"; - default-state = "off"; + codec { + sound-dai = <&sti_hdmi>; }; }; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { label = "LS-UART0"; + pinctrl-names = "default", "no-hw-flowctrl"; + pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>; + pinctrl-1 = <&pinctrl_serial0>; + rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -119,14 +127,14 @@ status = "okay"; }; - mmc0: sdhci@09060000 { + mmc0: sdhci@9060000 { pinctrl-0 = <&pinctrl_sd0>; bus-width = <4>; status = "okay"; }; /* high speed expansion connector */ - mmc1: sdhci@09080000 { + mmc1: sdhci@9080000 { status = "okay"; }; @@ -138,11 +146,11 @@ status = "okay"; }; - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { status = "okay"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { status = "okay"; }; @@ -183,17 +191,17 @@ sti_uni_player0: sti-uni-player@8d80000 { status = "okay"; }; - /* SSC11 to HDMI */ hdmiddc: i2c@9541000 { /* HDMI V1.3a supports Standard mode only */ clock-frequency = <100000>; st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <1>; + st,i2c-min-sda-pulse-width-us = <5>; status = "okay"; }; - miphy28lp_phy: miphy28lp@9b22000 { + miphy28lp_phy: miphy28lp@0 { + phy_port1: port@9b2a000 { st,osc-force-ext; }; @@ -202,25 +210,5 @@ sata1: sata@9b28000 { status = "okay"; }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2260"; - status = "okay"; - - simple-audio-card,dai-link@0 { - /* DAC */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - }; - }; }; diff --git a/arch/arm/dts/stih410-clock.dtsi b/arch/arm/dts/stih410-clock.dtsi index 8598effd6c..81a8c25d7b 100644 --- a/arch/arm/dts/stih410-clock.dtsi +++ b/arch/arm/dts/stih410-clock.dtsi @@ -1,12 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics R&D Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <dt-bindings/clock/stih410-clks.h> / { + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -14,27 +27,6 @@ compatible = "st,stih410-clk", "simple-bus"; - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - clock-output-names = "CLK_SYSIN"; - }; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - /* * A9 PLL. */ @@ -64,35 +56,19 @@ <&clockgen_a9_pll 0>, <&clk_s_c0_flexgen 13>, <&clk_m_a9_ext2f_div2>; + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - - /* - * Bootloader initialized system infrastructure clock for - * serial devices. - */ - clk_ext2f_a9: clockgen-c0@13 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - clock-output-names = "clk-s-icn-reg-0"; - }; - - clockgen-a@090ff000 { + clockgen-a@90ff000 { compatible = "st,clkgen-c32"; reg = <0x90ff000 0x1000>; @@ -134,7 +110,7 @@ clock-critical = <0>; /* clk-s-c0-fs0-ch0 */ }; - clk_s_c0: clockgen-c@09103000 { + clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -208,11 +184,27 @@ "clk-clust-hades", "clk-hwpe-hades", "clk-fc-hades"; - clock-critical = <CLK_ICN_CPU>, + clock-critical = <CLK_PROC_STFE>, + <CLK_ICN_CPU>, <CLK_TX_ICN_DMU>, <CLK_EXT2F_A9>, <CLK_ICN_LMI>, <CLK_ICN_SBC>; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -229,7 +221,7 @@ "clk-s-d0-fs0-ch3"; }; - clockgen-d0@09104000 { + clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; @@ -265,13 +257,7 @@ "clk-s-d2-fs0-ch3"; }; - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clockgen-d2@x9106000 { + clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; diff --git a/arch/arm/dts/stih410-pinctrl.dtsi b/arch/arm/dts/stih410-pinctrl.dtsi index b3e9dfc81c..e6eadd1244 100644 --- a/arch/arm/dts/stih410-pinctrl.dtsi +++ b/arch/arm/dts/stih410-pinctrl.dtsi @@ -1,16 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Peter Griffin <peter.griffin(a)linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "st-pincfg.h" / { soc { - pin-controller-rear { + pin-controller-rear@922f080 { usb0 { pinctrl_usb0: usb2-0 { diff --git a/arch/arm/dts/stih410.dtsi b/arch/arm/dts/stih410.dtsi index b59b110989..6d847019c5 100644 --- a/arch/arm/dts/stih410.dtsi +++ b/arch/arm/dts/stih410.dtsi @@ -1,67 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 STMicroelectronics Limited. * Author: Peter Griffin <peter.griffin(a)linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. */ #include "stih410-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> / { aliases { bdisp0 = &bdisp0; }; - cpus { - cpu@0 { - st,syscfg = <&syscfg_core 0x8e0>; - st,syscfg-eng = <&syscfg_opp 0x4 0x0>; - clocks = <&clk_m_a9>; - operating-points-v2 = <&cpu0_opp_table>; - }; - cpu@1 { - clocks = <&clk_m_a9>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; - - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp@1500000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <1500000000>; - clock-latency-ns = <10000000>; - opp-suspend; - }; - opp@1200000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <1200000000>; - clock-latency-ns = <10000000>; - }; - opp@800000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <800000000>; - clock-latency-ns = <10000000>; - }; - opp@400000000 { - opp-supported-hw = <0xffffffff 0xffffffff 0xffffffff>; - opp-hz = /bits/ 64 <400000000>; - clock-latency-ns = <10000000>; - }; - }; - soc { - syscfg_opp: @08a6583c { - compatible = "syscon"; - reg = <0x08a6583c 0x8>; - }; - - usb2_picophy1: phy2 { + usb2_picophy1: phy2@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xf8 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -71,8 +25,9 @@ status = "disabled"; }; - usb2_picophy2: phy3 { + usb2_picophy2: phy3@0 { compatible = "st,stih407-usb2-phy"; + reg = <0 0>; #phy-cells = <0>; st,syscfg = <&syscfg_core 0xfc 0xf4>; resets = <&softreset STIH407_PICOPHY_SOFTRESET>, @@ -83,15 +38,14 @@ }; ohci0: usb@9a03c00 { - compatible = "generic-ohci"; + compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; - interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; reset-names = "power", "softreset"; - phys = <&usb2_picophy1>; phy-names = "usb"; @@ -99,9 +53,9 @@ }; ehci0: usb@9a03e00 { - compatible = "generic-ehci"; + compatible = "st,st-ehci-300x"; reg = <0x9a03e00 0x100>; - interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, @@ -116,15 +70,14 @@ }; ohci1: usb@9a83c00 { - compatible = "generic-ohci"; + compatible = "st,st-ohci-300x"; reg = <0x9a83c00 0x100>; - interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; phy-names = "usb"; @@ -132,9 +85,9 @@ }; ehci1: usb@9a83e00 { - compatible = "generic-ehci"; + compatible = "st,st-ehci-300x"; reg = <0x9a83e00 0x100>; - interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, @@ -142,18 +95,18 @@ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; reset-names = "power", "softreset"; - phys = <&usb2_picophy2>; phy-names = "usb"; status = "disabled"; }; - sti-display-subsystem { + sti-display-subsystem@0 { compatible = "st,sti-display-subsystem"; #address-cells = <1>; #size-cells = <1>; + reg = <0 0>; assigned-clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, <&clk_s_c0_pll1 0>, @@ -243,10 +196,10 @@ sti_hdmi: sti-hdmi@8d04000 { compatible = "st,stih407-hdmi"; - #sound-dai-cells = <0>; reg = <0x8d04000 0x1000>; reg-names = "hdmi-reg"; - interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "irq"; clock-names = "pix", "tmds", @@ -262,7 +215,7 @@ <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; - hdmi,hpd-gpio = <&pio5 3>; + hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; reset-names = "hdmi"; resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; ddc = <&hdmiddc>; @@ -283,24 +236,7 @@ <&clk_s_d2_quadfs 1>; }; - sti-dvo@8d00400 { - compatible = "st,stih407-dvo"; - status = "disabled"; - reg = <0x8d00400 0x200>; - reg-names = "dvo-reg"; - clock-names = "dvo_pix", - "dvo", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, - <&clk_s_d2_flexgen CLK_DVO>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dvo>; - }; - - sti-hqvdp@9c000000 { + sti-hqvdp@9c00000 { compatible = "st,stih407-hqvdp"; reg = <0x9C00000 0x100000>; clock-names = "hqvdp", "pix_main"; @@ -315,7 +251,7 @@ bdisp0:bdisp@9f10000 { compatible = "st,stih407-bdisp"; reg = <0x9f10000 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bdisp"; clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; }; @@ -324,8 +260,8 @@ compatible = "st,st-hva"; reg = <0x8c85000 0x400>, <0x6000000 0x40000>; reg-names = "hva_registers", "hva_esram"; - interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>, - <GIC_SPI 59 IRQ_TYPE_NONE>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_hva"; clocks = <&clk_s_c0_flexgen CLK_HVA>; }; @@ -338,66 +274,7 @@ interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; }; - g1@8c80000 { - compatible = "st,g1"; - reg = <0x8c80000 0x194>; - interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>; - }; - - temp0{ - compatible = "st,stih407-thermal"; - reg = <0x91a0000 0x28>; - clock-names = "thermal"; - clocks = <&clk_sysin>; - interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; - }; - - delta0 { - compatible = "st,delta"; - clock-names = "delta", "delta-st231", "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - - h264pp0: h264pp@8c00000 { - compatible = "st,h264pp"; - reg = <0x8c00000 0x20000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>; - clock-names = "clk_h264pp_0"; - clocks = <&clk_s_c0_flexgen CLK_PP_DMU>; - }; - - mali: mali@09f00000 { - compatible = "arm,mali-400"; - reg = <0x09f00000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>, - <GIC_SPI 50 IRQ_TYPE_NONE>, - <GIC_SPI 41 IRQ_TYPE_NONE>, - <GIC_SPI 45 IRQ_TYPE_NONE>, - <GIC_SPI 42 IRQ_TYPE_NONE>, - <GIC_SPI 46 IRQ_TYPE_NONE>, - <GIC_SPI 43 IRQ_TYPE_NONE>, - <GIC_SPI 47 IRQ_TYPE_NONE>, - <GIC_SPI 44 IRQ_TYPE_NONE>, - <GIC_SPI 48 IRQ_TYPE_NONE>; - interrupt-names = "IRQGP", - "IRQGPMMU", - "IRQPP0", - "IRQPPMMU0", - "IRQPP1", - "IRQPPMMU1", - "IRQPP2", - "IRQPPMMU2", - "IRQPP3", - "IRQPPMMU3"; - clock-names = "gpu-clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; - reset-names = "gpu"; - resets = <&softreset STIH407_GPU_SOFTRESET>; - }; - - delta0 { + delta0@0 { compatible = "st,st-delta"; clock-names = "delta", "delta-st231", @@ -407,51 +284,17 @@ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; }; - h264pp0: h264pp@8c00000 { - compatible = "st,h264pp"; - reg = <0x8c00000 0x20000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>; - clock-names = "clk_h264pp_0"; - clocks = <&clk_s_c0_flexgen CLK_PP_DMU>; - }; - - mali: mali@09f00000 { - compatible = "arm,mali-400"; - reg = <0x09f00000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_NONE>, - <GIC_SPI 50 IRQ_TYPE_NONE>, - <GIC_SPI 41 IRQ_TYPE_NONE>, - <GIC_SPI 45 IRQ_TYPE_NONE>, - <GIC_SPI 42 IRQ_TYPE_NONE>, - <GIC_SPI 46 IRQ_TYPE_NONE>, - <GIC_SPI 43 IRQ_TYPE_NONE>, - <GIC_SPI 47 IRQ_TYPE_NONE>, - <GIC_SPI 44 IRQ_TYPE_NONE>, - <GIC_SPI 48 IRQ_TYPE_NONE>; - interrupt-names = "IRQGP", - "IRQGPMMU", - "IRQPP0", - "IRQPPMMU0", - "IRQPP1", - "IRQPPMMU1", - "IRQPP2", - "IRQPPMMU2", - "IRQPP3", - "IRQPPMMU3"; - clock-names = "gpu-clk"; - clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; - reset-names = "gpu"; - resets = <&softreset STIH407_GPU_SOFTRESET>; - }; - - hva@8c85000{ - compatible = "st,st-hva"; - reg = <0x8c85000 0x400>, <0x6000000 0x40000>; - reg-names = "hva_registers", "hva_esram"; - interrupts = <GIC_SPI 58 IRQ_TYPE_NONE>, - <GIC_SPI 59 IRQ_TYPE_NONE>; - clock-names = "clk_hva"; - clocks = <&clk_s_c0_flexgen CLK_HVA>; + sti-cec@94a087c { + compatible = "st,stih-cec"; + reg = <0x94a087c 0x64>; + clocks = <&clk_sysin>; + clock-names = "cec-clk"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cec-irq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cec0_default>; + resets = <&softreset STIH407_LPM_SOFTRESET>; + hdmi-phandle = <&sti_hdmi>; }; }; }; -- 2.17.1

2 1

[U-Boot] [PATCH] mmc: stm32_sdmmc2: Increase SDMMC_BUSYD0END_TIMEOUT_US
by Patrice Chotard 26 Aug '19

26 Aug '19

Increase SDMMC_BUSYD0END_TIMEOUT_US from 1s to 2s to avoid timeout error during blocks erase on some sdcard Issue seen on Kingston 16GB : Device: STM32 SDMMC2 Manufacturer ID: 27 OEM: 5048 Name: SD16G Bus Speed: 50000000 Mode: SD High Speed (50MHz) card capabilities: widths [4, 1] modes [SD Legacy, SD High Speed (50MHz)] host capabilities: widths [4, 1] modes [MMC legacy, SD Legacy, MMC High Speed (26MHz), SD High Speed (50MHz), MMC High Speed (52MHz)] Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.5 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes Issue reproduced with following command: STM32MP> mmc erase 0 100000 MMC erase: dev # 0, block # 0, count 1048576 ... mmc erase failed 16384 blocks erased: ERROR By by setting SDMMC_BUSYD0END_TIMEOUT_US at 2 seconds and by adding time measurement in stm32_sdmmc2_end_cmd() as shown below: +start = get_timer(0); /* Polling status register */ ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, SDMMC_BUSYD0END_TIMEOUT_US); +printf("time = %ld ms\n", get_timer(start)); We get the following trace: STM32MP> mmc erase 0 100000 MMC erase: dev # 0, block # 0, count 1048576 ... time = 17 ms time = 1 ms time = 1025 ms time = 54 ms time = 56 ms time = 1021 ms time = 57 ms time = 56 ms time = 1020 ms time = 53 ms time = 57 ms time = 1021 ms time = 53 ms time = 57 ms time = 1313 ms time = 54 ms time = 56 ms time = 1026 ms time = 54 ms time = 56 ms time = 1036 ms time = 54 ms time = 56 ms time = 1028 ms time = 53 ms time = 56 ms time = 1027 ms time = 54 ms time = 56 ms time = 1024 ms time = 54 ms time = 56 ms time = 1020 ms time = 54 ms time = 57 ms time = 1023 ms time = 54 ms time = 56 ms time = 1033 ms time = 53 ms time = 57 ms .... time = 53 ms time = 57 ms time = 1021 ms time = 56 ms time = 56 ms time = 1026 ms time = 54 ms time = 56 ms 1048576 blocks erased: OK We see that 1 second timeout is not enough, we also see one measurement up to 1313 ms. Set the timeout to 2 second to keep a security margin. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/mmc/stm32_sdmmc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 867ed569eb..0ade1b160e 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -190,7 +190,7 @@ struct stm32_sdmmc2_ctx { #define SDMMC_IDMACTRL_IDMAEN BIT(0) #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF -#define SDMMC_BUSYD0END_TIMEOUT_US 1000000 +#define SDMMC_BUSYD0END_TIMEOUT_US 2000000 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, struct mmc_data *data, -- 2.17.1

2 1

[U-Boot] [PATCH v1] ddr, fsl: add DM_I2C support
by Heiko Schocher 26 Aug '19

26 Aug '19

add DM_I2C support for this driver. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Did not fixed checkpatch warning: CHECK: Prefer kernel type 'u8' over 'uint8_t' + uint8_t buf = 0; Travis build, see: https://travis-ci.org/hsdenx/u-boot-test/builds/558858904 drivers/ddr/fsl/main.c | 88 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 77 insertions(+), 11 deletions(-) diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index e1f69a1d25..cb19d0f0ff 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <dm.h> #include <i2c.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -82,17 +83,82 @@ u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { #endif +#if defined(CONFIG_DM_I2C) +#define DEV_TYPE struct udevice +#else +/* Local udevice */ +struct ludevice { + u8 chip; +}; + +#define DEV_TYPE struct ludevice + +#endif + #define SPD_SPA0_ADDRESS 0x36 #define SPD_SPA1_ADDRESS 0x37 -static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr, + int alen, uint8_t *buf, int len) { int ret; + +#ifdef CONFIG_DM_I2C + ret = dm_i2c_read(dev, 0, buf, len); +#else + ret = i2c_read(dev->chip, addr, alen, buf, len); +#endif + + return ret; +} + #ifdef CONFIG_SYS_FSL_DDR4 - uint8_t dummy = 0; +static int ddr_i2c_dummy_write(unsigned int chip_addr) +{ + uint8_t buf = 0; + +#ifdef CONFIG_DM_I2C + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_SPD_BUS_NUM); + return ret; + } + + return dm_i2c_write(dev, 0, buf, 1); +#else + return i2c_write(chip_addr, 0, 1, &buf, 1); #endif + return 0; +} +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; + DEV_TYPE *dev; + +#if defined(CONFIG_DM_I2C) + ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + CONFIG_SYS_SPD_BUS_NUM); + return; + } +#else /* Non DM I2C support - will be removed */ + struct ludevice ldev = { + .chip = i2c_address, + }; + dev = &ldev; + i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); +#endif #ifdef CONFIG_SYS_FSL_DDR4 /* @@ -101,18 +167,18 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) * To access the upper 256 bytes, we need to set EE page address to 1 * See Jedec standar No. 21-C for detail */ - i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1); - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256); + ddr_i2c_dummy_write(SPD_SPA0_ADDRESS); + ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256); if (!ret) { - i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1); - ret = i2c_read(i2c_address, 0, 1, - (uchar *)((ulong)spd + 256), - min(256, - (int)sizeof(generic_spd_eeprom_t) - 256)); + ddr_i2c_dummy_write(SPD_SPA1_ADDRESS); + ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256), + min(256, + (int)sizeof(generic_spd_eeprom_t) + - 256)); } #else - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); + ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); #endif if (ret) { -- 2.21.0

2 4

[U-Boot] [PATCH v1] watchdog: move WATCHDOG_TIMEOUT_MSECS to Kconfig
by Heiko Schocher 26 Aug '19

26 Aug '19

move WATCHDOG_TIMEOUT_MSECS to Kconfig and fix all board defconfigs. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Patchseries build fine on travis see: https://travis-ci.org/hsdenx/u-boot-test/builds/544546490 Based on mainline commit: 68b90e57bc: "configs: tinker-rk3288 disable CONFIG_SPL_I2C_SUPPORT" and wdt imx patches from Marek: http://patchwork.ozlabs.org/patch/1112591/ http://patchwork.ozlabs.org/patch/1112592/ arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 | 1 - configs/dh_imx6_defconfig | 1 + configs/display5_defconfig | 1 + configs/display5_factory_defconfig | 1 + configs/ge_bx50v3_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/m53menlo_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/tqma6s_wru4_mmc_defconfig | 1 + configs/warp_defconfig | 1 + drivers/watchdog/Kconfig | 9 +++++++++ include/configs/MPC8349ITX.h | 6 ------ include/configs/MPC837XERDB.h | 5 ----- include/configs/dh_imx6.h | 1 - include/configs/display5.h | 1 - include/configs/ge_bx50v3.h | 2 -- include/configs/kp_imx6q_tpc.h | 1 - include/configs/m53menlo.h | 1 - include/configs/mx53ppd.h | 2 -- include/configs/socfpga_common.h | 1 - include/configs/socfpga_stratix10_socdk.h | 1 - include/configs/tqma6_wru4.h | 1 - include/configs/warp.h | 1 - include/wdt.h | 3 --- scripts/config_whitelist.txt | 1 - 25 files changed, 18 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 index 9583bf743e..d7f7b9f111 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 @@ -16,6 +16,5 @@ You can enable it by setting CONFIG_IMX_WATCHDOG. Use following config to set watchdog timeout, if this config is not defined, the default timeout value is 128s which is the maximum. Set 10 seconds for example: - #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000 Set CONFIG_WATCHDOG_RESET_DISABLE to disable reset watchdog, so that the watchdog will not be fed in u-boot. diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index d9ec5c7c5e..c3ef829553 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -62,5 +62,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 3b793f4500..1c52441802 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -79,4 +79,5 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=15000 CONFIG_IMX_WATCHDOG=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 0d9eed3a3e..1df7461a21 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -86,5 +86,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=15000 CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index 8be881b939..cc056dc681 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -60,5 +60,6 @@ CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_IPUV3=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=6000 CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 0ca83cbfea..7e9d2fc747 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -40,5 +40,6 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 0e5fa01fde..6be311bf35 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -69,6 +69,7 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 19ebab78e9..8c8e9a28ed 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -49,4 +49,5 @@ CONFIG_USB_EHCI_MX5=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set +CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index 57f2221c78..ea29fa967b 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -66,5 +66,6 @@ CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index a37d769296..e033cc9d8c 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -39,5 +39,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 CONFIG_IMX_WATCHDOG=y CONFIG_OF_LIBFDT=y diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 5993865647..9784a998c4 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -8,6 +8,15 @@ config WATCHDOG this option if you want to service enabled watchdog by U-Boot. Disable this option if you want U-Boot to start watchdog but never service it. +config WATCHDOG_TIMEOUT_MSECS + int "Watchdog timeout in msec" + default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 + default 128000 if ARCH_MX7 || ARCH_VF610 + default 30000 if ARCH_SOCFPGA + default 60000 + help + Watchdog timeout in msec + config HW_WATCHDOG bool diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index a3f704c73b..c395d62379 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -209,12 +209,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_VSC7385_BASE 0xF8000000 -#ifdef CONFIG_VSC7385_ENET - - -#endif - - #define CONFIG_SYS_LED_BASE 0xF9000000 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 13a7682958..37f51ba743 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -186,11 +186,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#ifdef CONFIG_VSC7385_ENET - - -#endif - /* * Serial Port */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 3eee382a64..54b61a0a06 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -98,7 +98,6 @@ #endif /* Watchdog */ -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/display5.h b/include/configs/display5.h index 8829cbad91..9d7cb270a8 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -361,7 +361,6 @@ /* Commands */ /* Watchdog */ -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 15000 /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 0481ed06a9..4bc2a8878b 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -28,8 +28,6 @@ #define CONFIG_REVISION_TAG #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 - #define CONFIG_MXC_UART /* SATA Configs */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index d2ebf92953..4d075b47f6 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -62,7 +62,6 @@ #endif /* Watchdog */ -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index fc0b1f480c..ff6354904b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -156,7 +156,6 @@ #define CONFIG_FSL_IIM /* Watchdog */ -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 /* * Boot Linux diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 2d6715cba2..2944415d7f 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -22,8 +22,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 8000 - #define CONFIG_BOARD_LATE_INIT #define CONFIG_REVISION_TAG diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d1034ac280..d6a7caee19 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -108,7 +108,6 @@ #define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 #endif /* diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 8d2971c6e2..27f87e75df 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -167,7 +167,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_l4_sys_free_clk_hz(void); #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) #endif -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 #endif /* diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 34f000f214..0af52e5565 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -17,7 +17,6 @@ #define CONSOLE_DEV "ttymxc3" /* Watchdog */ -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 /* Config on-board RTC */ #define CONFIG_RTC_DS1337 diff --git a/include/configs/warp.h b/include/configs/warp.h index 5345f5314d..41fd6c759e 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE /* Watchdog */ -#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M) diff --git a/include/wdt.h b/include/wdt.h index 5bcff24ab3..e833d3a772 100644 --- a/include/wdt.h +++ b/include/wdt.h @@ -107,9 +107,6 @@ struct wdt_ops { }; #if CONFIG_IS_ENABLED(WDT) -#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS -#define CONFIG_WATCHDOG_TIMEOUT_MSECS (60 * 1000) -#endif #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) static inline int initr_watchdog(void) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8651d569c5..921dc5290c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4451,7 +4451,6 @@ CONFIG_WATCHDOG_NOWAYOUT CONFIG_WATCHDOG_PRESC CONFIG_WATCHDOG_RC CONFIG_WATCHDOG_TIMEOUT -CONFIG_WATCHDOG_TIMEOUT_MSECS CONFIG_WD_PERIOD CONFIG_X600 CONFIG_X86EMU_DEBUG -- 2.21.0

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[U-Boot] [PATCH 00/15] rk3399: Add redundant boot support
by Jagan Teki 26 Aug '19

26 Aug '19

Boot redundancy is one of the key criteria for switch recovery or golden partition based on the bootcount value, which indeed very much needed in production systems on the fields. This patchset support redundant boot on Rockchip rk3399. To make full functional redundancy below features would require from U-Boot level. - bootcount, for counting number reboots - altboot - watchdog support, if SPL or U-Boot reset because of WDT - add CPUINFO for more understanding about how SoC and reset reason. patch 0001 - 0005: cpu info, reset reason patch 0006 - 0009: designware watchdog driver, dm-conversion patch 0010: Add watchdog property available to SPL patch 0011: Add Kconfig option for dw_wdt.c patch 0012: Disable watchdog for TPL patch 0013: enable watchdog on rockpro64, overlay patch 0014: bootcount support patch 0015: enable bootcount on rockpro64, overlay I would like, not to merge watchdog and bootcount on Mainline devboards since these features will mostly required on production devices but any comments, please share. Any inputs? Jagan. Jagan Teki (15): arm: rockchip: Add common cru.h rockchip: Add cpu-info rockchip: rk3288: Print reset reason rockchip: Add common reset reason rockchip: rk3288/rk3399: Enable DISPLAY_CPUINFO wdt: designware: Simplify is_enabled function wdt: designware: Simplify enable function wdt: dw: Add driver-model support wdt: dw: Rename to dw_wdt.c rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for watchdog wdt: Kconfig: Add WDT_DW entry include: rk3399: Disable watchdog in TPL [DO NOT MERGE] rk3399: rockpro64: Enable watchdog rockchip: rk3399: Add bootcount support [DO NOT MERGE] rk3399: rockpro64: Enable bootcount arch/arm/dts/rk3399-u-boot.dtsi | 6 + arch/arm/include/asm/arch-rockchip/cru.h | 28 +++ .../include/asm/arch-rockchip/cru_rk3288.h | 14 +- arch/arm/mach-rockchip/Kconfig | 2 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu-info.c | 65 +++++++ arch/arm/mach-rockchip/rk3288-board.c | 39 ---- arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 2 +- arch/arm/mach-rockchip/rk3399-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3399/Kconfig | 10 + arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 2 +- common/board_f.c | 2 +- configs/evb-rk3288_defconfig | 1 - configs/evb-rk3399_defconfig | 1 - configs/fennec-rk3288_defconfig | 1 - configs/ficus-rk3399_defconfig | 1 - configs/firefly-rk3288_defconfig | 1 - configs/firefly-rk3399_defconfig | 1 - configs/miqi-rk3288_defconfig | 1 - configs/nanopc-t4-rk3399_defconfig | 1 - configs/nanopi-m4-rk3399_defconfig | 1 - configs/nanopi-neo4-rk3399_defconfig | 1 - configs/orangepi-rk3399_defconfig | 1 - configs/phycore-rk3288_defconfig | 1 - configs/popmetal-rk3288_defconfig | 1 - configs/puma-rk3399_defconfig | 1 - configs/rock-pi-4-rk3399_defconfig | 1 - configs/rock960-rk3399_defconfig | 1 - configs/rockpro64-rk3399_defconfig | 4 +- configs/tinker-rk3288_defconfig | 1 - configs/vyasa-rk3288_defconfig | 1 - drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/ram/rockchip/sdram_rk3288.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/video/rockchip/rk3288_mipi.c | 2 +- drivers/video/rockchip/rk3399_mipi.c | 2 +- drivers/video/rockchip/rk_mipi.c | 2 +- drivers/watchdog/Kconfig | 9 + drivers/watchdog/Makefile | 2 +- drivers/watchdog/designware_wdt.c | 73 ------- drivers/watchdog/dw_wdt.c | 184 ++++++++++++++++++ include/configs/rk3399_common.h | 10 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_stratix10_socdk.h | 2 +- scripts/config_whitelist.txt | 1 - 46 files changed, 332 insertions(+), 160 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/cru.h create mode 100644 arch/arm/mach-rockchip/cpu-info.c delete mode 100644 drivers/watchdog/designware_wdt.c create mode 100644 drivers/watchdog/dw_wdt.c -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH] sunxi: H6: DRAM: Add support for half DQ
by Jernej Skrabec 23 Aug '19

23 Aug '19

Half DQ configuration seems to be very rare for H6 based boards/STBs, but exists nevertheless. Currently the only known product which needs this support is Tanix TX6 mini. This commit adds support for half DQ configuration. Code was tested for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix TX6 4 GiB/DDR3) and none were found. Thanks to Icenowy Zheng for help with this code. Signed-off-by: Jernej Skrabec <jernej.skrabec(a)siol.net> --- .../include/asm/arch-sunxi/dram_sun50i_h6.h | 1 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 74 ++++++++++++------- 2 files changed, 50 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index 0a1da02376..49a8a66f7b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -315,6 +315,7 @@ struct dram_para { u8 cols; u8 rows; u8 ranks; + u8 bus_full_width; const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 2a8275da3a..0d65327d35 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para) u8 rows = para->rows; u8 ranks = para->ranks; + if (!para->bus_full_width) + cols -= 1; + /* Ranks */ if (ranks == 2) mctl_ctl->addrmap[0] = rows + cols - 3; @@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para) /* Columns */ mctl_ctl->addrmap[2] = 0; switch (cols) { + case 7: + mctl_ctl->addrmap[3] = 0x1F1F1F00; + mctl_ctl->addrmap[4] = 0x1F1F; + break; case 8: mctl_ctl->addrmap[3] = 0x1F1F0000; mctl_ctl->addrmap[4] = 0x1F1F; @@ -300,13 +307,16 @@ static void mctl_com_init(struct dram_para *para) reg_val = 0x3f00; clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); - /* TODO: half DQ, DDR4 */ - reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) | - MSTR_ACTIVE_RANKS(para->ranks); + /* TODO: DDR4 */ + reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) reg_val |= MSTR_DEVICETYPE_LPDDR3; if (para->type == SUNXI_DRAM_TYPE_DDR3) reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; + if (para->bus_full_width) + reg_val |= MSTR_BUSWIDTH_FULL; + else + reg_val |= MSTR_BUSWIDTH_HALF; writel(reg_val | BIT(31), &mctl_ctl->mstr); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) @@ -333,7 +343,10 @@ static void mctl_com_init(struct dram_para *para) } writel(reg_val, &mctl_ctl->odtcfg); - /* TODO: half DQ */ + if (!para->bus_full_width) { + writel(0x0, &mctl_phy->dx[2].gcr[0]); + writel(0x0, &mctl_phy->dx[3].gcr[0]); + } } static void mctl_bit_delay_set(struct dram_para *para) @@ -514,22 +527,31 @@ static void mctl_channel_init(struct dram_para *para) if (readl(&mctl_phy->pgsr[0]) & 0x400000) { - /* - * Detect single rank. - * TODO: also detect half DQ. - */ + /* Check for single rank and optionally half DQ. */ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 && - (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) { + (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) { para->ranks = 1; + + if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 || + (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2) + para->bus_full_width = 0; + /* Restart DRAM initialization from scratch. */ mctl_core_init(para); return; } - else { - panic("This DRAM setup is currently not supported.\n"); + + /* Check for dual rank and half DQ */ + if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 && + (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) { + para->bus_full_width = 0; + + /* Restart DRAM initialization from scratch. */ + mctl_core_init(para); + return; } + + panic("This DRAM setup is currently not supported.\n"); } if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { @@ -557,11 +579,8 @@ static void mctl_channel_init(struct dram_para *para) static void mctl_auto_detect_dram_size(struct dram_para *para) { - /* TODO: non-LPDDR3, half DQ */ - /* - * Detect rank number by the code in mctl_channel_init. Furtherly - * when DQ detection is available it will also be executed there. - */ + /* TODO: non-(LP)DDR3 */ + /* Detect rank number and half DQ by the code in mctl_channel_init. */ mctl_core_init(para); /* detect row address bits */ @@ -570,8 +589,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) mctl_core_init(para); for (para->rows = 13; para->rows < 18; para->rows++) { - /* 8 banks, 8 bit per byte and 32 bit width */ - if (mctl_mem_matches((1 << (para->rows + para->cols + 5)))) + /* 8 banks, 8 bit per byte and 16/32 bit width */ + if (mctl_mem_matches((1 << (para->rows + para->cols + + 4 + para->bus_full_width)))) break; } @@ -580,18 +600,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) mctl_core_init(para); for (para->cols = 8; para->cols < 11; para->cols++) { - /* 8 bits per byte and 32 bit width */ - if (mctl_mem_matches(1 << (para->cols + 2))) + /* 8 bits per byte and 16/32 bit width */ + if (mctl_mem_matches(1 << (para->cols + 1 + + para->bus_full_width))) break; } } unsigned long mctl_calc_size(struct dram_para *para) { - /* TODO: non-LPDDR3, half DQ */ + u8 width = para->bus_full_width ? 4 : 2; + + /* TODO: non-(LP)DDR3 */ - /* 8 banks, 32-bit (4 byte) data width */ - return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks; + /* 8 banks */ + return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; } #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \ @@ -625,6 +648,7 @@ unsigned long sunxi_dram_init(void) .ranks = 2, .cols = 11, .rows = 14, + .bus_full_width = 1, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 .type = SUNXI_DRAM_TYPE_LPDDR3, .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, -- 2.22.0

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