July 2019 - U-Boot

[U-Boot] [PATCH] armv8: ls1028aqds: define ARCH_MISC_INIT to handle mux
by Pankaj Bansal 22 Aug '19

22 Aug '19

define ARCH_MISC_INIT for LS1028AQDS platform to handle board related mux. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 51d4acedac..3b171cf643 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1290,6 +1290,7 @@ config TARGET_LS1028AQDS select ARM64 select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT + select ARCH_MISC_INIT help Support for Freescale LS1028AQDS platform The LS1028A Development System (QDS) is a high-performance -- 2.17.1

2 1

[U-Boot] [PATCH v2 1/3] armv8: ls1088aqds: The ls1088aqds board supports the I2C driver model.
by Chuanhua Han 22 Aug '19

22 Aug '19

This patch is updating ls1088aqds board init code to support DM_I2C. Signed-off-by: Chuanhua Han <chuanhua.han(a)nxp.com> --- depends on: - http://patchwork.ozlabs.org/project/uboot/list/?series=110856 - http://patchwork.ozlabs.org/project/uboot/list/?series=109459 - http://patchwork.ozlabs.org/project/uboot/list/?series=120936 Changes in v2: - Simplify i2c_write related function calls and reduce the amount of code by using circular iteration - Place the variable definitions for udevice at the beginning of the function board/freescale/ls1088a/eth_ls1088aqds.c | 149 +++++++++++++++++++++---------- include/configs/ls1088aqds.h | 4 +- 2 files changed, 104 insertions(+), 49 deletions(-) diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index f16b78c..6fb671f 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -80,11 +80,16 @@ struct ls1088a_qds_mdio { struct mii_dev *realbus; }; +struct reg_pair { + uint addr; + u8 *val; +}; + static void sgmii_configure_repeater(int dpmac) { struct mii_dev *bus; uint8_t a = 0xf; - int i, j, ret; + int i, j, k, ret; unsigned short value; const char *dev = "LS1088A_QDS_MDIO2"; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -96,8 +101,28 @@ static void sgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, &reg_val[0]}, {4, &reg_val[1]}, + {8, &reg_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, &reg_val[3]}, + {0x2d, &reg_val[4]}, {4, &reg_val[5]}, + }; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif + /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 1: @@ -143,31 +168,34 @@ static void sgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, - &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, - &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, - &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, - &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_phy_addr, + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_phy_addr, + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + mdelay(100); ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) @@ -202,7 +230,7 @@ error: static void qsgmii_configure_repeater(int dpmac) { uint8_t a = 0xf; - int i, j; + int i, j, k; int i2c_phy_addr = 0; int phy_addr = 0; int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b}; @@ -212,12 +240,32 @@ static void qsgmii_configure_repeater(int dpmac) uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7}; uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84}; + u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20}; + struct reg_pair reg_pair[10] = { + {6, &reg_val[0]}, {4, &reg_val[1]}, + {8, &reg_val[2]}, {0xf, NULL}, + {0x11, NULL}, {0x16, NULL}, + {0x18, NULL}, {0x23, &reg_val[3]}, + {0x2d, &reg_val[4]}, {4, &reg_val[5]}, + }; + const char *dev = mdio_names[EMI1_SLOT1]; int ret = 0; unsigned short value; +#ifdef CONFIG_DM_I2C + struct udevice *udev; +#endif /* Set I2c to Slot 1 */ - i2c_write(0x77, 0, 0, &a, 1); +#ifndef CONFIG_DM_I2C + ret = i2c_write(0x77, 0, 0, &a, 1); +#else + ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, 0, &a, 1); +#endif + if (ret) + goto error; switch (dpmac) { case 7: @@ -251,28 +299,35 @@ static void qsgmii_configure_repeater(int dpmac) return; } +#ifdef CONFIG_DM_I2C + i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev); +#endif + for (i = 0; i < 4; i++) { for (j = 0; j < 4; j++) { - a = 0x18; - i2c_write(i2c_phy_addr, 6, 1, &a, 1); - a = 0x38; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - a = 0x4; - i2c_write(i2c_phy_addr, 8, 1, &a, 1); - - i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1); - i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1); - - i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1); - i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1); - - a = 0x14; - i2c_write(i2c_phy_addr, 0x23, 1, &a, 1); - a = 0xb5; - i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1); - a = 0x20; - i2c_write(i2c_phy_addr, 4, 1, &a, 1); - mdelay(100); + reg_pair[3].val = &ch_a_eq[i]; + reg_pair[4].val = &ch_a_ctl2[j]; + reg_pair[5].val = &ch_b_eq[i]; + reg_pair[6].val = &ch_b_ctl2[j]; + + for (k = 0; k < 10; k++) { +#ifndef CONFIG_DM_I2C + ret = i2c_write(i2c_addr[dpmac], + reg_pair[k].addr, + 1, reg_pair[k].val, 1); +#else + ret = i2c_get_chip_for_busnum(0, + i2c_addr[dpmac], + 1, &udev); + if (!ret) + ret = dm_i2c_write(udev, + reg_pair[k].addr, + reg_pair[k].val, 1); +#endif + if (ret) + goto error; + } + ret = miiphy_read(dev, phy_addr, 0x11, &value); if (ret > 0) goto error; diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 4387862..8b62bbe 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -46,7 +46,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_CLK_FREQ 100000000 #else #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif @@ -357,9 +359,7 @@ unsigned long get_board_ddr_clk(void); * RTC configuration */ #define RTC -#define CONFIG_RTC_PCF8563 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#define CONFIG_CMD_DATE /* EEPROM */ #define CONFIG_ID_EEPROM -- 2.9.5

2 4

[U-Boot] [PATCH 1/5] armv8: fsl-layerscape: add missing sec jr base address defines
by laurentiu.tudor＠nxp.com 22 Aug '19

22 Aug '19

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> Add defines for all the SEC job rings base addresses. Signed-off-by: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..7cd5333ff4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -89,10 +89,18 @@ /* SEC */ #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define FSL_SEC_JR1_OFFSET 0x07020000ull +#define FSL_SEC_JR2_OFFSET 0x07030000ull +#define FSL_SEC_JR3_OFFSET 0x07040000ull #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) +#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) +#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) +#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) #ifdef CONFIG_TFABOOT #ifdef CONFIG_NXP_LSCH3_2 -- 2.17.1

3 13

[U-Boot] [PATCH v5] board/BuR/zynq/brsmarc2: initial commit
by Hannes Schmelzer 22 Aug '19

22 Aug '19

This commit adds the first of a few more Xilinx ZYNQ based SoM boards. The SoM is based on Xilinx Zynq 7000 SoC. Mainly vxWorks 6.9.4.x is running on the board, doing some PLC stuff on various carrier boards. Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- Changes in v5: - rebase to current master - dts: fix dtc compiler warnings regarding cell-size in board-thermal - remove brsmarc2_r512 target (can be covered all with brsmarc2) Changes in v4: - use CONFIG_SYS_AUTOLOAD instead defining it in environment - drop duplicate CONFIG_BOOTP_MAY_FAIL - drop duplicate CONFIG_ENV_OVERWRITE - move CONFIG_MII from boardheader to Kconfig - dts: change temperature-sensor node names to fit dts spec - dts: change rtc node name to fit dts spec - dts: drop memory node from -common-dtsi - dts: move vxWorks (bur) specific bindings at phys to -vxworks.dtsi - dts: minor cosmetic (whitespace) cleanup - dts: move resetcontroller node to -vxworks.dtsi Changes in v3: - drop silicon version 1/2 from ps7_init_gpl.c (they are obsolete) - board.c: drop obsolete board_eth_init(...) - board.c: strip down dram_init(..) - board.c: drop unused #include - board.c: cleanup comments - move CONFIG_ZYNQ_SERIAL from boardheader to Kconfig - move CONFIG_FPGA_ZYNQPL from boardheader to Kconfig - fix comments in boardheader - drop *_SYS_LDSCRIPT from boardheader (defined in Kconfig) - drop CONFIG_SYS_MALLOC_LEN (defined in Kconfig) - dop CONFIG_ENV_SPI_MAX_HZ from boardheader (defined in Kconfig) - dts: split vxWorks specific parts away from dts into separate file - dts: add compatible string to factory-settings node - dts: drop invalid (zero)= mac-addresses on gem0/gem1 - dts: fixup style on ethernet_phy1 description - dts: add comments to phy's - drop helper-scripts for taking vivado handoff files into tree Changes in v2: - fix SDPX tag in Make-files/rules arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-brsmarc2-common.dtsi | 157 ++++++++++++++++++ arch/arm/dts/zynq-brsmarc2-vxworks.dtsi | 143 +++++++++++++++++ arch/arm/dts/zynq-brsmarc2.dts | 8 + board/BuR/zynq/.gitignore | 1 + board/BuR/zynq/MAINTAINERS | 6 + board/BuR/zynq/Makefile | 16 ++ board/BuR/zynq/brsmarc2/board.c | 63 ++++++++ board/BuR/zynq/brsmarc2/ps7_init_gpl.c | 276 ++++++++++++++++++++++++++++++++ board/BuR/zynq/config.mk | 49 ++++++ configs/brsmarc2_defconfig | 75 +++++++++ include/configs/brsmarc2.h | 150 +++++++++++++++++ 12 files changed, 945 insertions(+) create mode 100644 arch/arm/dts/zynq-brsmarc2-common.dtsi create mode 100644 arch/arm/dts/zynq-brsmarc2-vxworks.dtsi create mode 100644 arch/arm/dts/zynq-brsmarc2.dts create mode 100644 board/BuR/zynq/.gitignore create mode 100644 board/BuR/zynq/MAINTAINERS create mode 100644 board/BuR/zynq/Makefile create mode 100644 board/BuR/zynq/brsmarc2/board.c create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c create mode 100644 board/BuR/zynq/config.mk create mode 100644 configs/brsmarc2_defconfig create mode 100644 include/configs/brsmarc2.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 20dbc2f..e718fe6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -233,6 +233,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm011-x16.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ + zynq-brsmarc2.dtb \ zynq-zed.dtb \ zynq-zturn.dtb \ zynq-zybo.dtb \ diff --git a/arch/arm/dts/zynq-brsmarc2-common.dtsi b/arch/arm/dts/zynq-brsmarc2-common.dtsi new file mode 100644 index 0000000..09b88c7 --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2-common.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * common DTS part for B&R BRSMARC2 boards + * + * Copyright (C) 2019 B&R Industrial Automation GmbH + */ + +/dts-v1/; +#include "zynq-7000.dtsi" +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "BRSMARC2 Zynq SoM"; + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + ethernet1 = &gem1; + i2c0 = &i2c0; + serial0 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + can0 = &can0; + can1 = &can1; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + board_thermal: board-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <2500>; /* milliseconds */ + + thermal-sensors = <&temp_core 0>; + + trips { + crit_trip: crit-trip { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&crit_trip>; + cooling-device = + <&resetc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&amba { + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&ethernet_phy0>; + + /* DP83822 phy */ + ethernet_phy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gem1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&ethernet_phy1>; + + /* DP83822 phy */ + ethernet_phy1: ethernet-phy@3 { + reg = <3>; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; + status = "okay"; + clock-frequency = <100000>; + + boardtemp: temperature-sensor@49 { + #thermal-sensor-cells = <0>; + compatible = "nxp,pct2075"; + reg = <0x49>; + }; + + temp_core: temperature-sensor@4c { /* temp. zynq die */ + #thermal-sensor-cells = <1>; + compatible = "ti,tmp431"; + reg = <0x4c>; + }; + + extrtc: rtc@51 { /* realtime clock */ + compatible = "epson,rx8571"; + reg = <0x51>; + }; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; + spi-max-frequency = <100000000>; + spi_flash: spiflash@0 { + u-boot,dm-pre-reloc; + compatible = "spidev", "spi-flash"; + spi-max-frequency = <100000000>; + reg = <0>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; +}; + +&sdhci0 { + status = "okay"; + max-frequency = <25000000>; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi b/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi new file mode 100644 index 0000000..136fc52 --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2-vxworks.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * primary OS (vxWorks 6.9.4.x) specific parts for B&R BRSMARC2 boards + * + * Copyright (C) 2019 B&R Industrial Automation GmbH + */ + +#include "zynq-brsmarc2-common.dtsi" + +/ { + fset: factory-settings { + compatible = "bur,fsetv1"; + bl-version = " "; + order-no = " "; + cpu-order-no = " "; + hw-revision = " "; + serial-no = <0>; + device-id = <0x0>; + parent-id = <0x0>; + hw-variant = <0x0>; + hw-platform = <0x0>; + fram-offset = <0x0>; + fram-size = <0x0>; + cache-disable = <0x0>; + cpu-clock = <0x0>; + }; + + aliases { + fset = &fset; + }; + + board { + status = "okay"; + compatible = "bur,brsmarc2-som"; + usb0mux-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>; + usb1mux-gpios = <&gpio0 69 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + fpga: fpga@40000000 { + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + compatible = "bur,zynqPL", "simple-bus"; + reg = <0x40200000 0x1 /* version registers */ + 0x40200004 0x1>; /* misc registers */ + bur,upddest = &spi_flash; + bur,updaddr = <0x100000>; + bur,updsize = <0x200000>; + + plk: plk@80000000 { + status = "disabled"; + compatible = "bur,DdVxIoEplSMP"; + bur,hwtree = "IF9"; + reg = <0x80000000 0x8000>; + interrupt-parent = <&intc>; + interrupts = <0 68 4>, + <0 84 4>; + local-mac-address = [ 00 60 65 aa ab ac ]; + }; + + x2x: x2x@40100000 { + status = "disabled"; + compatible = "bur,xlk"; + bur,hwtree = "IF10"; + reg = <0x40100000 0x8000 + 0x40108000 0x8000>; + interrupt-parent = <&intc>; + interrupts = <0 65 4>; + }; + + uart2: serial@40200800 { + status = "disabled"; + compatible = "ns16550a", "bur,DdVxSf16x5xIO"; + bur,hwtree = "IF8"; + reg = <0x40200800 0x40>; + interrupt-parent = <&intc>; + interrupts = <0 66 4>; + term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>; + }; + + uart3: serial@40200840 { + status = "disabled"; + compatible = "ns16550a", "bur,DdVxSf16x5xIO"; + bur,hwtree = "IF9"; + reg = <0x40200840 0x40>; + interrupt-parent = <&intc>; + interrupts = <0 67 4>; + term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>; + }; + + uart4: serial@40200900 { + status = "disabled"; + compatible = "ns16550a", "bur,DdVxSf16x5xIO"; + bur,hwtree = "IF20"; + reg = <0x40200900 0x40>; + interrupt-parent = <&intc>; + interrupts = <0 88 4>; + }; + + uart5: serial@40200A00 { + status = "disabled"; + compatible = "ns16550a", "bur,DdVxSf16x5xIO"; + bur,hwtree = "IF21"; + reg = <0x40200A00 0x40>; + interrupt-parent = <&intc>; + interrupts = <0 90 4>; + }; + }; +}; + +&i2c0 { + resetc: reset-controller@60 { + compatible = "bur,rststm"; + reg = <0x60>; + hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>; + cooling-min-state = <0>; + cooling-max-state = <1>; /* reset gets fired */ + #cooling-cells = <2>; /* min followed by max */ + }; +}; + +&can0 { + status = "disabled"; + bur,hwtree = "IF6"; + term-gpios = <&gpio0 70 GPIO_ACTIVE_HIGH>; +}; + +&can1 { + status = "disabled"; + bur,hwtree = "IF7"; + term-gpios = <&gpio0 71 GPIO_ACTIVE_HIGH>; +}; + +&ethernet_phy0 { + ti,ledcr = <0x0480>; + ti,rgmii-rxclk-shift; +}; + +&ethernet_phy1 { + ti,ledcr = <0x0480>; +}; diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts new file mode 100644 index 0000000..b53a2e7 --- /dev/null +++ b/arch/arm/dts/zynq-brsmarc2.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * B&R BRSMARC2 board DTS file + * + * Copyright (C) 2019 B&R Industrial Automation GmbH + */ + +#include "zynq-brsmarc2-vxworks.dtsi" diff --git a/board/BuR/zynq/.gitignore b/board/BuR/zynq/.gitignore new file mode 100644 index 0000000..fa64fbc --- /dev/null +++ b/board/BuR/zynq/.gitignore @@ -0,0 +1 @@ +./ps7_init_gpl.c diff --git a/board/BuR/zynq/MAINTAINERS b/board/BuR/zynq/MAINTAINERS new file mode 100644 index 0000000..c6b3cfb --- /dev/null +++ b/board/BuR/zynq/MAINTAINERS @@ -0,0 +1,6 @@ +BRSMARC2 BOARD +M: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> +S: Maintained +F: board/BuR/zynq/ +F: include/configs/brsmarc2.h +F: configs/brsmarc2_defconfig diff --git a/board/BuR/zynq/Makefile b/board/BuR/zynq/Makefile new file mode 100644 index 0000000..85a4b77 --- /dev/null +++ b/board/BuR/zynq/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Hannes Schmelzer <oe5hpm(a)oevsv.at> - +# B&R Industrial Automation GmbH - http://www.br-automation.com +# + +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//') + +obj-y := ../common/common.o +obj-y += ../common/br_resetc.o +obj-y += $(hw-platform-y)/board.o + +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes diff --git a/board/BuR/zynq/brsmarc2/board.c b/board/BuR/zynq/brsmarc2/board.c new file mode 100644 index 0000000..0331087 --- /dev/null +++ b/board/BuR/zynq/brsmarc2/board.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board functions for B&R BRSMARC2 Board + * + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm(a)oevsv.at> + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ +#include <common.h> +#include <fdtdec.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <i2c.h> +#include "../../common/bur_common.h" +#include "../../common/br_resetc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +int board_init(void) +{ + /* reset pulse for peripherals */ + gpio_request(9, "nRESET_PS_3V3"); + gpio_direction_output(9, 1); + + return 0; +} +#else +int board_init(void) +{ + return 0; +} +#endif + +int board_late_init(void) +{ + int rc; + struct udevice *i2cdev; + + br_resetc_bmode(); + brdefaultip_setup(0, 0x57); + + rc = i2c_get_chip_for_busnum(0, 0x5D, 1, &i2cdev); + if (rc >= 0) + rc = dm_i2c_write(i2cdev, 0xEF, NULL, 0); + if (rc != 0) + printf("WARN: cannot write to LEDs!\n"); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + /* simple test if ram_size determined from fdt is plausible */ + gd->ram_size = get_ram_size((void *)gd->ram_base, gd->ram_size); + + zynq_ddrc_init(); + + return 0; +} diff --git a/board/BuR/zynq/brsmarc2/ps7_init_gpl.c b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c new file mode 100644 index 0000000..d4e20d9 --- /dev/null +++ b/board/BuR/zynq/brsmarc2/ps7_init_gpl.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/ps7_init_gpl.h> + +unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00500801U), + EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00500141U), + EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000503U), + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U, 0x00501903U), + EMIT_MASKWRITE(0XF8000160, 0x007F007FU, 0x00000000U), + EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U), + EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DFC4CDU), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001040U), + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004159AU), + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44D258D4U), + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0xB2024127U), + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x2B08B290U), + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000018U), + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040970U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U), + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284545U), + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x0020006AU), + EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x0001D400U), + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x0001C400U), + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x0001BC00U), + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x0001C800U), + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x0000007AU), + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007DU), + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x0000007EU), + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000CAU), + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000C6U), + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000C4U), + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000C7U), + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000BAU), + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BDU), + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000BEU), + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FD04U), + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00000700U), + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x000007A0U), + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U), + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000006E0U), + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00000302U), + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000303U), + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000205U), + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000204U), + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00000320U), + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00000320U), + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00000321U), + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000340U), + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000340U), + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U), + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U), + EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x00380037U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_MASKDELAY(0XF8F00200, 1), + EMIT_EXIT(), +}; + +unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0XF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} diff --git a/board/BuR/zynq/config.mk b/board/BuR/zynq/config.mk new file mode 100644 index 0000000..17e3d57 --- /dev/null +++ b/board/BuR/zynq/config.mk @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Hannes Schmelzer <oe5hpm(a)oevsv.at> - +# B&R Industrial Automation GmbH - http://www.br-automation.com +# + +hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE) | sed -e 's/zynq-//') + +payload_off :=$(shell printf "%d" $(CONFIG_SYS_SPI_U_BOOT_OFFS)) + +fpga_path := $(shell echo $(KBUILD_SRC)/board/$(BOARDDIR)/$(hw-platform-y)) +fpga_src := $(shell ls $(fpga_path)/*.bit 2>/dev/null) +fpga_file := $(shell echo $(fpga_src) | rev | cut -d/ -f1 | rev) +fpga_off := $(shell printf "%d" \ + $(shell cat $(fpga_path)/${fpga_file}.offset 2>/dev/null)) +flen_min := $(shell expr ${payload_off} + ${fpga_off}) + +quiet_cmd_prodbin = PRODBIN $@ $(payload_off) +cmd_prodbin = \ + dd if=/dev/zero bs=1 count=${flen_min} 2>/dev/null | tr "\000" "\377" >$@ && \ + dd conv=notrunc bs=1 if=spl/boot.bin of=$@ seek=0 2>/dev/null && \ + test -z ${fpga_src} && dd conv=notrunc bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null && \ + test -z ${fpga_src} || ( \ + dd conv=notrunc bs=1 if=u-boot-dtb.img of=$@ seek=$(payload_off) 2>/dev/null; \ + dd obs=1 if=$(fpga_file) of=$@ seek=$(fpga_off) 2>/dev/null \ + ) + +quiet_cmd_prodzip = SAPZIP $@ +cmd_prodzip = \ + test -d misc && rm -r misc; \ + mkdir misc && \ + cp spl/boot.bin misc/ && \ + cp u-boot-dtb.img misc/ && \ + zip -9 -r $@ misc/* >/dev/null $< + +quiet_cmd_fpga = FPGA $@ ($(fpga_file)) @ $(fpga_off) +cmd_fpga = test -z ${fpga_src} || cp ${fpga_src} $(fpga_file) + +$(hw-platform-y)_fpga: + $(call if_changed,fpga) + +$(hw-platform-y)_prog.bin: u-boot-dtb.img spl/boot.bin $(hw-platform-y)_fpga + $(call if_changed,prodbin) + +$(hw-platform-y)_prod.zip: $(hw-platform-y)_prog.bin + $(call if_changed,prodzip) + + +ALL-y += $(hw-platform-y)_prod.zip diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig new file mode 100644 index 0000000..b325eeb --- /dev/null +++ b/configs/brsmarc2_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="BuR" +CONFIG_SYS_CONFIG_NAME="brsmarc2" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SPL_GPIO_SUPPORT=y +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x20000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_ZYNQ_SDHCI_MAX_FREQ=100000000 +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=0 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run b_default" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_SPL_RAM_SUPPORT is not set +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="zynq-brsmarc2" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=30000000 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_NATSEMI=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/brsmarc2.h b/include/configs/brsmarc2.h new file mode 100644 index 0000000..0b37fcc --- /dev/null +++ b/include/configs/brsmarc2.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * specific parts for B&R brsmarc2 SoM + * + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm(a)oevsv.at> - + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ + +#ifndef __CONFIG_BRSMARC2_H__ +#define __CONFIG_BRSMARC2_H__ + +#include <configs/bur_cfg_common.h> + +/* Cache options */ +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +# define CONFIG_SYS_L2_PL310 +# define CONFIG_SYS_PL310_BASE 0xf8f02000 +#endif + +#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 +#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +/* Serial drivers */ +#define CONFIG_BAUDRATE 115200 +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* MMC */ +#define CONFIG_ZYNQ_HISPD_BROKEN + +/* USB */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +/* Environment */ +#define CONFIG_SYS_AUTOLOAD "no" + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_EXTRA_ENV_SETTINGS \ +BUR_COMMON_ENV \ +"board_id=0xFF\0" \ +"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ +"dtbaddr=0x4000000\0" \ +"loadaddr=0x2000000\0" \ +"fpgaaddr=fdt get value fpgabase /fpga bur,updaddr;" \ +" fdt get value fpgasize /fpga bur,updsize\0" \ +"fpga=setenv fpgastatus disabled; run fpgaaddr;" \ +" sf read ${loadaddr} ${fpgabase} ${fpgasize} &&" \ +" fpga loadb 0 ${loadaddr} ${fpgasize} && setenv fpgastatus okay\0" \ +"fpgastatus=disabled\0" \ +"fpgaupd=run fpgaaddr && tftp ${loadaddr} X20CP04xx.bit &&" \ +" sf erase ${fpgabase} +${filesize} &&" \ +" sf write ${loadaddr} ${fpgabase} ${filesize}\0" \ +"netupd=tftp ${loadaddr} boot.bin && sf probe &&" \ +" sf erase 0 +${filesize} && sf write ${loadaddr} 0 ${filesize} &&" \ +" tftp ${loadaddr} u-boot-dtb.img &&" \ +" sf erase 0x40000 +${filesize} && sf write ${loadaddr} 0x40000 ${filesize}\0" \ +"cfgscr=mw ${dtbaddr} 0;" \ +" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \ +" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ +"vxargs=setenv bootargs gem(0,0)host:vxWorks h=${serverip}" \ +" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \ +"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x10000;" \ +" fdt set /fpga status ${fpgastatus};" \ +" fdt boardsetup\0" \ +"startvx=run vxargs && mw 0x1100 0 && run vxfdt &&" \ +" bootm ${loadaddr} - ${dtbaddr}\0" \ +"b_break=0\0" \ +"b_tgts_std=mmc spi usb0 net0 net1\0" \ +"b_tgts_rcy=spi usb0 net0 net1\0" \ +"b_tgts_pme=usb0 net0 net1 mmc spi\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_mmc=run fpga; mmc dev 0; load mmc 0 ${loadaddr} arimg && run startvx\0" \ +"b_spi=run fpga; sf read ${loadaddr} 900000 700000 && run startvx\0" \ +"b_net0=tftp ${scradr} netscr-brsmarc2-${board_id}.img && source ${scradr}\0" \ +"b_net1=tftp ${scradr} netscript.img && source ${scradr}\0" \ +"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" + +#define CONFIG_SYS_LOAD_ADDR 0xC0000 /* + * default load and execution + * address for loads / scripts + */ +/* Support both device trees and ATAGs. */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_MACH_TYPE 0xFFFFFFFF + +/* Miscellaneous configurable options */ +#define CONFIG_CLOCKS +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) +/* Physical Memory map */ +#define CONFIG_SYS_TEXT_BASE 0x4000000 + +#define CONFIG_SYS_SDRAM_BASE 0 + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) + +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +/* SPL part */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_I2C_SUPPORT + +/* Disable dcache for SPL just for sure */ +#define CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_ZYNQ_QSPI +# define CONFIG_SPL_SPI_LOAD +#endif /* CONFIG_ZYNQ_QSPI */ + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SPL_TEXT_BASE 0x0 +/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ +#define CONFIG_SPL_MAX_SIZE 0x30000 +/* The highest 64k OCM address */ +#define OCM_HIGH_ADDR 0xffff0000 +/* Just define any reasonable size */ +#define CONFIG_SPL_STACK_SIZE 0x2000 +/* SPL stack position - and stack goes down */ +#define CONFIG_SPL_STACK (OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE) +/* On the top of OCM space */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_STACK + \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 +/* BSS setup */ +#define CONFIG_SPL_BSS_START_ADDR 0x100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#endif /* CONFIG_SPL_BUILD */ +#endif /* __CONFIG_BRSMARC2_H__ */ -- 2.7.4

3 3

[U-Boot] U-Boot/EBBR plugfest at ELC-EU?
by Grant Likely 21 Aug '19

21 Aug '19

Quick poll: who would be interested in a U-Boot/EBBR plugfest event collocates with ELC-EU this year (week of 28th Oct)? In the EBBR meetings we’ve tossed around the idea of an U-Boot/EBBR plugfest to work out compatibility issues between OS distros and upstream U-Boot SBC support. The idea is to get a number of SBCs supported by mainline U-Boot with UEFI features turned on, along with U-Boot & OS developers and hold a 1 day debug sprint to work out how many platforms can work with ‘stock’ OS images. Details to be worked out if this looks viable. I’ve asked the LF folks if they have space on either Thursday 31st Oct or Friday 1st Nov. They are checking availability, but no commitments have been made. It would help to know if this date and location is feasible. What do you think? Would you come to a plug fest attached to ELC-EU? Would you be interested in helping to organise? Or, is there another time & location that would work better? Cheers, g. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

10 19

[U-Boot] [PATCH 1/1] efi_loader: re-enable GRUB workaround on 32bit ARM
by Heinrich Schuchardt 20 Aug '19

20 Aug '19

GRUB on ARM 32bit prior to version 2.04 lacks proper handling of caches. In U-Boot v2019.04 a workaround for this was inadvertently removed. The workaround is currently also needed for booting on systems with caches that cannot be managed via CP15 (e.g. with an i.MX6 CPU). Re-enable the workaround and make it customizable. Fixes: f69d63fae281 ("efi_loader: use efi_start_image() for bootefi") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/Kconfig | 8 ++++++++ lib/efi_loader/efi_boottime.c | 28 +++++++++++++--------------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index a7f2c68fa9..c7027a9676 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -107,4 +107,12 @@ config EFI_HAVE_RUNTIME_RESET default y depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || SYSRESET_X86 +config EFI_GRUB_ARM32_WORKAROUND + bool "Workaround for GRUB on 32bit ARM" + default y + depends on ARM && !ARM64 + help + GRUB prior to version 2.04 requires U-Boot to disable caches. This + workaround currently is also needed on systems with caches that + cannot be managed via CP15. endif diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 4f6e8d1679..f75ca1a67c 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -39,14 +39,6 @@ LIST_HEAD(efi_register_notify_events); /* Handle of the currently executing image */ static efi_handle_t current_image; -/* - * If we're running on nasty systems (32bit ARM booting into non-EFI Linux) - * we need to do trickery with caches. Since we don't want to break the EFI - * aware boot path, only apply hacks when loading exiting directly (breaking - * direct Linux EFI booting along the way - oh well). - */ -static bool efi_is_direct_boot = true; - #ifdef CONFIG_ARM /* * The "gd" pointer lives in a register on ARM and AArch64 that we declare @@ -1911,13 +1903,21 @@ error: */ static void efi_exit_caches(void) { -#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#if defined(CONFIG_EFI_GRUB_ARM32_WORKAROUND) /* - * Grub on 32bit ARM needs to have caches disabled before jumping into - * a zImage, but does not know of all cache layers. Give it a hand. + * Boooting Linux via GRUB prior to version 2.04 fails on 32bit ARM if + * caches are enabled. + * + * TODO: + * According to the UEFI spec caches that can be managed via CP15 + * operations should be enabled. Caches requiring platform information + * to manage should be disabled. This should not happen in + * ExitBootServices() but before invoking any UEFI binary is invoked. + * + * We want to keep the current workaround while GRUB prior to version + * 2.04 is still in use. */ - if (efi_is_direct_boot) - cleanup_before_linux(); + cleanup_before_linux(); #endif } @@ -2893,8 +2893,6 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, if (ret != EFI_SUCCESS) return EFI_EXIT(EFI_INVALID_PARAMETER); - efi_is_direct_boot = false; - image_obj->exit_data_size = exit_data_size; image_obj->exit_data = exit_data; -- 2.20.1

3 4

[U-Boot] [PATCH v0] rockchip: rk3399: Add ROC-RK3399-PC support
by djw＠t-chip.com.cn 19 Aug '19

19 Aug '19

From: Levin Du <djw(a)t-chip.com.cn> Add initial support for ROC-RK3399-PC board. Specification - Rockchip RK3399 - LPDDR4 4GiB - eMMC slot - SD card slot - RTL8211E 1Gbps - HDMI Out, DP, MIPI DSI/CSI, EDP - PCIe M.2 - USB 2.0, USB-3.0 - USB C Type Commit details of rk3399-roc-pc.dts sync from Linux v5.2: "arm64: dts: rockchip: add support for ROC-RK3399-PC board" (sha1: 8bb878cf20ae10809c36db96993bfce7026d062b) Signed-off-by: Levin Du <djw(a)t-chip.com.cn> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 18 + arch/arm/dts/rk3399-roc-pc.dts | 680 +++++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 + configs/roc-rk3399-pc_defconfig | 61 +++ 5 files changed, 766 insertions(+) create mode 100644 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-roc-pc.dts create mode 100644 configs/roc-rk3399-pc_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f5535078c720..547f609e63b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -115,6 +115,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-puma-ddr1333.dtb \ rk3399-puma-ddr1600.dtb \ rk3399-puma-ddr1866.dtb \ + rk3399-roc-pc.dtb \ rk3399-rock-pi-4.dtb \ rk3399-rock960.dtb \ rk3399-rockpro64.dtb diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi new file mode 100644 index 000000000000..77d5cf5d3cd6 --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Levin Du <djw(a)t-chip.com.cn> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&vdd_log { + regulator-min-microvolt = <430000>; + regulator-init-microvolt = <950000>; +}; diff --git a/arch/arm/dts/rk3399-roc-pc.dts b/arch/arm/dts/rk3399-roc-pc.dts new file mode 100644 index 000000000000..19f7732d728c --- /dev/null +++ b/arch/arm/dts/rk3399-roc-pc.dts @@ -0,0 +1,680 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Board"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_vbus_typec0: vcc-vbus-typec0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_vbus_typec0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* + * should be placed inside mp8859, but not until mp8859 has + * its own dt-binding. + */ + vcc12v_sys: mp8859-dcdc1 { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc_vbus_typec0>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en &hub_rst>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_vbus_typec1: vcc-vbus-typec1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_vbus_typec1_en>; + regulator-name = "vcc_vbus_typec1"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb1: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; +}; + +&i2c7 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hub_rst: hub-rst { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb-typec { + vcc_vbus_typec1_en: vcc-vbus-typec1-en { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + fusb1_int: fusb1-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 3308b3595fd8..9b80db21ed96 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -31,6 +31,12 @@ F: configs/orangepi-rk3399_defconfig F: arch/arm/dts/rk3399-u-boot.dtsi F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi +ROC-RK3399-PC +M: Levin Du <djw(a)t-chip.com.cn> +S: Maintained +F: configs/roc-rk3399-pc_defconfig +F: arch/arm/dts/rk3399-roc-pc-u-boot.dtsi + ROCK-PI-4 M: Akash Gajjar <akash(a)openedev.com> M: Jagan Teki <jagan(a)amarulasolutions.com> diff --git a/configs/roc-rk3399-pc_defconfig b/configs/roc-rk3399-pc_defconfig new file mode 100644 index 000000000000..09e9b8a75642 --- /dev/null +++ b/configs/roc-rk3399-pc_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x50000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_TPL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.18.0

2 3

[U-Boot] [PATCH] core: ofnode: do not assert if node not valid in ofnode_get_name()
by Kever Yang 19 Aug '19

19 Aug '19

In some case with LIVE DT, some node always not valid, or not have a valid name, eg. blk driver add by mmc. Return fail instead of Assert for this kind of ofnode, and this help with assert happen from time to time when of_live is enabled and DEBUG is enabled. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- drivers/core/ofnode.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index c72c6e2673..bd338a4c68 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -212,7 +212,11 @@ ofnode ofnode_get_parent(ofnode node) const char *ofnode_get_name(ofnode node) { - assert(ofnode_valid(node)); + if (!ofnode_valid(node)) { + debug("%s node not valid\n", __func__); + return NULL; + } + if (ofnode_is_np(node)) return strrchr(node.np->full_name, '/') + 1; -- 2.17.1

2 4

[U-Boot] [PATCH v2 1/2] arm: dts: rock960: Enable booting from eMMC when using SPL
by Manivannan Sadhasivam 17 Aug '19

17 Aug '19

This commits enables booting from eMMC when using SPL on 96Boards Rock960 board by adding SDHCI to boot order. Since the SDHCI driver already has the reloc flag, this works straightaway. While we are at it, let's also include the common u-boot dtsi for rk3399. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam(a)linaro.org> --- Changes in v2: * Moved the change to <board>-u-boot.dtsi as spotted by Peter. arch/arm/dts/rk3399-rock960-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/rk3399-rock960-u-boot.dtsi b/arch/arm/dts/rk3399-rock960-u-boot.dtsi index 5256f6d3f2..4850debdf0 100644 --- a/arch/arm/dts/rk3399-rock960-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock960-u-boot.dtsi @@ -3,4 +3,11 @@ * Copyright (C) 2019 Jagan Teki <jagan(a)amarulasolutions.com> */ +#include "rk3399-u-boot.dtsi" #include "rk3399-sdram-lpddr3-2GB-1600.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = &sdhci, &sdmmc; + }; +}; -- 2.17.1

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[U-Boot] [PATCH 00/13] powerpc: Enable device tree support
by Z.q. Hou 16 Aug '19

16 Aug '19

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> This patch is to enable device tree support for the Freescale PowerPC platforms below. Hou Zhiqiang (13): powerpc: Enable device tree support for T2080RDB powerpc: Enable device tree support for T4240RDB powerpc: Enable device tree support for T1024RDB powerpc: Enable device tree support for T1042D4RDB powerpc: Enable device tree support for P1020RDB powerpc: Enable device tree support for P2020RDB powerpc: Enable device tree support for P2041RDB powerpc: Enable device tree support for P3041DS powerpc: Enable device tree support for P4080DS powerpc: Enable device tree support for P5040DS powerpc: dts: add default definition of CONFIG_RESET_VECTOR_ADDRESS powerpc: mpc8548cds: extend the reserved length for monitor powerpc: Enable device tree support for MPC8548CDS arch/powerpc/dts/Makefile | 12 +++ arch/powerpc/dts/e500mc_power_isa.dtsi | 33 ++++++ arch/powerpc/dts/e500v2_power_isa.dtsi | 26 +++++ arch/powerpc/dts/e5500_power_isa.dtsi | 34 +++++++ arch/powerpc/dts/mpc8548-post.dtsi | 27 +++++ arch/powerpc/dts/mpc8548.dtsi | 27 +++++ arch/powerpc/dts/mpc8548cds.dts | 23 +++++ arch/powerpc/dts/mpc8548cds_36b.dts | 23 +++++ arch/powerpc/dts/p1020-post.dtsi | 27 +++++ arch/powerpc/dts/p1020.dtsi | 31 ++++++ arch/powerpc/dts/p1020rdb-pc.dts | 23 +++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 23 +++++ arch/powerpc/dts/p1020rdb-pd.dts | 23 +++++ arch/powerpc/dts/p2020-post.dtsi | 27 +++++ arch/powerpc/dts/p2020.dtsi | 31 ++++++ arch/powerpc/dts/p2020rdb-pc.dts | 23 +++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 23 +++++ arch/powerpc/dts/p2041.dtsi | 63 ++++++++++++ arch/powerpc/dts/p2041rdb.dts | 18 ++++ arch/powerpc/dts/p3041.dtsi | 63 ++++++++++++ arch/powerpc/dts/p3041ds.dts | 18 ++++ arch/powerpc/dts/p4080.dtsi | 83 +++++++++++++++ arch/powerpc/dts/p4080ds.dts | 18 ++++ arch/powerpc/dts/p5040.dtsi | 62 +++++++++++ arch/powerpc/dts/p5040ds.dts | 18 ++++ arch/powerpc/dts/t1024rdb.dts | 17 ++++ arch/powerpc/dts/t102x.dtsi | 52 ++++++++++ arch/powerpc/dts/t1042d4rdb.dts | 17 ++++ arch/powerpc/dts/t104x.dtsi | 62 +++++++++++ arch/powerpc/dts/t2080rdb.dts | 17 ++++ arch/powerpc/dts/t4240.dtsi | 102 +++++++++++++++++++ arch/powerpc/dts/t4240rdb.dts | 17 ++++ arch/powerpc/dts/u-boot.dtsi | 3 + board/freescale/p1_p2_rdb_pc/README | 19 ++++ board/freescale/p2041rdb/README | 18 ++++ board/freescale/t102xrdb/README | 19 ++++ board/freescale/t104xrdb/README | 19 ++++ board/freescale/t208xrdb/README | 19 ++++ configs/MPC8548CDS_36BIT_defconfig | 3 + configs/MPC8548CDS_defconfig | 3 + configs/MPC8548CDS_legacy_defconfig | 3 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig | 2 + configs/P1020RDB-PC_SDCARD_defconfig | 2 + configs/P1020RDB-PC_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig | 2 + configs/P1020RDB-PD_SDCARD_defconfig | 2 + configs/P1020RDB-PD_SPIFLASH_defconfig | 2 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig | 2 + configs/P2020RDB-PC_SDCARD_defconfig | 2 + configs/P2020RDB-PC_SPIFLASH_defconfig | 2 + configs/P2020RDB-PC_defconfig | 3 + configs/P2041RDB_NAND_defconfig | 3 + configs/P2041RDB_SDCARD_defconfig | 3 + configs/P2041RDB_SPIFLASH_defconfig | 3 + configs/P2041RDB_defconfig | 3 + configs/P3041DS_NAND_defconfig | 3 + configs/P3041DS_SDCARD_defconfig | 3 + configs/P3041DS_SPIFLASH_defconfig | 3 + configs/P3041DS_defconfig | 3 + configs/P4080DS_SDCARD_defconfig | 3 + configs/P4080DS_SPIFLASH_defconfig | 3 + configs/P4080DS_defconfig | 3 + configs/P5040DS_NAND_defconfig | 3 + configs/P5040DS_SDCARD_defconfig | 3 + configs/P5040DS_SPIFLASH_defconfig | 3 + configs/P5040DS_defconfig | 3 + configs/T1024RDB_NAND_defconfig | 2 + configs/T1024RDB_SDCARD_defconfig | 2 + configs/T1024RDB_SPIFLASH_defconfig | 2 + configs/T1024RDB_defconfig | 3 + configs/T1042D4RDB_NAND_defconfig | 2 + configs/T1042D4RDB_SDCARD_defconfig | 2 + configs/T1042D4RDB_SPIFLASH_defconfig | 2 + configs/T1042D4RDB_defconfig | 3 + configs/T2080RDB_NAND_defconfig | 2 + configs/T2080RDB_SDCARD_defconfig | 2 + configs/T2080RDB_SPIFLASH_defconfig | 2 + configs/T2080RDB_defconfig | 3 + configs/T4240RDB_SDCARD_defconfig | 2 + configs/T4240RDB_defconfig | 3 + include/configs/MPC8548CDS.h | 2 +- 91 files changed, 1292 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/dts/e500mc_power_isa.dtsi create mode 100644 arch/powerpc/dts/e500v2_power_isa.dtsi create mode 100644 arch/powerpc/dts/e5500_power_isa.dtsi create mode 100644 arch/powerpc/dts/mpc8548-post.dtsi create mode 100644 arch/powerpc/dts/mpc8548.dtsi create mode 100644 arch/powerpc/dts/mpc8548cds.dts create mode 100644 arch/powerpc/dts/mpc8548cds_36b.dts create mode 100644 arch/powerpc/dts/p1020-post.dtsi create mode 100644 arch/powerpc/dts/p1020.dtsi create mode 100644 arch/powerpc/dts/p1020rdb-pc.dts create mode 100644 arch/powerpc/dts/p1020rdb-pc_36b.dts create mode 100644 arch/powerpc/dts/p1020rdb-pd.dts create mode 100644 arch/powerpc/dts/p2020-post.dtsi create mode 100644 arch/powerpc/dts/p2020.dtsi create mode 100644 arch/powerpc/dts/p2020rdb-pc.dts create mode 100644 arch/powerpc/dts/p2020rdb-pc_36b.dts create mode 100644 arch/powerpc/dts/p2041.dtsi create mode 100644 arch/powerpc/dts/p2041rdb.dts create mode 100644 arch/powerpc/dts/p3041.dtsi create mode 100644 arch/powerpc/dts/p3041ds.dts create mode 100644 arch/powerpc/dts/p4080.dtsi create mode 100644 arch/powerpc/dts/p4080ds.dts create mode 100644 arch/powerpc/dts/p5040.dtsi create mode 100644 arch/powerpc/dts/p5040ds.dts create mode 100644 arch/powerpc/dts/t1024rdb.dts create mode 100644 arch/powerpc/dts/t102x.dtsi create mode 100644 arch/powerpc/dts/t1042d4rdb.dts create mode 100644 arch/powerpc/dts/t104x.dtsi create mode 100644 arch/powerpc/dts/t2080rdb.dts create mode 100644 arch/powerpc/dts/t4240.dtsi create mode 100644 arch/powerpc/dts/t4240rdb.dts -- 2.17.1

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